DETAILED ACTION
This Office action is in response to the RCE filed 15 June 2026. Claims 7-26 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8 June 2026 has been entered.
Response to Arguments
Applicant's arguments filed 8 June 2026 have been fully considered but they are not persuasive; the rejections of the claims have been modified in response to Applicant's amendments to the claims. The amended limitations (and Applicant’s arguments regarding the amended limitations) are addressed by the modified rejections below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-13 and 21-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation “in a second direction perpendicular to the first direction and perpendicular to the top surface of the semiconductor layer” in lines 11-12. It is unclear how the “second direction” can be both “perpendicular to the first direction” and “perpendicular to the top surface of the semiconductor layer” as required by the limitation above, when the first direction is defined as “perpendicular to a top surface of the semiconductor layer” (line 8). For the purposes of examination, it is assumed the intended limitation requires the second direction to be perpendicular to the first direction and parallel to the top surface of the semiconductor layer. Claims 8-13 depend directly or indirectly from claim 7 and thus also contain the above indefinite language.
Claim 21 recites the limitation “a second direction perpendicular to the first direction and perpendicular to the bottom surface of the gate structure” in lines 9-10. It is unclear how the “second direction” can be both “perpendicular to the first direction” and “perpendicular to the bottom surface of the gate structure” as required by the limitation above, when the first direction is required to be “perpendicular to a bottom surface of the gate structure” (line 8). For the purposes of examination, it is assumed the intended limitation requires the second direction to be perpendicular to the first direction and parallel to the bottom surface of the gate structure. Claims 22-26 depend directly or indirectly from claim 21 and thus also contain the above indefinite language.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 7-12 and 14-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2017/0104097 A1 to Park.
Regarding independent claim 7, as best understood, Park (Fig. 6) discloses a semiconductor structure, comprising:
a semiconductor layer 510 (¶ 0118);
a first isolation structure 550a (¶ 0124) in the semiconductor layer;
a first gate structure 586a (¶ 0141) adjacent a first side of the first isolation structure;
a first source/drain region 524 (¶ 0117) adjacent a second side of the first isolation structure;
a second source/drain region 522 (¶ 0117) adjacent the first gate structure, wherein the first gate structure 586a is between the first source/drain region 524 and the second source/drain region 522 in a first direction perpendicular to a top surface of the semiconductor layer (direction from top to bottom in Fig. 6); and
a first conductive field plate 561a (¶ 0129) at least partially embedded in the first isolation structure 550a, wherein:
in a second direction (direction from left to right in Fig. 6) perpendicular to the first direction and [parallel] to the top surface of the semiconductor layer, a sidewall of the first conductive plate 561a is separated from a sidewall of the semiconductor layer 510 by the first isolation structure 550a (Fig. 6).
Regarding claim 8, Park (Fig. 6) discloses the semiconductor structure of claim 7, comprising: a dielectric layer (unlabelled in figure, 592/591/593 disposed thereon) over the semiconductor layer 510, over the first gate structure 586a, and over the first isolation structure 550a, wherein the first conductive field plate 561a is at least partially embedded in the dielectric layer (Fig. 6).
Regarding claim 9, Park (Fig. 6) discloses the semiconductor structure of claim 8, wherein the dielectric layer (unlabelled in figure, 592/591/593 disposed thereon) comprises: a first portion over a portion of the first gate structure 586a; a second portion over a portion of the first source/drain region 524; and a third portion over a portion of the first isolation structure 550a (Fig. 6).
Regarding claim 10, Park (Fig. 6) discloses the semiconductor structure of claim 7, comprising: a dielectric layer (unlabelled in figure, 592/591/593 disposed thereon) over the first gate structure 586a, the first source/drain region 524, and the first isolation structure 550a; and a contact 574 (¶ 0133) in the dielectric layer contacting the first source/drain region 524, wherein the first conductive field plate 561a is at least partially embedded in the dielectric layer (Fig. 6).
Regarding claim 11, Park (Fig. 6) discloses the semiconductor structure of claim 10, wherein the first conductive field plate 561a comprises: a line portion (portion of 561a extending from 591 to surface of 550a) embedded in the dielectric layer; and a plug portion (portion of 561a in 550a) embedded in the first isolation structure 550a (Fig. 6).
Regarding claim 12, Park (Fig. 6) discloses the semiconductor structure of claim 7, comprising: a second isolation structure 550a (portion containing 565a) in the semiconductor layer 510 adjacent the first gate structure 586a; and a second conductive field plate 565a (¶ 0129) at least partially embedded in the second isolation structure (Fig. 6).
Regarding independent claim 14, Park (Fig. 6) discloses a semiconductor structure, comprising:
a semiconductor layer 510 (¶ 0118);
a first isolation structure 550a (¶ 0124) in the semiconductor layer 510 over a first drift region 534 (¶ 0120);
a second isolation structure 552 (¶ 0122) in the semiconductor layer 510;
a first gate structure 586a (¶ 0141) adjacent a first side of the first isolation structure 550a in a first direction (direction going into Fig. 6) and over a first channel region 540 (¶ 0121) in a second direction (direction from top to bottom in Fig. 6) perpendicular to the first direction;
a first source/drain region 524 (¶ 0117) adjacent a second side of the first isolation structure 550a; and
a first conductive field plate 561a (¶ 0129) in the first isolation structure 550a over the first drift region 534 (¶ 0120), over the second isolation structure 552 (portions 561a are at a height above 552, thus “over” 552) and having a lowermost surface (bottom of 561a) below an uppermost surface of the first isolation structure 550a and above a lowermost surface of the first isolation structure 550a (Fig. 6), wherein the first isolation structure 550a is separated from the second isolation structure 552 in a third direction (direction left to right in Fig. 6) perpendicular to the first direction and the second direction (Fig. 6).
Regarding claim 15, Park (Fig. 6) discloses the semiconductor structure of claim 14, comprising: a second source/drain region 522 (¶ 0117) adjacent the first gate structure 586a (Fig. 6).
Regarding claim 16, Park (Fig. 6) discloses the semiconductor structure of claim 14, comprising: a dielectric layer (unlabelled in figure, 592/591/593 disposed thereon) over the first gate structure 586a, the first source/drain region 524, and the first isolation structure 550a; and a contact 574 (¶ 0133) in the dielectric layer contacting the first source/drain region 524, wherein the first conductive field plate 561a is at least partially embedded in the dielectric layer (Fig. 6).
Regarding claim 17, Park (Fig. 6) discloses the semiconductor structure of claim 14, comprising: a dielectric layer (unlabelled in figure, 592/591/593 disposed thereon) over the semiconductor layer 510, over the first gate structure 586a, and over the first isolation structure 550a, wherein the first conductive field plate 561a is at least partially embedded in the dielectric layer (Fig. 6).
Regarding claim 18, Park (Fig. 6) discloses the semiconductor structure of claim 17, wherein the first conductive field plate 561a comprises: a line portion (portion of 561a extending from 591 to surface of 550a) embedded in the dielectric layer; and a plug portion (portion of 561a in 550a) embedded in the first isolation structure 550a (Fig. 6).
Claims 21 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0088777 A1 to Lu et al. (hereinafter “Lu”).
Regarding independent claim 21, as best understood, Lu (Fig. 3) discloses a semiconductor structure, comprising:
a source/drain region 106 (¶ 0022);
a gate structure 210 (¶ 0032);
a first isolation structure 302 (¶ 0038) between the source/drain region 106 and the gate structure 210 in a first direction (direction from top to bottom in Fig. 3);
a first dielectric layer 124 (¶ 0033) over the gate structure 210 and the first isolation structure 302 (Fig. 3); and
a second isolation structure (portion of 118; ¶ 0034) between the source/drain region 106 and the gate structure 210 in the first direction (direction from top to bottom in Fig. 3) perpendicular to a bottom surface of the gate structure 210 and separated from the first isolation structure 302 in a second direction (direction from left to right in Fig. 3) perpendicular to the first direction and [parallel] to the bottom surface of the gate structure 210 (Fig. 3).
Regarding claim 22, Lu (Fig. 3) discloses the semiconductor structure of claim 21, comprising: a second dielectric layer 118 (¶ 0025) over the first dielectric layer 124 and the gate structure 210, wherein: the first dielectric layer 124 contacts a first portion of a top surface of the gate structure 210, and the second dielectric layer 118 contacts a second portion of the top surface of the gate structure 210 (Fig. 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claims 7 and 14 above, and further in view of US 2022/0293771 A1 to Lin et al. (hereinafter “Lin”).
Regarding claim 13, Park (Fig. 6) discloses the semiconductor structure of claim 7, comprising: a second isolation structure 552 (¶ 0122) in the semiconductor layer 510 adjacent the first source/drain region 524; a second gate structure 587a (¶ 0142) adjacent the second isolation structure.
Park fails to expressly disclose a third source/drain region adjacent the second gate structure; and a second conductive field plate at least partially embedded in the second isolation structure. In the same field of endeavor, Lin (Fig. 1) discloses a semiconductor structure including a second isolation structure 50 (¶ 0021) adjacent a first source/drain region 53 (¶ 0021); a second gate structure 52 (¶ 0021) adjacent the second isolation structure, a third source/drain region 42 (¶ 0020) adjacent the second gate structure; and a second conductive field plate 54 (¶ 0021). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park to include a shared source/drain region and device configuration as taught by Lin, the combination thus teaching a second conductive field plate at least partially embedded in the second isolation structure, for the purpose of providing a dual transistor, an art-recognized alternative high power device configuration (¶ 0021).
Regarding claim 19, Park (Fig. 6) discloses the semiconductor structure of claim 14, comprising: a second source/drain region 522 (¶ 0117) adjacent the first gate structure 586a.
Park fails to expressly disclose: the second isolation structure is over a second drift region; a second gate structure adjacent the second isolation structure over a second channel region; a third source/drain region adjacent the second gate structure; and a second conductive field plate in the second isolation structure over the second drift region and having a lowermost surface at depth of at least 50% of a thickness of the second isolation structure. In the same field of endeavor, Lin (Fig. 1) discloses a second isolation structure 50 (¶ 0021) in a semiconductor layer over a second drift region 26 (¶ 0020); a second gate structure 52 (¶ 0021) adjacent the second isolation structure over a second channel region 56 (¶ 0021); a third source/drain region 42 (¶ 0020) adjacent the second gate structure; and a second conductive field plate 54 (¶ 0021) over the second drift region 26 (Fig. 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park to include a shared source/drain region and device configuration as taught by Lin, the combination thus teaching a second conductive field plate in the second isolation structure, for the purpose of providing a dual transistor, an art-recognized alternative high power device configuration (¶ 0021).
The combination of Park and Lin fail to expressly disclose the second conductive field plate having a lowermost surface at depth of at least 50% of a thickness of the second isolation structure. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the recited lowermost surface depth, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F .2d 272, 205 USPQ 215 (CCPA 1980). Here, the conductive field plate lowermost surface depth is considered a result effective variable because it affects the contact area of the conductive field plate and the semiconductor structure’s breakdown voltage (¶¶ 0136-37) . Thus the ordinary artisan would have been motivated to modify the depth of the conductive field plate for the purpose of improving the breakdown voltage characteristics of the semiconductor structure.
Regarding claim 20, Park (Fig. 6) discloses the semiconductor structure of claim 14, however fails to expressly disclose: the lowermost surface of the first conductive field plate below the uppermost surface of the first isolation structure and above the lowermost surface of the first isolation structure is at a depth of at least 50% of a thickness of the first isolation structure. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the recited first conductive field plate lowermost surface depth, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F .2d 272, 205 USPQ 215 (CCPA 1980). Here, the conductive field plate depth is considered a result effective variable because it affects the contact area of the conductive field plate and the semiconductor structure’s breakdown voltage (¶¶ 0136-37). Thus, the ordinary artisan would have been motivated to modify the depth of the conductive field plate for the purpose of improving the breakdown voltage characteristics of the semiconductor structure.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Lu.
Regarding claim 23, Lu (Fig. 3) discloses the semiconductor structure of claim 22, wherein: the second dielectric layer 118 contacts a second portion of the top surface of the source/drain region 106, however fails to expressly disclose the first dielectric layer contacts a first portion of a top surface of the source/drain region. In other embodiments, Lu discloses a dielectric layer 406 contacting a first portion of a top portion of a top surface of the source drain region 106 (see Figs. 4, 9A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Lu to include a first dielectric layer as recited for the purpose of providing protection to the underlying region (¶ 0044).
Claims 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Lu as applied to claim 21 above, and further in view of Park.
Regarding claim 24, Lu discloses the semiconductor structure of claim 21, however fails to expressly disclose wherein the gate structure overlies a portion of the isolation structure. In the same field of endeavor, Park (Fig. 6) discloses a semiconductor structure including a gate structure 586a (¶ 0141) overlying a portion of an isolation structure 550a. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Lu to include the configuration of Park for the purpose of improving breakdown voltage characteristics without degradation of on-resistance characteristics (Park, ¶ 0136).
Regarding claim 25, Lu discloses the semiconductor structure of claim 21, including a conductive field plate 214 (¶ 0034), however fails to expressly disclose: the conductive field plate extending through the first dielectric layer and a portion of the isolation structure. In the same field of endeavor, Park (Fig. 6) discloses a conductive field plate 561a (¶ 0129) extending through a dielectric layer (unlabelled in figure; 592/591/593 disposed thereon) and a portion of the isolation structure 550a (¶ 0122). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Lu to include the conductive field plate disposed as taught by Park, the combination thus teaching the conductive field plate extending through the first dielectric layer, for the purpose of improving breakdown voltage by providing a conductive field plate in an art-recognized alternative manner (Park, ¶ 0005).
Regarding claim 26, Lu and Park disclose the semiconductor structure of claim 25, Park (Fig. 6) discloses further wherein the isolation structure 550a contacts a first sidewall of the conductive field plate 561a, a second sidewall of the conductive field plate, and a bottom surface of the conductive field plate (Fig. 6).
Conclusion
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CANDICE Y. CHAN
Examiner
Art Unit 2813
8 August 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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