Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
OFFICE ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) The claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) The claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 6-10, 14-20 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Inman (US 2014/0149715)
Regarding claim 1, the prior art discloses:
A method for determining layers for nodes in a circuit design (see abstract/summary and/or fig 1-9, 19-20), the method comprising:
identifying a plurality of structures in a circuit design, wherein each of the plurality of structures comprises four nodes of the circuit design and each of the four nodes are connected to every other node in the respective structure (fig 1-2, 4-9 show plurality of 4-node structures, each of the four nodes are directly or indirectly connected to every other node in the respective structure);
removing, from the plurality of structures, an even number of pairs of connected nodes of the circuit design to form a reduced node structure;
(see fig 5-7 as example, 2 pairs of layers of nodes in fig 5 (fig 5 has 12 nodes) have been removed to form a reduced node structure of 8 nodes as shown in fig 6 and/or 7)
assigning circuit layers for the nodes in the reduced node structure (see fig 6-7); and
assigning, by a processing device, circuit layers for the pairs of connected nodes removed from the plurality of structures based on the assigned circuit layers for the nodes in the reduced node structure (fig 6-7 show the reduced layers of nodes being assigned, i.e., Layer L1, Layer L2)
( Claim 2) wherein each of the pairs of connected nodes is shared by two of the plurality of structures (see fig 1-2, 4-8)
(Claim 6) wherein assigning the circuit layers for the pairs of connected nodes removed from the plurality of structures comprises, for each of the pairs of connected nodes, assigning a first node and a second node of the respective pair of connected nodes to different circuit layers (fig 5-9).
(Claim 7) wherein assigning the circuit layers for the pairs of connected nodes removed from the plurality of structures comprises, for each of the pairs of connected nodes, assigning circuit layers to the respective pair of connected nodes different from circuit layers assigned to another pair of connected nodes connected to the respective pair of connected nodes (fig 5-9).
(Claim 8) performing lithography (in terms of one or more of mask, pixel, place and route, physical design (par 75, 77, 86, 146-147, 151-152, , 199, 203, 226)) for the nodes and the pairs of connected nodes based on their assigned circuit layers.
Claims 9-10 and 14-16 recite similar subject matter and are rejected for the same reason.
Boarder claims 17-20 recite similar subject matter and are rejected for the same reason.
For nodes outside the identified even number of pairs of connected nodes in claim 17, see at least par 198, i.e., pair is sorted ascending on even nodes, and descending on odd nodes. Odd nodes are interpreted as outside even number of pairs of connected nodes.
Allowable Subject Matter
Claims 3-5 and 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 3-5 and 11-13 would be allowable because the prior art of record does not teach or suggest the limitations in claim 3 and similarly recited claim 11.
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL DINH whose telephone number is 571-272-1890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s Supervisor, Jack Chiang can be reached on 571-272-7483. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users.
To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format.
For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197(toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PAUL DINH/ Primary Examiner, Art Unit 2851