DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-10, 21, 23-29, and 31-32 are pending in the application and are currently being examined. Claims 1-2, 21, 23, and 27 have been amended. Claims 11-20, 22, and 30 have been canceled. New claims 31 and 32 have been added.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/23/2026 is being considered by the examiner.
Response to Arguments
Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. After reconsidering the references, Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections below.
Regarding the previous 112(b) rejections, the amendments are sufficient to overcome, and the 112(b) rejections are withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 27-29 and 31-32 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 27, lines 5-7 state “first and second spacers disposed on and in contact with a top surface of the fin base and sidewalls of the first and second nanostructured channel regions, respectively, wherein the sidewalls are facing each other”. However, the drawings and written description fail to describe spacers located in the claimed region. It appears the spacers in the claim most closely reference the gate spacers 126 which are at the sidewalls of the gate regions. For the purposes of examination, claim 27 will be interpreted to read “first and second spacers disposed on and in contact with a top surface of the fin base and sidewalls of first and second gate structures, respectively, wherein the sidewalls are facing each other” for lines 5-7, and “the first and second gate structures surround” in line 16.
Claims 28-29 and 31-32 are also rejected for being dependent on rejected claim 27.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 3, 8-9, 21, 23-25, 27-28, and 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 2018/0301564 A1, hereafter Kwon) in view of Iyer et al. (US 2007/0111538 A1, hereafter Iyer).
Regarding claim 1, Fig. 15A of Kwon teaches a semiconductor device, comprising:
a substrate (100, [0029]);
a fin base (AP, [0029]) disposed on the substrate (100);
nanostructured channel regions (CS, [0031]) disposed on a first portion (R1, [0029]) of the fin base (AP);
a gate structure (GE and GD, [0033]) surrounding the nanostructured channel regions (CS);
a source/drain (S/D) region (SD, [0036]) disposed on a second portion (R2, [0029]) of the fin base (AP);
an air spacer (AG, [0038]) disposed between the S/D region (SD) and the fin base (AP); and
a dielectric layer (growth prevention regions, 148a, [0075]) disposed between the air spacer (AG) and the fin base (AP).
Kwon does not explicitly teach wherein the dielectric layer comprises a first nitride layer comprising a first nitrogen concentration and disposed in the fin base; and a second nitride layer comprising a second nitrogen concentration higher than the first nitrogen concentration and disposed between the air spacer and the first nitride layer.
However, Kwon teaches the dielectric layer 148a can be a multilayer structure, which would include a dual-layered structure comprising a first silicon nitride as the lower layer (in the fin base) and a second silicon nitride as the upper layer (located between the air spacer and the first nitride layer [0075]. This dielectric is a growth prevention region in Kwon. As it is made of a dielectric material, this growth prevention region has the added benefit of isolating the source/drain regions from the substrate.
Iyer teaches a similar silicon nitride stack for isolation in Fig. 2F in which a first silicon nitride layer (of a lower nitrogen concentration due to processing parameters in [0034]) (206, [0026]) is covered by a second silicon nitride layer (of a higher nitrogen concentration due to processing parameters in [0038]) (208, [0026]). The reason the higher nitrogen concentration is placed on top is to prevent oxidation during other processing steps [0037] while also providing proper isolation to allow for higher transistor density [0004]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the growth prevention regions of Kwon to be two layered with silicon nitride layers of differing nitrogen concentrations for higher transistor density as taught by Iyer [0004].
Regarding claim 3, Kwon in view of Iyer teach the semiconductor device of claim 1, wherein:
the first nitride layer (lower layer of 148a of claim 1 comprising silicon nitride, [0075], of lower nitrogen content taught by Iyer’s layer 206 [0034]) comprises a silicon nitride layer with the first nitrogen concentration; and
the second nitride layer (upper layer of 148a of claim 1 comprising silicon nitride, [0075], of higher nitrogen content taught by Iyer’s layer 208 [0038]) comprises a silicon nitride layer with the second nitrogen concentration.
Regarding claim 8, Kwon in view of Iyer teach the semiconductor device of claim 1. Fig. 15A of Kwon further teaches:
a first spacer (146, [0039], see annotated Fig. 15A) disposed between a first portion of the gate structure (GE and GD, [0033], see annotated Fig. 15A) and the S/D region (SD, [0036]); and
a second spacer (146, see annotated Fig. 15A) disposed directly on the fin base (AP, [0029]) and between a second portion of the gate structure (see annotated Fig. 15A) and the air spacer (AG, [0038]).
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Regarding claim 9, Kwon in view of Iyer teach the semiconductor device of claim 1. Fig. 15A of Kwon further teaches a spacer (second spacer in annotated Fig. 15A) disposed directly on the fin base (AP, [0029]) and between the gate structure (GE and GD, [0033], second portion of gate structure in annotated Fig. 15A) and the dielectric layer (growth prevention regions, 148a, [0075]) (while not in the same vertical layer, the spacer is laterally between the second portion of the gate structure and the dielectric layer), wherein the spacer (146) and the dielectric layer (148a) comprise a same nitride material (146 may include silicon nitride or silicon oxynitride [0041]).
Regarding claim 21, Fig. 15A of Kwon teaches a semiconductor device, comprising:
a substrate (100, [0029]);
a fin base (AP, [0029]) disposed on the substrate (100);
nanostructured channel regions (CS, [0031]) disposed on the fin base (AP);
a gate structure (GE and GD, [0033]) surrounding the nanostructured channel regions (CS);
a source/drain (S/D) region (SD, [0036]) disposed on the fin base (AP);
an air spacer (AG, [0038]) with a curved cross-sectional profile disposed between the S/D region (SD) and the fin base (AP).
Kwon does not explicitly teach a first dielectric layer comprising a first nitrogen concentration and disposed between the air spacer and the fin base; and a second dielectric layer comprising a second nitrogen concentration higher than the first nitrogen concentration and disposed between the air spacer and the first dielectric layer.
However, Kwon teaches the dielectric layer 148a can be a multilayer structure, which would include a dual-layered structure comprising a first silicon nitride as the lower layer (in the fin base) and a second silicon nitride as the upper layer (located between the air spacer and the first nitride layer [0075]. This dielectric is a growth prevention region in Kwon. As it is made of a dielectric material, this growth prevention region has the added benefit of isolating the source/drain regions from the substrate.
Iyer teaches a similar silicon nitride stack for isolation in Fig. 2F in which a first silicon nitride layer (of a lower nitrogen concentration due to processing parameters in [0034]) (206, [0026]) is covered by a second silicon nitride layer (of a higher nitrogen concentration due to processing parameters in [0038]) (208, [0026]). The reason the higher nitrogen concentration is placed on top is to prevent oxidation during other processing steps [0037] while also providing proper isolation to allow for higher transistor density [0004]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the growth prevention regions of Kwon to be two layered with silicon nitride layers of differing nitrogen concentrations for higher transistor density as taught by Iyer [0004].
Regarding claim 23, Kwon in view of Iyer teach the semiconductor device of claim 21, wherein:
the first dielectric layer (lower layer of 148a of claim 1 comprising silicon nitride, [0075], of lower nitrogen content taught by Iyer’s layer 206 [0034]) comprises a silicon nitride layer with the first nitrogen concentration; and
the second dielectric layer (upper layer of 148a of claim 1 comprising silicon nitride, [0075], of higher nitrogen content taught by Iyer’s layer 208 [0038]) comprises a silicon nitride layer with the second nitrogen concentration.
Regarding claim 24, Fig. 15A of Kwon teaches the semiconductor device of claim 21, further comprising a gate spacer (146, [0039])disposed along a sidewall of one of the nanostructured channel regions (CS, [0031]), wherein the gate spacer (146) is in contact with the air spacer (AG, [0038]).
Regarding claim 25, Fig. 15A of Kwon teaches the semiconductor device of claim 21, further comprising:
a first spacer (146, [0039], see annotated Fig. 15A) disposed between a first portion of the gate structure (GE and GD, [0033], see annotated Fig. 15A) and the S/D region (SD, [0036]); and
a second spacer (146, [0039], see annotated Fig. 15A) disposed directly on the fin base (AP, [0029]) and between a second portion of the gate structure (GE and GD, see annotated Fig. 15A)and the air spacer (AG, [0038]).
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Regarding claim 27, Fig. 15A of Kwon teaches a semiconductor device, comprising:
a substrate (100, [0029]);
a fin base (AP, [0029]) disposed on the substrate (100);
first and second nanostructured channel regions (122, see annotated Fig. 15A, [0031]) disposed on the fin base (AP);
first and second spacers (146, [0039], see annotated Fig. 15A) disposed on and in contact with a top surface of the fin base (AP) and sidewalls of first and second gate structures (GE and GD, [0033], see annotated Fig. 15A), respectively, wherein the sidewalls are facing each other;
an air spacer (AG, [0038]) extending laterally between the first and second spacers (146);
a source/drain (S/D) region (SD, [0036]) disposed on the air spacer (AG); and
the first and second gate structures (GE and GD) surround the first and second nanostructured channel regions (122), respectively.
Kwon fails to explicitly disclose a first nitride layer comprising a first nitrogen concentration and disposed between the air spacer and the fin base;
a second nitride layer comprising a second nitrogen concentration higher than the first nitrogen concentration and disposed between the air spacer and the first nitride layer, wherein the second nitride layer extends laterally between the first and second spacers and sidewalls of the second nitride layer is in contact with the sidewalls of the first and second spacers.
However, Kwon teaches the dielectric layer 148a can be a multilayer structure, which would include a dual-layered structure comprising a first silicon nitride as the lower layer (in the fin base) and a second silicon nitride as the upper layer (located between the air spacer and the first nitride layer [0075]. This dielectric is a growth prevention region in Kwon. As it is made of a dielectric material, this growth prevention region has the added benefit of isolating the source/drain regions from the substrate.
Iyer teaches a similar silicon nitride stack for isolation in Fig. 2F in which a first silicon nitride layer (of a lower nitrogen concentration due to processing parameters in [0034]) (206, [0026]) is covered by a second silicon nitride layer (of a higher nitrogen concentration due to processing parameters in [0038]) (208, [0026]). The reason the higher nitrogen concentration is placed on top is to prevent oxidation during other processing steps [0037] while also providing proper isolation to allow for higher transistor density [0004]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the growth prevention regions of Kwon to be two layered with silicon nitride layers of differing nitrogen concentrations for higher transistor density as taught by Iyer [0004].
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Regarding claim 28, Kwon in view of Iyer teach the semiconductor device of claim 27, wherein the air spacer (AG of Kwon, [0038]) comprises a curved cross-sectional profile.
Regarding claim 31, Kwon in view of Iyer teach the semiconductor device of claim 27, wherein the first nitride layer (lower layer of 148a of claim 1 comprising silicon nitride, [0075], of lower nitrogen content taught by Iyer’s layer 206 [0034]) comprises a first dielectric constant; and
the second nitride layer (upper layer of 148a of claim 1 comprising silicon nitride, [0075], of higher nitrogen content taught by Iyer’s layer 208 [0038]) comprises a second dielectric constant greater than the first dielectric constant. It is known in the art that silicon nitride has a higher dielectric constant when the nitrogen concentration is increased.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Iyer, and further in view of Reznicek (US 10,170,638 B1).
Regarding claim 2, Kwon in view of Iyer teach the semiconductor of claim 1. Kwon in view of Iyer fail to teach a first portion of the dielectric layer extends into the fin base and a second portion of the dielectric layer extends above a top surface of the fin base.
However, Reznicek teaches in Fig. 8 a dual spacer structure (20L, 22, column 8, lines 39-20) in which a first portion of the dielectric layer extends into the fin base (see annotated Fig. 8) and a second portion of the dielectric layer extends above a top surface of the fin base (see annotated Fig. 8). The dielectric being above the fin base allows the dielectric to connect to the inner gate spacers (20S, column 8 line 24) to create better insulation between the source drain region and the substrate (column 11 lines 33-37). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the dielectric layer of Kwon in view of Iyer to have a portion extend above the fin base to provide better insulation as taught by Reznicek.
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Claim(s) 4-6 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Iyer as applied to claim 1 above, and further in view of Jung et al. (US 2020/0365692 A1, hereafter Jung).
Regarding claim 4, Kwon in view of Iyer teach the semiconductor device of claim 1. Kwon in view of Iyer fail to disclose the S/D region comprising S/D sub-regions disposed on sidewalls of the nanostructured channel regions and non-overlapping with each other.
However, Fig. 3 of Jung teaches a similar device with the S/D region (250, [0045]) comprising S/D sub-regions (230, [0045]) with candle-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions, with the subregions not overlapping with one another. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon in view of Iyer to include the layered S/D regions of Jung in order to minimize performance deterioration of the device [0052].
Regarding claim 5, Kwon in view of Iyer teach the semiconductor device of claim 1. Kwon in view of Iyer fail to disclose a doped S/D sub-region extending along a sidewall of the S/D region; and
undoped S/D sub-regions disposed on sidewalls of the nanostructured channel regions, wherein the undoped S/D sub-regions are separated from each other by the doped S/D sub-region.
However, Fig. 3 of Jung teaches a similar device with the S/D region (250, [0045]) comprising S/D sub-regions (230, [0045]) with candle-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions, with the subregions not overlapping with one another. Similarly, Jung indicates that element 230 may include n-type impurities, one of ordinary skill in the art would know that the impurities are not necessary, as that would still leave 240 with a higher concentration than 230. This means that the undoped subregions 230 are separated from one another by the doped subregion 240. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon in view of Iyer to include the layered S/D regions of Jung in order to minimize performance deterioration of the device [0052].
Regarding claim 6, Kwon in view of Iyer teach the semiconductor device of claim 1. Kwon in view of Iyer fail to disclose a first S/D sub-region disposed directly on the air spacer; and
second and third S/D sub-regions disposed directly on the air spacer and along opposite sidewalls of the first S/D sub-region.
However, Fig. 3 of Jung teaches a similar device with the S/D region (250, [0045]) comprising S/D sub-regions (here the second and third sub-regions, 230, [0045]) with candle-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions, with the subregions not overlapping with one another. Jung also discloses another subregion (here the first sub-region, 240, [0038]). While Jung does not show the second and third subregions being disposed on the air spacer, they are being placed in a similar position in Kwon in view of Iyer, making them placed on the air gap of Kwon (AG, [0038] of Kwon, see annotated Fig. 15A of Kwon). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon in view of Iyer to include the layered S/D regions of Jung in order to minimize performance deterioration of the device [0052].
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Regarding claim 10, Kwon in view of Iyer teach the semiconductor device of claim 1. Kwon also discloses in Fig. 2A spacers (146, [0039]) disposed between the gate structure (GE and GD, [0033]) and the S/D region (SD,[0036]), Kwon in view of Iyer fail to disclose the S/D region comprising:
first S/D sub-regions disposed on sidewalls of the nanostructured channel regions, and
a second S/D sub-region comprising first portions disposed on the first S/D sub-regions and second portions disposed on sidewalls of the spacers.
However, Fig. 3 of Jung teaches a similar device with the S/D region (250, [0045]) comprising S/D sub-regions (230, [0045]) with candle-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions, with the subregions not overlapping with one another. Jung also discloses another subregion (240, [0038]), which includes first portions (see annotated Fig. 3) disposed on the first S/D sub-regions (230) and second portions disposed on sidewalls of the spacers (see annotated Fig. 3). These epitaxial structures (230) structures and included to minimize performance deterioration of the device [0052]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon in view of Iyer to include the layered S/D regions of Jung.
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Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Iyer as applied to claim 1 above, in view of Jung and further in view of Bomberger et al. (US 2020/0303502 A1, hereafter Bomberger).
Regarding claim 7, Kwon in view of Iyer teach the semiconductor device of claim 1. Kwon in view of Iyer fail to disclose the S/D region comprising:
first S/D sub-regions with triangular-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions;
a pair of second S/D sub-regions disposed on the first S/D sub-regions, wherein sidewalls of the pair of second S/D sub-regions facing each other comprise zig-zag-shaped cross-sectional profiles; and
a third S/D sub-region disposed between the pair of second S/D sub-regions.
However, Fig. 3 of Jung teaches a similar device with the S/D region (250, [0045]) comprising S/D sub-regions (230, [0045]) with candle-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions. These epitaxial structures (230) structures are less doped than the surrounding 240 to minimize performance deterioration [0052]. While Jung teaches these regions 230 to be candle shaped, one of ordinary skill in the art would know that altering the shape of these regions to be triangles is merely a matter of choice, as evidenced by MPEP 2144.05:
“In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).” (MPEP 2144.04).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon to include the layered S/D regions of Jung and further modified to be a triangular shape depending on design choice.
Bomberger teaches a device similar to Kwon in view of Iyer and in further view of Jung. In Fig. 3H, Bomberger depicts a pair of second S/D sub-regions (nubs, 332, [0049]), wherein sidewalls of the pair of second S/D sub-regions facing each other comprise zig-zag-shaped cross-sectional profiles (while not sharp, nubs 332 seem to make a general zig-zag shape); and
a third S/D sub-region (conductive contact structure, 344, [0053]) disposed between the pair of second S/D sub-regions (332). These subregions are created within the S/D region to decrease contact area of the source or drain while having a low resistance [0024-25]
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of invention of Kwon in view of Iyer with the subregions taught by Jung, as well as the subregions taught by Bomberger.
Claim(s) 26 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Iyer, and further in view of Jung.
Regarding claim 26, Kwon in view of Iyer teach the semiconductor device of claim 21. Kwon in view of Iyer fail to disclose the S/D region comprising S/D sub-regions with triangular-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions.
However, Fig. 3 of Jung teaches a similar device with the S/D region (250, [0045]) comprising S/D sub-regions (230, [0045]) with candle-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions. These epitaxial structures (230) structures are less doped than the surrounding 240 to minimize performance deterioration [0052]. While Jung teaches these regions 230 to be candle shaped, one of ordinary skill in the art would know that altering the shape of these regions to be triangles is merely a matter of choice, as evidenced by MPEP 2144.05:
“In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).” (MPEP 2144.04).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon to include the layered S/D regions of Jung and further modified to be a triangular shape depending on design choice.
Regarding claim 29, Kwon in view of Iyer teach the semiconductor device of claim 27. Kwon in view of Iyer fail to disclose the S/D region comprises semiconductor layers with triangular-shaped cross-sectional profiles on sidewalls of the first and second nanostructured channel regions.
However, Fig. 3 of Jung teaches a similar device with the S/D region (250, [0045]) comprising S/D sub-regions (230, [0045]) with candle-shaped cross-sectional profiles disposed on sidewalls of the nanostructured channel regions. These epitaxial structures (230) structures are less doped than the surrounding 240 to minimize performance deterioration [0052]. While Jung teaches these regions 230 to be candle shaped, one of ordinary skill in the art would know that altering the shape of these regions to be triangles is merely a matter of choice, as evidenced by MPEP 2144.05:
“In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).” (MPEP 2144.04).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kwon to include the layered S/D regions of Jung and further modified to be a triangular shape depending on design choice.
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Iyer as applied to claim 27 above, and further in view of Jang et al. (US 2020/0220018 A1, hereafter Jang).
Regarding claim 32, Kim in view of Iyer teach the semiconductor device of claim 27. Kim in view of Iyer fail to teach a contact structure disposed on the S/D region, wherein the S/D region comprises:
first and second undoped S/D sub-regions disposed on the sidewalls of the first and second nanostructured channel regions, respectively;
a pair of doped S/D sub-regions extending vertically between the contact structure and the air spacer and disposed between the first and second undoped S/D sub-regions; and
a doped S/D sub-region extending vertically between the contact structure and the air spacer and disposed between the pair of doped S/D sub-regions.
However, Fig. 9 of Jang teaches a similar device with a contact structure (180, [0042]) disposed on the S/D region (150c, [0064]), wherein the S/D region (150c) comprises:
first and second undoped S/D sub-regions (151, [0058], see annotated Fig. 9) disposed on the sidewalls of the first and second nanostructured channel regions (CS of Kwon, [0031]), respectively; (epitaxial layer 151 of Jang is described as though it may include impurities, meaning the impurities are not necessary and may be excluded [0058])
a pair of doped S/D sub-regions (152c, [0064], see annotated Fig. 9) extending vertically between the contact structure (180) and the air spacer (AG of Kwon, [0038]) and disposed between the first and second undoped S/D sub-regions (151); (epitaxial layer 152 is described as having a higher impurity concentration compared to epitaxial layer 151, and as 151 is undoped, 152 would have to be doped [0058]) and
a doped S/D sub-region (154c, [0065]) extending vertically between the contact structure (180) and the air spacer (AG of Kwon) and disposed between the pair of doped S/D sub-regions (152) (epitaxial layer 154 is described as having a different type of impurity compared to epitaxial layer 152, implying 154 is doped as well).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the source/drain region of Kwon in view of Iyer to include the sub-regions taught by Jang in order to reduce short channel effects caused by diffusion of impurities ([0030] of Jang) and further include the source/drain contact of Jang to get the expected result of direct electrical contact to the device.
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Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892 /ERIC W JONES/Primary Examiner, Art Unit 2892
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