Prosecution Insights
Last updated: April 19, 2026
Application No. 18/128,129

Passive Device Dies With Measurement Structures

Final Rejection §103
Filed
Mar 29, 2023
Examiner
NGUYEN, DUY T V
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., Ltd.
OA Round
2 (Final)
79%
Grant Probability
Favorable
3-4
OA Rounds
2y 10m
To Grant
96%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
828 granted / 1052 resolved
+10.7% vs TC avg
Strong +17% interview lift
Without
With
+17.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
57 currently pending
Career history
1109
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
51.5%
+11.5% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
14.2%
-25.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1052 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Application 1. Acknowledgement is made of the amendment received on 1/8/2026. Claims 1-6, 8-16 & 21-25 are pending in this application. Claims 7 & 17-20 are canceled. Claim 25 is new. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 2. Claims 13, 15, 16 and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2017/0170224) in view of Kuo (US 2022/0310779, cited in IDS 12/16/2025) and Felber et al. (US 2004/0061111). Re claim 13, Huang teaches, under BRI, Figs. 6, 8 & 10, [0017, 0058, 0064, 0067, 0068, 0074, 0078], a structure, comprising: -a substrate (100-103); -first and second groups of trench capacitors (left & right 105-107) disposed on the substrate, wherein the first group of trench capacitors (left 105-107) comprises: a first trench capacitor with a first trench (first trench on left) having an elongated side extending a long a first direction, and a second trench capacitor with a second trench (second trench on left) having an elongated side extending a long a second direction; -a first conductive line (left 109) connected to the first group of trench capacitors; -a second conductive line (right 109) with first and second line portions (lower & upper portions), wherein the first line portion (lower portion) is connected to the second group of trench capacitors (left 105-107); -a first bonding structure (202) disposed on the first conductive line (109) and connected to the first group of trench capacitors (left 105-107); and -a second bonding structure (dielectric 201) disposed on the second line portion and electrically isolated (by 108) from the first and second groups of trench capacitors (105-107). PNG media_image1.png 338 424 media_image1.png Greyscale Huang does not explicitly teach the second direction substantially perpendicular to the first direction. Kou teaches, Fig. 1, [0015, the second direction (y axis) substantially perpendicular to the first direction (x axis) (between capacitance cells). As taught by Kou, one of ordinary skill in the art would utilize & modify the above teaching to obtain the second direction substantially perpendicular to the first direction in the first group of trench capacitors, because it aids in achieving a desired arrangement of multi-trench capacitance structure in a 2D grid. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kou in combination with Huang due to above reason. Huang/Kou does not explicitly teach first and second measurement structures disposed directly on the first and second conductive lines, respectively, and configured to measure electrical properties of the first and second groups of trench capacitors, respectively. Felber teaches, Fig. 2, “These capacitor plates 401, 402 are furthermore connected via interconnects 501, 502 to contact areas (not shown) which can be contact-connected to the needles of a test needle card” [0030]. As taught by Felber, one of ordinary skill in the art would utilize & modify the above teaching to obtain first and second measurement structures disposed directly on the first and second conductive lines, respectively, and configured to measure electrical properties of the first and second groups of trench capacitors, respectively as claimed, because it aids in achieving the highest possible yield of memory cells. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Felber in combination with Huang/Kou due to above reason. Re claim 15, Huang/Kou/Felber does not explicitly teach each of the first and second measurement structures comprises a metal layer. Felber does teach a contact area connected to interconnects (501, 502) and needles of a test needle card [0031] & “a current is impressed in order to determine whether a current flow takes place between the two capacitor rows” [0033]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Felber to obtain a metal layer as claimed, because metal layer is a known electrical conductor. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416. Re claim 16, in combination cited above, Felber teaches, Fig. 2, each trench capacitor in the first group of trench capacitors (rows 301) comprises a stack of capacitors electrically connected to each other in a parallel configuration. Re claims 21 & 24, Huang teaches, under BRI, Figs. 6, 8 & 10, [0017, 0058, 0064, 0065, 0067, 0068, 0074, 0078], a structure, comprising: -a substrate (100-103); -first and second groups of trench capacitors (left right 105-107) disposed in the substrate, wherein the first group of trench capacitors (left 105-107) comprises: a first trench capacitor with a first trench (first trench on left) having an elongated side extending a long a first direction, and a second trench capacitor with a second trench (second trench on left) having an elongated side extending a long a second direction; -a first interconnect line (left 109) disposed on the first group of trench capacitors; -a second interconnect line (right 109) disposed on the second group of trench capacitors; -a passivation layer (201) disposed on the first and second interconnect lines (left & right 109); -a first bonding structure (left portion of 200 and/or with 202) disposed on the first interconnect line (left 109) through the passivation layer (201); and -a second bonding structure (right portion of 200 and/or with 202) disposed on the second interconnect line (right 109) through the passivation layer (201). PNG media_image1.png 338 424 media_image1.png Greyscale Huang does not explicitly teach the second direction substantially perpendicular to the first direction. Kou teaches, Fig. 1, [0015, the second direction (y axis) substantially perpendicular to the first direction (x axis) (between capacitance cells). As taught by Kou, one of ordinary skill in the art would utilize & modify the above teaching to obtain the second direction substantially perpendicular to the first direction in the first group of trench capacitors, because it aids in achieving a desired arrangement of multi-trench capacitance structure in a 2D grid. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kou in combination with Huang due to above reason. Huang/Kou does not explicitly teach first and second measurement structures electrically connected to the first and second interconnect lines, respectively, wherein the first and second measurement structures are electrically isolated from each other; and wherein the first and second measurement structures are disposed directly on the first and second interconnect lines, respectively. Felber teaches, Fig. 2, “These capacitor plates 401, 402 are furthermore connected via interconnects 501, 502 to contact areas (not shown) which can be contact-connected to the needles of a test needle card” [0030]. As taught by Felber, one of ordinary skill in the art would utilize & modify the above teaching to obtain first and second measurement structures electrically connected to the first and second conductive lines, respectively, wherein the first and second measurement structures are electrically isolated from each other, and the first and second measurement structures are disposed directly on the first and second conductive lines, respectively as claimed, because it aids in achieving the highest possible yield of memory cells. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Felber in combination with Huang/Kou due to above reason. Re claim 22, Huang/Kou/Felber does not explicitly teach each of the first and second measurement structures comprises a metal layer. Felber does teach a contact area connected to interconnects (501, 502) and needles of a test needle card [0031] & “a current is impressed in order to determine whether a current flow takes place between the two capacitor rows” [0033]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Felber to obtain a metal layer as claimed, because metal layer is a known electrical conductor. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416. Re claim 23, in combination cited above, Felber teaches, Fig. 2, each trench capacitor in the first group of trench capacitors (rows 301) comprises a stack of capacitors electrically connected to each other in a parallel configuration. Re claim 25, Huang teaches, Fig. 10, wherein the second interconnect line (right 109) comprises: a first conductive portion (vertical portion of 109) connected to the second group of trench capacitors (right 105-107); a second conductive portion (horizontal portion of 109) connected to the second bonding structure (right 200, 202); and an insulating portion (of dielectric 108) disposed between the first and second conductive portions (in horizontal direction). 3. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Huang as modified by Kou/Felber as applied to claim 13 above, and further in view of Yamashita et al. (US 2006/0169484). The teachings of Huang/Kou/Felber have been discussed above. Re claim 14, Huang/Kou/Felber does not teach each of the first and second bonding structures comprises a metal pad and a solder ball. Yamashita teaches, Fig. 1, each of the first and second bonding structures comprises a metal pad (20) and a solder ball (30). As taught by Yamashita, one of ordinary skill in the art would utilize & modify the above teaching to obtain each of the first and second bonding structures comprises a metal pad and a solder ball as claimed, because solder ball is known and wildly used in to art as bonding structure. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yamashita in combination with Huang/Kou/Felber due to above reason. Allowable Subject Matter 4. Claims 1-6 & 8-12 are allowed including limitations “first and second measurement structures electrically connected to the first and second conductive lines, respectively, and configured to measure electrical properties of the first and second groups of trench capacitors, respectively, wherein the first and second measurement structures are electrically isolated from each other; and a third measurement structure electrically connected to the first group of trench capacitors and electrically isolated from the first measurement structure, wherein the first measurement structure is connected to a first voltage and the third measurement structure is connected to a second voltage higher than the first voltage” (claim 1). Response to Arguments 5. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection. Conclusion 6. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action; and/or Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the timing fee set forth in 37 CFR 1.17(p) on 12/16/2025 prompted the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 609.04(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/21/26
Read full office action

Prosecution Timeline

Mar 29, 2023
Application Filed
Oct 01, 2025
Non-Final Rejection — §103
Jan 06, 2026
Examiner Interview Summary
Jan 06, 2026
Applicant Interview (Telephonic)
Jan 08, 2026
Response Filed
Feb 23, 2026
Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12593539
DISPLAY DEVICE HAVING MULTI-WIDTH CONNECTION ELECTRODE
2y 5m to grant Granted Mar 31, 2026
Patent 12593657
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12593497
INTEGRATED CIRCUIT IN HYBRID ROW HEIGHT STRUCTURE
2y 5m to grant Granted Mar 31, 2026
Patent 12593436
VERTICALLY STACKED MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Mar 31, 2026
Patent 12588425
Systems, Articles, and Methods related to Multilayered Magnetic Memory Devices
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
79%
Grant Probability
96%
With Interview (+17.1%)
2y 10m
Median Time to Grant
Moderate
PTA Risk
Based on 1052 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month