DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 11/30/2025 have been fully considered but they are not persuasive.
Applicant argues on pages 8 and 9 that Shin does not have a device isolation layer 103 located between two gates GE and that also Lu does not provide for isolation structure 108 to not overlap with the second gates in top view.
Examiner respectfully disagrees. As mentioned below in the 112(b) rejection, the interpretation of “in” to make sense of the claim requires the “substrate” to encompass much more than just element 100 of the instant application but also includes the gate structures and ILD 170. Therefore, Shin teaches insulating structure 121 that is “in” the substrate and does not overlap with the second gates in a top view. Therefore, Examiner has updated the rejection below to include the amended portions of the claim and is maintaining the rejection.
Claim 21 has been given the same interpretation and can be found below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The newly amended portions to claim 1 makes unclear how to apply the term “in” within the recitation [1] “an insulating structure disposed in the substrate” which is different than how the term is applied in recitations [2] “a first gate disposed in the active region” and [3]“a plurality of second gates disposed in the resistor region.”
Recitation [2] and [3] uses the term in as being on and above while recitation [1] appears to imply an element being embedded inside another element. These diverging interpretations for the same term causes indefiniteness within the claims and requires correction. The only interpretation which allows for the claim to make sense is that if “substrate” does not only refer to element 100 in fig. 1 of the instant application but the refers to all the elements underneath element 175 of fig. 1 of the instant application.
Claim 21 recites similar limitations and therefore inherits the same indefiniteness issues mentioned above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al. (US PGPub 2019/0229062; hereinafter “Shin”).
Re claim 1: Shin teaches (e.g. figs. 1 and 2) a semiconductor device (device of fig. 2), comprising: a substrate (the elements from 151 down to base semiconductor 100; hereinafter “SUB”), defined with an active region (R1) and a resistor region (R2); a first gate (GE within R1; hereinafter “1G”) disposed in the active region (R1), wherein the first gate (1G) has a first length (length of 1G in direction D1; hereinafter “1L”) extending along a first direction (D1) and a second length (length of 1G in direction D2; hereinafter “2L”) extending along a second direction (D2); a plurality of second gates (GE within R2; hereinafter “2G”) disposed in the resistor region (R2), wherein each of the second gates (2G) has a third length (length of 2G in direction D1; hereinafter “3L”) extending along the first direction (D1) and a fourth length (length of 2G in direction D2; hereinafter “4L”) extending along the second direction (D2), the first length (1L) is equal to the third length (3L), and the second length (2L) is equal to the fourth length (4L); and a resistor (RS) disposed on the plurality of second gates (2G); and an insulating structure (gate spacer 121; e.g. paragraph 22) disposed in the substrate (SUB) and located between two of the second gates (2G), wherein the insulating structure (121) does not overlap with the two of the second gates (2G) in a top view of the semiconductor device (device of fig. 2).
Re claim 2: Shin teaches the semiconductor device of claim 1, wherein in a top view of the semiconductor device, the resistor (RS) has a first area A1 (area of RS), the plurality of second gates (2G) have a total area A2 (area of 2G), and the following relationship is satisfied: 0.14 ≤ A2/A1 ≤ 0.7 (the area of 2G is less than the area of RS, approximately 1/7th ).
Re claim 3: Shin teaches the semiconductor device of claim 1, wherein the resistor (RS) comprises doped polysilicon, metal nitrides (resistor material 163 of RS may include TiN, TaN; e.g. paragraph 39), metal oxides, or a combination thereof.
Re claim 4: Shin teaches the semiconductor device of claim 1, wherein a number of the first gates (three 1G) is greater than or equal to two, a first spaced distance (distance between 1G) is between two of the first gates (1G) adjacent to each other in the first direction (1D), a second spaced distance (distance between 2G) is between two of the second gates (2G) adjacent to each other in the first direction (1D), and the first spaced distance is equal to the second spaced distance (gate spacing between adjacent 1G is the same as the distance between adjacent 2G).
Re claim 5: Shin teaches the semiconductor device of claim 4, wherein a third spaced distance is between two of the first gates (1G) adjacent to each other in the second direction (D2), a fourth spaced distance is between two of the second gates (2G) adjacent to each other in the second direction (D2), and the third spaced distance is equal to the fourth spaced distance (the structure of fig. 1 repeats in an array, the spacing would be identical as the spacing in direction D1).
Re claim 21: Shin teaches (e.g. figs. 1 and 2) a semiconductor device (device of fig. 2), comprising: a substrate (the elements from 151 down to base semiconductor 100; hereinafter “SUB”), defined with an active region (R1) and a resistor region (R2); a first gate (GE within R1; hereinafter “1G”) disposed in the active region (R1), wherein the first gate (1G) has a first length (length of 1G in direction D1; hereinafter “1L”) extending along a first direction (D1) and a second length (length of 1G in direction D2; hereinafter “2L”) extending along a second direction (D2); a plurality of second gates (GE within R2; hereinafter “2G”) disposed in the resistor region (R2), wherein each of the second gates (2G) has a third length (length of 2G in direction D1; hereinafter “3L”) extending along the first direction (D1) and a fourth length (length of 2G in direction D2; hereinafter “4L”) extending along the second direction (D2), the first length (1L) is equal to the third length (3L), and the second length (2L) is equal to the fourth length (4L); and a resistor (RS) disposed on the plurality of second gates (2G); and an insulating structure (gate spacer 121; e.g. paragraph 22) disposed in the substrate (SUB) and located between two of the second gates (2G), wherein the insulating structure (121) has a fifth length (length of 121 in direction D1; hereinafter “5L”) in the first direction (D1), and the third length (3L) of the second gate (2G) is greater than (as can be seen in fig. 2, 121 is smaller in length than second gate 2G in the left-right direction of fig. 2) or equal to the fifth length (5L) of the insulating structure (121).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898