DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/14/2026 has been entered.
Response to Arguments
Applicant's arguments filed 4/14/2026 have been fully considered but they are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (US PGPub 2016/0020148; hereinafter “Song”) in view of Park et al. (US PGPub 2005/0095779; hereinafter “Park”).
Re claim 1: Song teaches (e.g. figs. 1 and 2A) a semiconductor device (device 100A), comprising: a substrate (semiconductor 101; e.g. paragraph 26), defined with an active region (transistor area TA; e.g. paragraph 26) and a resistor region (resistor area RA; e.g. paragraph 46); a first gate (active gate structures 110R; e.g. paragraph 26) disposed on the active region (TA), wherein the first gate (110R) has a first length (length of 110R in left-right direction of fig. 1; hereinafter “1L”) extending along a first direction (left-right direction of fig. 1; hereinafter “D1”) and a second length (length of 110R in up-down direction of fig. 1; hereinafter “2L”) extending along a second direction (up-down direction of fig. 1; hereinafter “D2”); a plurality of second gates (dummy gate structures 110D; e.g. paragraph 46) disposed on the resistor region (RA), wherein each of the second gates (110D) has a third length (length of 110D in direction D1; hereinafter “3L”) extending along the first direction (D1) and a fourth length (length of 110D in direction D2; hereinafter “4L”) extending along the second direction (D2), the first length (1L) is equal (see fig. 1) to the third length (3L), and the second length (2L) is equal (see fig. 1) to the fourth length (4L); and a resistor (resistor element 152; e.g. paragraph 53) disposed on the plurality of second gates (110D).
Song is silent as to explicitly teaching an insulating structure embedded inside the substrate and located between two of the second gates, wherein the insulating structure does not overlap with the two of the second gates in a top view of the semiconductor device, and a top surface of the insulating structure is flush with a top surface of the substrate.
Park teaches (e.g. fig. 9) a resistor structure 124a (e.g. paragraph 51) over gate structures DG1, PG1 in a peripheral region P and gate structures in region C and further teaches (e.g. fig. 9) an insulating structure (device isolation layer 102, 202; e.g. paragraph 36) embedded inside the substrate (substrate 100; e.g. paragraph 36) and located between two of the second gates (gate structure DG1,PG1 of Park; e.g. paragraph 40; equivalent to gate structures 110D of Song), wherein the insulating structure (102, 202) does not overlap with the two of the second gates (DG1, PG1) in a top view of the semiconductor device (device of fig. 9), and a top surface of the insulating structure (102, 202) is flush with a top surface of the substrate (100).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the isolation structures having planar surfaces with the substrate as taught by Park in the device of Song in order to have the predictable result of properly isolating the circuit and peripheral regions from each other while also providing a planar surface for subsequent structures to be formed on so that planarization processes to prevent unevenness is simplified.
Re claim 2: Song teaches the semiconductor device of claim 1, wherein in a top view of the semiconductor device, the resistor (152) has a first area A1 (area of 152), the plurality of second gates (110D) have a total area A2 (area of 110D), and the following relationship is satisfied: 0.14 ≤ A2/A1 ≤ 0.7 (the area of 110D is approximately 1/3 the area of 110D).
Re claim 3: Song in view of Park teaches the semiconductor device of claim 1, wherein the resistor (152) comprises doped polysilicon (tungsten silicide; e.g. paragraph 55 of Song), metal nitrides (TiN, TaN, TiSiN, TaSiN resistor material 124; e.g. paragraph 44 of Park), metal oxides, or a combination thereof.
Re claim 4: Song teaches the semiconductor device of claim 1, wherein a number of the first gates (three 110R) is greater than or equal to two, a first spaced distance (distance between 110R) is between two of the first gates (110R) adjacent to each other in the first direction (1D), a second spaced distance (distance between 110D) is between two of the second gates (110D) adjacent to each other in the first direction (1D), and the first spaced distance is equal to the second spaced distance (gate spacing between adjacent 110R is the same as the distance between adjacent 110D).
Re claim 5: Song teaches the semiconductor device of claim 4, wherein a third spaced distance is between two of the first gates (110R) adjacent to each other (the unit cell as shown in fig. 1 of Song would be repeated in the second direction D2, therefore, the spacing in the second direction between 110R would be the same as the spacing of 110D in the second direction D2) in the second direction (D2), a fourth spaced distance is between two of the second gates (110D) adjacent to each other in the second direction (D2), and the third spaced distance is equal to the fourth spaced distance (the structure of fig. 1 repeats in an array, the spacing would be identical as the spacing in direction D2).
Re claim 21: Song teaches (e.g. figs. 1 and 2A) a semiconductor device (device 100A), comprising: a substrate (semiconductor 101; e.g. paragraph 26), defined with an active region (transistor area TA; e.g. paragraph 26) and a resistor region (resistor area RA; e.g. paragraph 46); a first gate (active gate structures 110R; e.g. paragraph 26) disposed on the active region (TA), wherein the first gate (110R) has a first length (length of 110R in left-right direction of fig. 1; hereinafter “1L”) extending along a first direction (left-right direction of fig. 1; hereinafter “D1”) and a second length (length of 110R in up-down direction of fig. 1; hereinafter “2L”) extending along a second direction (up-down direction of fig. 1; hereinafter “D2”); a plurality of second gates (dummy gate structures 110D; e.g. paragraph 46) disposed on the resistor region (RA), wherein each of the second gates (110D) has a third length (length of 110D in direction D1; hereinafter “3L”) extending along the first direction (D1) and a fourth length (length of 110D in direction D2; hereinafter “4L”) extending along the second direction (D2), the first length (1L) is equal (see fig. 1) to the third length (3L), and the second length (2L) is equal (see fig. 1) to the fourth length (4L); and a resistor (resistor element 152; e.g. paragraph 53) disposed on the plurality of second gates (110D).
Song is silent as to explicitly teaching an insulating structure embedded inside the substrate and located between two of the second gates, wherein the insulating structure has a fifth length in the first direction, the third length of the second gate is greater than or equal to the fifth length of the insulating structure, and a top surface of the insulating structure is flush with a top surface of the substrate.
Park teaches (e.g. fig. 9) a resistor structure 124a (e.g. paragraph 51) over gate structures DG1, PG1 in a peripheral region P and gate structures in region C and further teaches (e.g. fig. 9) an insulating structure (device isolation layer 102, 202; e.g. paragraph 36) embedded inside the substrate (substrate 100; e.g. paragraph 36) and located between two of the second gates (gate structure DG1,PG1 of Park; e.g. paragraph 40; equivalent to gate structures 110D of Song), wherein the insulating structure (102, 202) has a fifth length (a length of 102, 202 in left-right direction of fig. 9 of Park; hereinafter “5L”) in the first direction (D1), the third length (3L) of the second gate (110D of Song/DG1,PG1 of Park) is greater than or equal to (there exists a length 3L from the entire length of 110D which is equal to the length 5L) the fifth length (5L) of the insulating structure (121), and a top surface of the insulating structure (102, 202) is flush with a top surface of the substrate (100).
an insulating structure (device isolation layer 102, 202; e.g. paragraph 36) embedded inside the substrate (substrate 100; e.g. paragraph 36) and located between two of the second gates (gate structure DG1,PG1 of Park; e.g. paragraph 40; equivalent to gate structures 110D of Song), wherein the insulating structure (102, 202) does not overlap with the two of the second gates (DG1, PG1) in a top view of the semiconductor device (device of fig. 9), and a top surface of the insulating structure (102, 202) is flush with a top surface of the substrate (100).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the isolation structures having planar surfaces with the substrate as taught by Park in the device of Song in order to have the predictable result of properly isolating the circuit and peripheral regions from each other while also providing a planar surface for subsequent structures to be formed on so that planarization processes to prevent unevenness is simplified.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
Prosecution Insights