DETAILED ACTION
Claim Rejections - 35 USC § 112
1. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
2. Claims 1 – 18 are rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as based on a disclosure which is not enabling. The disclosure does not enable one of ordinary skill in the art to practice the invention, which is/are critical or essential to the practice of the invention but not included in the claim(s). See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976).
The specification does not disclose the first insulating layer comprises a first region comprising a first sub-region entirely overlapped with overlapping the first source region and a second sub-region entirely overlapped with a normal region of the first gate and the first source region because connection electrodes CNE1, CNE2, CNE3, CNE4 connected through the first insulating layer (10 or 40 as shown in fig. 4A, or 4B). Therefore, the first insulating layer (10 or 40) comprises a first region comprising a first sub-region (cannot entirely) overlapped with overlapping the first source region and a second sub-region (cannot entirely) overlapped with a normal region of the first gate and the first source region.
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Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 1 – 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
In claim 1, lines 12 - 14, “the first insulating layer comprises a first region comprising a first sub-region entirely overlapped with overlapping the first source region and a second sub-region entirely overlapped with a normal region of the first gate and the first source region” is unclear as to whether it is being referred to “the first insulating layer comprises a first region comprising a first sub-region overlapped with overlapping the first source region and a second sub-region overlapped with a normal region of the first gate and the first source region” because connection electrodes CNE1, CNE2, CNE3, CNE4 connected through the first insulating layer (10 or 40 as shown in fig. 4A, or 4B). In order for further examination, “the first insulating layer comprises a first region comprising a first sub-region entirely overlapped with overlapping the first source region and a second sub-region entirely overlapped with a normal region of the first gate and the first source region” is assumed as “the first insulating layer comprises a first region comprising a first sub-region overlapped with overlapping the first source region and a second sub-region overlapped with a normal region of the first gate and the first source region”
In claim 1, lines 18 - 20, “at least a portion of the first sub-region and the second sub-region are disposed adjacent to each other with no first insulating layer having a thickness different from that of the first region” is unclear as to whether it is being referred to “at least portions of the first sub-region and the second sub-region are disposed adjacent to each other with a same thickness in the first region”
In claim 1, lines 14 - 16, “a distance from an upper portion of the semiconductor pattern to an upper portion of the gate in the first edge is smaller than a distance from the upper portion of the semiconductor pattern to an upper portion of the gate in the second edge” is unclear as to whether it is being referred to “a distance from an upper portion of the semiconductor pattern to an upper portion of the gate along the first edge is smaller than a distance from the upper portion of the semiconductor pattern to an upper portion of the gate along the second edge” because fig. 4B of Applicant discloses a distance from an upper portion of the semiconductor pattern (AA2) to an upper portion of the gate (GE2) along the first edge (e1) is smaller than a distance from the upper portion of the semiconductor pattern (AA2) to an upper portion of the gate along the second edge (e2). In order for further examination, “a distance from an upper portion of the semiconductor pattern to an upper portion of the gate in the first edge is smaller than a distance from the upper portion of the semiconductor pattern to an upper portion of the gate in the second edge” is assumed as “a distance from an upper portion of the semiconductor pattern to an upper portion of the gate along the first edge is smaller than a distance from the upper portion of the semiconductor pattern to an upper portion of the gate along the second edge”
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Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
6. Claim(s) 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (10367073).
With regard to claim 19, Liu et al. disclose a display panel (a panel including Fig. 5d; for example, see column 11, lines 4 - 7) comprising:
a base layer (101);
a light emitting element (a light emitting element including a cathode electrode 900; for example, see column 11, lines 35 - 37) arranged on the base layer (101);
a pixel circuit including a first transistor (a first transistor including a semiconductor pattern 300) and electrically connected to the light emitting element; and
a first insulating layer (420) arranged on the base layer (101), wherein the first transistor comprises:
a first semiconductor pattern (300) arranged between the base layer (101) and the insulating layer (420) and including a first source region (referred to as “300B” by examiner’s annotation shown in fig. 5d below), a first drain region (referred to as “300C” by examiner’s annotation shown in fig. 5d below), and a first channel region (referred to as “300A” by examiner’s annotation shown in fig. 5d below) arranged between the first source region (300B) and the first drain region (300C), and
a first gate (500) overlapping the channel region (300A) and arranged on the first insulating layer (420), and
wherein the gate (500) comprises a first edge (referred to as “E1” by examiner’s annotation shown in fig. 5d below) disposed adjacent to the source region (300B) and a second edge (referred to as “E2” by examiner’s annotation shown in fig. 5d below) disposed adjacent to the drain region (300C), and wherein a distance (referred to as “D1” by examiner’s annotation shown in fig. 5d below) from an upper portion (referred to as “500A1” by examiner’s annotation shown in fig. 5d below; wherein the upper portion 500A1 is formed on the lower edge surface of a lateral gate portion) of the semiconductor pattern (300) to an upper portion of the gate (500) along the first edge (E1) is smaller than a distance (referred to as “D2” by examiner’s annotation shown in fig. 5d below) from the upper portion (500A1) of the semiconductor pattern (300) to an upper portion (referred to as “500A2” by examiner’s annotation shown in fig. 5d below; wherein the upper portion 500A2 is a top surface of another lateral gate portion) of the gate (500) along the second edge (E2).
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Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claim(s) 1 – 11, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (11901461) in view of Liu et al. (10367073).
With regard to claim 1, Jang et al. disclose a display panel (a panel 210, fig. 11 including Fig. 14) comprising:
a light emitting element (710);
a pixel circuit including a first transistor (TR2) and electrically connected to the light emitting element (710); and
a first insulating layer (140), wherein the first transistor (TR2) comprises:
a first semiconductor pattern (A2) arranged under the first insulating layer (140) and including a first source region (referred to as “SR1” by examiner’s annotation shown in fig. 14 below), a first drain region (referred to as “DR1” by examiner’s annotation shown in fig. 14 below), and a first channel region (a region, formed between the source region SR1 and the drain region DR1 and forming under the gate G2, functioning as a first channel region) arranged between the first source region (SR1) and the first drain region (DR1), and
a first gate (G2) arranged on the first insulating layer (140) and overlapping the first channel region (the region, formed between the source region SR1 and the drain region DR1 and forming under the gate G2, functioning as the first channel region), and
wherein the first insulating layer (140) comprises a first region (a first region including first and second sub-regions 140A1, 140A2 as annotated in fig. 14 below) including a first sub-region (referred to as “140A1” by examiner’s annotation shown in fig. 14 below) overlapped with the first source region (SR1) and a second sub-region (referred to as “140A2” by examiner’s annotation shown in fig. 14 below) overlapped with a normal region (referred to as “G2A1” by examiner’s annotation shown in fig. 14 below) of the first gate (G2) and the first source region (SR1), and a second region (referred to as “140B” by examiner’s annotation shown in fig. 14 below) which overlaps a protruding region (referred to as “G2A2” by examiner’s annotation shown in fig. 14 below) of the first gate (G2), is disposed close to the first drain region (DR1) than the first region (SR1);
wherein at least a portion of the first sub-region (140A1) and the second sub-region (140A2) are disposed adjacent to each other with no the first insulating layer (140) having a thickness different from that of the first region (the first region including the first and second sub-regions 140A1, 140A2 as annotated in fig. 14 below).
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Jang et al. do not clearly disclose a second region of the first insulating layer, has a thickness greater than that of the first region of the first insulating layer.
However, Liu et al. discloses a second region (referred to as “402” by examiner’s annotation shown in fig. 5d below) of the first insulating layer (420), has a thickness greater than that of the first region (referred to as “420A” by examiner’s annotation shown in fig. 5d below) of the first insulating layer (420).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Jang et al.’s device to have a second region of the first insulating layer, has a thickness greater than that of the first region of the first insulating layer as taught by Liu et al. in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 2, Jang et al. disclose the first sub-region (140A1) of the first region and the second sub-region (140A2) of the first region have a uniform thickness.
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With regard to claim 3, Liu et al. disclose the first insulating layer (420) has a uniform thickness in the second region (402), and wherein the first region (420A as indicated in fig. 5d below) and the second region (402) forms a step in a region overlapping the channel region (300A as indicated in fig. 5d below).
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With regard to claim 6, Liu et al. disclose the first insulating layer (420) further comprises a third region (referred to as “420F” by examiner’s annotation shown in fig. 5d below) overlapping the first drain region (300C) and having a smaller thickness than the second region (402), and wherein the second region (402) forms a step with the third region (420F).
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With regard to claim 4, Liu et al. disclose the second region (420E) comprises: a first sub-region (referred to as “420C” by examiner’s annotation shown in fig. 5d below) having a first thickness and forming a step with the first region (420A); and a second sub-region (referred to as “420D” by examiner’s annotation shown in fig. 5d below) having a second thickness larger than the first thickness and forming a step with the first sub-region (420C).
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With regard to claim 5, Liu et al. disclose the first insulating layer (420) in the second region (420E) has a thickness gradually increasing (increasing from the middle portion of the insulating layer 420 to the region 402) towards the first drain region (300C).
With regard to claim 7, Liu et al. disclose a thickness of the first insulating layer (420) in the third region (420F) is the same as the thickness of the first insulating layer (420) in the first region (420A).
With regard to claim 8, Figure 5d of the Liu et al. reference (shown below) does appear to show in a cross-sectional view, a length (referred to as “X2” by examiner’s annotation shown in fig. 5d below) of the second region in a channel length direction is at most half of a length (referred to as “X1” by examiner’s annotation shown in fig. 5d below) of the first channel region in the channel length direction, as claimed. However, since the patent drawings are not labeled as “to scale,” one cannot be certain that a length of the second region in a channel length direction is at most half of a length of the first channel region in the channel length direction, as seemingly shown [see MPEP 2125].
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It would have been obvious to one having ordinary skill in the art at the time of the claimed invention to form a length of the second region in a channel length direction is at most half of a length of the first channel region in the channel length direction, because Fig. 5d suggests a length of the second region in a channel length direction is at most half of a length of the first channel region in the channel length direction and a prima facie case of obviousness exists where device dimensions of the prior art are such that one of ordinary skill in the art would have expected them to have the same performance {MPEP 2144.04(IV)(A)}.
With regard to claim 9, Figure 5d of the Liu et al. reference (shown below) does appear to show a thickness of the first insulating layer (420) in the second region (402) is at most two times greater than the thickness of the first insulating layer (420) in the first region (420A), as claimed. However, since the patent drawings are not labeled as “to scale,” one cannot be certain that a thickness of the first insulating layer in the second region is at most two times greater than the thickness of the first insulating layer in the first region, as seemingly shown [see MPEP 2125].
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It would have been obvious to one having ordinary skill in the art at the time of the claimed invention to form a thickness of the first insulating layer in the second region is at most two times greater than the thickness of the first insulating layer in the first region, because Fig. 5d suggests a thickness of the first insulating layer in the second region is at most two times greater than the thickness of the first insulating layer in the first region and a prima facie case of obviousness exists where device dimensions of the prior art are such that one of ordinary skill in the art would have expected them to have the same performance {MPEP 2144.04(IV)(A)}.
With regard to claim 10, Jang et al. disclose a second transistor (TR1), wherein the second transistor (TR1) comprises: a second semiconductor pattern (A1) arranged on the same layer (A1, A2) as the first semiconductor pattern (A2) and including a second source region (a source region forming under the source electrode S1), a second drain region (a drain region forming under the drain electrode D1), and a second channel region (a middle region of the second semiconductor pattern A1) arranged between the second source region and the second drain region, and a second gate (G1) overlapping the second channel region and arranged on the same layer (G1, G2) as the first gate (G2), and wherein the first semiconductor pattern (A2) and the second semiconductor pattern (A1) include the same material and include any one of polysilicon and oxide semiconductor (the active layer A1, A2 includes a silicon semiconductor layer 130a, and an oxide semiconductor layer 130b which contacts the silicon semiconductor layer 130a).
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With regard to claim 12, Jang et al. disclose the first insulating layer (140) has a uniform thickness in a region (referred to as “140B1” by examiner’s annotation shown in fig. 14 below) overlapping the second semiconductor pattern (A1).
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With regard to claim 18, Liu et al. disclose a second insulating layer (610) arranged on the first insulating layer (420) and covering the first gate (500); a first connection electrode (710) arranged on the second insulating layer (610) and connected to the first source region (300B as indicated in fig. 5d below) through a first contact hole formed in the first insulating layer (420) and the second insulating layer (610); and a second connection electrode (720) arranged on the second insulating layer (710) and connected to the first drain region (300C as indicated in fig. 5d below) through a second contact hole formed in the first and second insulating layers (420, 610).
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9. Claims 14, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (11901461) in view of Luo et al. (12074174).
With regard to claim 14, Jang et al. disclose an upper insulating layer (170) arranged on the first gate (G2); and a second transistor (TR1), wherein the second transistor (TR1) comprises: a second semiconductor pattern (A2) including a second source region (a source region forming under the source electrode S1), a second drain region (a drain region forming under the drain electrode D1), and a second channel region (a middle region of the second semiconductor pattern A1) arranged between the second source region and the second drain region, and a second gate (G2) arranged on (on the bottom) the upper insulating layer (170) and overlapping the second channel region, and wherein the first semiconductor pattern (A2) and the second semiconductor pattern (A1) include any one of polysilicon and oxide semiconductor (the active layer A1, A2 includes a silicon semiconductor layer 130a, and an oxide semiconductor layer 130b which contacts the silicon semiconductor layer 130a), but Jang et al. do not clearly disclose a second semiconductor pattern arranged between the first insulating layer and the upper insulating layer.
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However, Luo et al. discloses a second semiconductor pattern (213) arranged between the first insulating layer (300) and the upper insulating layer (400).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Jang et al.’s device to have a second semiconductor pattern arranged between the first insulating layer and the upper insulating layer as taught by Luo et al. in order to improve the electrical performance of the thin-film transistor for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 16, Luo et al. disclose the upper insulating layer (400) has a uniform thickness in a region overlapping the second semiconductor pattern (213).
10. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (11901461) in view of Yang (10895774).
With regard to claim 13, Jang et al. do not clearly disclose the first transistor is a switching transistor and the second transistor is a driving transistor.
However, Yang discloses the first transistor is a switching transistor and the second transistor is a driving transistor (both the low temperature polysilicon thin film transistor and the oxide thin film transistor can be used as a driving transistor DTFT or a switching transistor STFT; for example, see column 9, lines 7 - 10).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Jang et al. device to have the first transistor is a switching transistor and the second transistor is a driving transistor as taught by Yang in order to obtain the low-temperature in the transistor for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Response to Arguments
11. Applicant’s arguments filed 01/16/26 have been fully considered but they are not persuasive.
It is argued, at pages of the remarks, that “the cited reference does not suggest or teach “a distance from an upper portion of the semiconductor pattern to an upper portion of the gate in the first edge is smaller than a distance from the upper portion of the semiconductor pattern to an upper portion of the gate in the second edge”. However, fig. 5d of Liu et al. does show the gate (500) comprises a first edge (referred to as “E1” by examiner’s annotation shown in fig. 5d below) disposed adjacent to the source region (300B) and a second edge (referred to as “E2” by examiner’s annotation shown in fig. 5d below) disposed adjacent to the drain region (300C), and wherein a distance (referred to as “D1” by examiner’s annotation shown in fig. 5d below) from an upper portion (referred to as “500A1” by examiner’s annotation shown in fig. 5d below; wherein the upper portion 500A1 is formed on the lower edge surface of a lateral gate portion) of the semiconductor pattern (300) to an upper portion of the gate (500) along the first edge (E1) is smaller than a distance (referred to as “D2” by examiner’s annotation shown in fig. 5d below) from the upper portion (500A1) of the semiconductor pattern (300) to an upper portion (referred to as “500A2” by examiner’s annotation shown in fig. 5d below; wherein the upper portion 500A2 is a top surface of another lateral gate portion) of the gate (500) along the second edge (E2).
Response to Amendment
12. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
5. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
3. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812