Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over Delacruz et al. [US 2020/0402913 A1] in view of Hou et al. [US 2022/0262742 A1].
As per claim 1, Delacruz et al. teach a device, comprising:
an interposer [0012 interconnect device, 0013-0014 interconnect area, 0023 formed as interposers, element 304 in FIG. 3 and paragraphs 0031-0032]; and
four integrated circuits (ICs) disposed on the interposer [0015 four chips are connected, chips A-D in FIG. 2] in a 2x2 configuration [as depicted in FIG. 2 and FIGS. 3-5], wherein each of the four ICs is connected via the interposer to neighboring ICs on two sides [0024 connecting multiple chips using an interconnect device, interconnect areas, stitching of reticles, paragraphs 0025-0026 interconnect areas 2A-2D in FIG. 2, see also FIGS. 3-5 paragraphs 0031-0035 and 0042].
However, Delacruz et al. do not teach specifically teach a horizontal stitch and a vertical stitch formed from overlapping exposure areas.
Hou et al. teach an interposer with a horizontal stitch and a vertical stitch [0029 may run predominantly horizontally, vertically, or a mix, 0030 stitching process] formed from overlapping exposure areas [paragraphs 0036-0038 overlapping areas 138o, paragraph 0047].
Thus, considering that Delacruz et al. teach upcoming techniques such as reticle stitching appear promising [0024] and devices can be integrated in a lower cost interposer with much finer pitch [0042], the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains by combining with Hou et al. because the stitching process forms a metallization that has a greater footprint than available for the light mask used to expose the photomask [0030, also in paragraph 0090 any number of pattern regions may be stitched together].
2. The device of claim 1, wherein a total surface area of the interposer is greater than a maximum reticle field corresponding to the exposure areas [Hou et al. 0030 greater footprint than available].
3. The device of claim 2, wherein the total surface area of the interposer is at least three times a size of the maximum reticle field [Hou et al. paragraphs 0030, 0063, 0067, 0082, 0092 allows for a larger footprint, it is thus interpreted that at least three times a size is an obvious design choice dependent upon the user relative to manufacturing equipment].
4. The device of claim 2, wherein the horizontal stitch and the vertical stitch are formed by slightly overlapping four exposure areas, wherein each of the four exposure areas is at or below the maximum reticle field [Hou et al. 0047 any number of regions may be combined in the stitching process adjacent to each other horizontally and/or vertically, FIG. 46 and paragraph 0085 depict four, 0090, paragraphs 0030 and 0092 greater footprint than available].
5. The device of claim 1, wherein a first pair of the four ICs has a same design, and a second pair of the four ICs has a same design, wherein the design of the first pair is different from the design of the second pair, wherein a first IC of the first pair has a 180 degree orientation relative to a second IC of the first pair, and a third IC of the second pair has a 180 degree orientation relative to a fourth IC of the second pair [Delacruz et al. 0012 different dies such that the connections may provide high bandwidth signaling, 0031 combined device, 0034-0035 by rotating chips interconnect areas align, Hou et al. 0010 encompass different orientations, rotated, paragraphs 0057, 0090; although the term “pair” is not explicitly recited it is interpreted that such is dependent on the intended configuration for manufacture].
6. The device of claim 5, wherein the design of the first pair is a mirror of the design of the second pair [although the terms “pair” and “mirror” are not explicitly recited it is interpreted that such is dependent on the intended configuration for manufacture knowing that devices often comprise symmetric features].
7. The device of claim 1, wherein the four ICs have a same design, wherein a first IC of the four ICs has a 90 degree orientation relative to a second IC of the four ICs, a third IC of the four ICs has a 180 degree orientation relative to the second IC of the four ICs, and a fourth IC of the four ICs has a 270 degree orientation relative to the second IC of the four ICs [Delacruz et al. 0012 different dies such that the connections may provide high bandwidth signaling, 0031 combined device, 0034-0035 by rotating chips interconnect areas align, Hou et al. 0010 encompass different orientations, rotated, paragraphs 0057, 0090].
8. The device of claim 7, wherein the first and second ICs both have defects, wherein portions of the first and second ICs having the defects are disposed in an unused portion of the device [Hou et al. 0083 to increase yield, it is interpreted that in order to have a working device defects are to be disposed in unused portions].
9. The device of claim 1, wherein the four ICs have a same design, wherein the four ICs have rotational symmetry such they can be arranged in any orientation on the interposer without changing their function or performance [Delacruz et al. 0012 different dies such that the connections may provide high bandwidth signaling, 0031 combined device, 0034-0035 by rotating chips interconnect areas align, Hou et al. 0010 encompass different orientations, rotated, paragraphs 0057, 0090].
As per claim 10, Delacruz et al. teach a method, comprising:
forming an interposer [0012 interconnect device, 0013-0014 interconnect area, 0023 formed as interposers, element 304 in FIG. 3 and paragraphs 0031-0032]
disposing four ICs on the interposer [0015 four chips are connected, chips A-D in FIG. 2] in a 2x2 configuration [as depicted in FIG. 2 and FIGS. 3-5], wherein each of the four ICs is connected via the interposer to neighboring ICs on two sides [0024 connecting multiple chips using an interconnect device, interconnect areas, stitching of reticles, paragraphs 0025-0026 interconnect areas 2A-2D in FIG. 2, see also FIGS. 3-5 paragraphs 0031-0035 and 0042].
However, Delacruz et al. do not teach a horizontal stitch and a vertical stitch using overlapping exposure areas.
Hou et al. teach forming an interposer with a horizontal stitch and a vertical stitch [0029 may run predominantly horizontally, vertically, or a mix, 0030 stitching process] using overlapping exposure areas [paragraphs 0036-0038 overlapping areas 138o, paragraph 0047].
Thus, considering that Delacruz et al. teach upcoming techniques such as reticle stitching appear promising [0024] and devices can be integrated in a lower cost interposer with much finer pitch [0042], the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains by combining with Hou et al. because the stitching process forms a metallization that has a greater footprint than available for the light mask used to expose the photomask [0030, also in paragraph 0090 any number of pattern regions may be stitched together].
11. The method of claim 10, wherein a total surface area of the interposer is greater than a maximum reticle field used to form the interposer using the overlapping exposure areas [Hou et al. 0030 greater footprint than available].
12. The method of claim 11, wherein the total surface area of the interposer is at least three times a size of the maximum reticle field [Hou et al. paragraphs 0030, 0063, 0067, 0082, 0092 allows for a larger footprint, it is thus interpreted that at least three times a size is an obvious design choice dependent upon the user relative to manufacturing equipment].
13. The method of claim 11, wherein the horizontal stitch and the vertical stitch are formed by slightly overlapping four exposure areas, wherein each of the four exposure areas is at or below the maximum reticle field [Hou et al. 0047 any number of regions may be combined in the stitching process adjacent to each other horizontally and/or vertically, FIG. 46 and paragraph 0085 depict four, 0090, paragraphs 0030 and 0092 greater footprint than available].
14. The method of claim 10, wherein a first pair of the four ICs has a same design, and a second pair of the four ICs has a same design, wherein the design of the first pair is a mirror of the design of the second pair, and wherein a first IC of the first pair has a 180 degree orientation relative to a second IC of the first pair when disposed on the interposer, and a third IC of the second pair has a 180 degree orientation relative to a fourth IC of the second pair when disposed on the interposer [Delacruz et al. 0012 different dies such that the connections may provide high bandwidth signaling, 0031 combined device, 0034-0035 by rotating chips interconnect areas align, Hou et al. 0010 encompass different orientations, rotated, paragraphs 0057, 0090; although the term “pair” is not explicitly recited it is interpreted that such is dependent on the intended configuration for manufacture].
15. The method of claim 10, wherein the four ICs have a same design, wherein a first IC of the four ICs has a 90 degree orientation relative to a second IC of the four ICs, a third IC of the four ICs has a 180 degree orientation relative to the second IC of the four ICs, and a fourth IC of the four ICs has a 270 degree orientation relative to the second IC of the four ICs [Delacruz et al. 0012 different dies such that the connections may provide high bandwidth signaling, 0031 combined device, 0034-0035 by rotating chips interconnect areas align, Hou et al. 0010 encompass different orientations, rotated, paragraphs 0057, 0090].
16. The method of claim 10, wherein the four ICs have a same design, wherein the four ICs have rotational symmetry such they can be arranged in any orientation on the interposer without changing their function or performance [Delacruz et al. 0012 different dies such that the connections may provide high bandwidth signaling, 0031 combined device, 0034-0035 by rotating chips interconnect areas align, Hou et al. 0010 encompass different orientations, rotated, paragraphs 0057, 0090].
Claims 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. [US 10,515,939 B2].
As per claim 17, Chen et al. teach a device [FIG. 7, see also FIG. 9], comprising:
four integrated circuits (ICs) [FIG. 7 elements 702_1-702_4] arranged in a 2x2 configuration [the four dies labelled A3 depicted in FIG. 7], wherein each of the four ICs is connected to neighboring ICs on at least two sides [column 7, lines 14-15 side-by-side fashion], and
wherein the four ICs have a same design [column 6, line 65 homogenous dies], wherein a first IC of the four ICs has a 90 degree orientation relative to a second IC of the four ICs, a third IC of the four ICs has a 180 degree orientation relative to the second IC of the four ICs, and a fourth IC of the four ICs has a 270 degree orientation relative to the second IC of the four ICs [FIG. 7, column 7 lines 23-25 symmetric placement],
wherein the first and second ICs both have defects [column 3, lines 54-55 assuming the distribution of defects is the same], wherein portions of the first and second ICs having the defects are disposed in an unused portion of the device [column 3, lines 54-65 it is interpreted that in order for the device to function, the defects are disposed in unused portions, which reduces yield loss as well as production cost column 1, lines 26-35].
Thus, the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because by selecting and assembling good dies in a side-by-side fashion yield is improved.
20. The device of claim 17, wherein the four ICs have rotational symmetry such they can be arranged in any orientation without changing their function or performance [column 8, lines 10-12, 58-60 rotationally symmetric, column 10, lines 18-23].
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Martorell et al. [US 2021/0111113 A1].
As per claim 17, Martorell et al. teach a device, comprising:
four integrated circuits (ICs) arranged in a 2x2 configuration [120A-D FIGS. 1A-C, 4A, 5A, 7A-C, 0031 two-by-two grid pattern], wherein each of the four ICs is connected to neighboring ICs on at least two sides [170E Fig. 1B, paragraphs 0036, 0045-0053, 0061 row direction and column direction, 0073], and
wherein the four ICs have a same design [0030 implement the same circuit design and layout], wherein a first IC of the four ICs has a 90 degree orientation relative to a second IC of the four ICs, a third IC of the four ICs has a 180 degree orientation relative to the second IC of the four ICs, and a fourth IC of the four ICs has a 270 degree orientation relative to the second IC of the four ICs [0030 mirrored, 0047 rotated, 0059 rotated],
wherein the first and second ICs both have defects, wherein portions of the first and second ICs having the defects are disposed in an unused portion of the device [paragraphs 0046-0048, 0058, 0068 it is interpreted that for a circuit designer to optimize the placement inclusive of defective interposer die working dice are identified to optimize the placement of the logic modules based on design constraints]. Thus, the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because yield may be increased.
20. The device of claim 17, wherein the four ICs have rotational symmetry such they can be arranged in any orientation without changing their function or performance [paragraphs 0047 and 0059 as such, the same circuitry and layout may be used for each].
Response to Arguments
Applicant’s arguments with respect to claims 17 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Regarding Chen et al., the claim does not recite “smaller size dyes can have defects and still be usable” as argued. Regarding Martorell et al., the claim does not recite “interposer chips can be arranged” as argued. Thus, given a broadest reasonable interpretation of the broadly claimed subject matter, the claims are obvious over the applied references. Regarding Delacruz et al. in view of Hou et al., in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The combination of references renders obvious a broadest reasonable interpretation of the broadly claimed subject matter, thus, the claims are obvious over the applied references. Furthermore, in the interest of advancing prosecution, the Examiner respectfully notes (see, also, the Election/Restriction section on the Applicant/Initiated Interview Summary dated 18 February 2026) that the claimed subject matter may be directed toward areas of subject matter that may be independent and distinct.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEIGH M GARBOWSKI whose telephone number is (571)272-1893. The examiner can normally be reached M-F 9-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEIGH M GARBOWSKI/Primary Examiner, Art Unit 2851
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