Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 12/19/2025.
Claims 1-20 are currently pending.
Claims 1, 13, and 19 have been amended.
Claims 1-20 have been examined.
Response to Arguments
In response to amended drawings, the Drawing Objection of the 7/22/2025 non-final is withdrawn.
In response to the amended titled, the Specification Objection to the title of the 7/22/2025 non-final is withdrawn.
In response to the amendment to claim 13, the Claim Objection of the 7/22/2025 non-final is withdrawn.
Applicant’s arguments, see page 12, filed 12/19/2025, with respect to the rejection of claims 13-14 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in further view of Nakamura. See below for more detail.
In regards to claims 15-18, applicant’s arguments, see page 13, filed 12/19/2025, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in further view of Nakamura. See below for more detail.
Applicant’s arguments, see page 13, filed 12/19/2025, with respect to the rejection of claims 1-10 and 19-20 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in further view of Nakamura. See below for more detail.
In regards to claims 11-12, applicant’s arguments, see page 14, filed 12/19/2025, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in further view of Nakamura. See below for more detail.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Evidence that claim 8 fails to correspond in scope with that which the inventor or a joint inventor, or for pre-AIA applications the applicant regards as the invention can be found in the reply filed remarks of 12/19/2025. In that paper, the inventor or a joint inventor, or for pre-AIA applications the applicant has stated that both the first set of micro-bumps and the second set of micro-bumps have the same diameter being the first diameter, and this statement indicates that the invention is different from what is defined in the claims because for the diameter to be the . Therefore this limitation is not physically possible.
Evidence that claim 10 fails to correspond in scope with that which the inventor or a joint inventor, or for pre-AIA applications the applicant regards as the invention can be found in the reply filed remarks of 12/19/2025. In that paper, the inventor or a joint inventor, or for pre-AIA applications the applicant has stated that both the first set of micro-bumps and the second set of micro-bumps have the same diameter being the first diameter, and this statement indicates that the invention is different from what is defined in the claims because for the diameter to be the sum of the first diameter and the first pitch would be necessity be larger than the first diameter as the pitch is a non-zero value. Therefore this limitation is not physically possible.
Claims 8 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 8 and 10 recites the limitation "the second diameter" respectively in the first lines of claims 8 and 10. There is insufficient antecedent basis for this limitation in the claim.
FOR PURPOSES OF EXAMINATION, AT THIS TIME:
Claim 8 will be read as “The package structure of claim 7, whereina second diameter is equal to
Claim 10 will be read as “The package structure of claim 9, whereina second diameter is equal to
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-8, 13, 14, and 19 are rejected under 35 U.S.C. 103 as obvious over Lee et al. US 20210407924 A1 (hereinafter Lee) in view of Nakamura et al. US 20150179551 A1 (hereinafter Nakamura).
The following annotated drawing of Lee Fig. 3 will be used in discussion:
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Regarding claim 1, Lee discloses:
A package structure (Lee, Fig. 3, semiconductor package) comprising:
a first integrated circuit (IC) chip (second semiconductor 800);
a first set of conductors on the first IC chip (annotated Fig. 3, first connection pad 820a);
a second set of conductors on the first IC chip (annotated Fig. 3, second connection pad 820b);
a first redistribution layer (second redistribution structure 700) coupled to the first set of conductors and the second set of conductors (Fig. 3, [0059], second redistribution structure conductive layers 720 couples the second redistribution structure 700 with the connection pads 820a and 820b); and
a chip layer (Fig. 3, [0036], frame structure 100) below the first redistribution layer (Fig. 3), the chip layer comprising:
a second IC chip (first semiconductor chip 200) electrically coupled to the first IC chip; ([0054]the first semiconductor chip 200 and the second semiconductor chip 800 are electrically connected)
a molding material (molding member 300); and
a first through-via positioned (through via 140) in the molding material; (Fig. 3, [0056])
wherein the first set of conductors is a first set of micro-bumps having a diameter, and being in a first region, (annotated Fig. 3, first connection pad 820a. Lee shows that the that the first set of conductors 820a includes solder balls 830 that based on the graphical representation would be around a similar thickness of the bump pad 220 which would be between 5 μm to 20 μm. Therefore may be considered micro-bumps and Lee can be considered to disclose that the first set of conductor is a first set of micro-bumps and the second set of conductor is a second set of micro-bumps. The micro-bumps would inherently have a diameter. )
and the second set of conductors is a second set of micro-bumps having the first diameter the second set of micro-bumps being in a second region, the second region and the first region do not overlap, (annotated Fig. 3, second connection pad 820b the micro-bumps in the first second and the second section are the same therefore would have the same diameter and the regions do not overlap),
Lee shows that the that the first set of conductors 820a includes solder balls 830 that based on the graphical representation would be around a similar thickness of the bump pad 220 which would be between 5 μm to 20 μm. Therefore may be considered micro-bumps and Lee can be considered to disclose that the first set of conductor is a first set of micro-bumps and the second set of conductor is a second set of micro-bumps.
However, Lee does not appear to disclose:
the first region of the first set of micro-bumps has a first area, and a first number of micro- bumps; and
the second region of the second set of micro-bumps has the first area, and a second number of micro-bumps greater than the first number of micro-bumps.
Nakamura, which teaches a semiconductor package including a semiconductor chip joined to an electrode pad (Nakamura, Abstract), discloses:
wherein the first region of the first set of micro-bumps has a first area, and a first number of micro-bumps; and (Nakamura, Fig. 7A, sub-region SA3 is a subregion with an area that is defined by SA3 and has a number of conductive posts 18b (3 conductive posts 18b))
the second region of the second set of micro-bumps has the first area, and a second number of micro-bumps greater than the first number of micro-bumps. (Nakamura, Fig. 7A, sub-region SA2 is a subregion with an area that is defined by SA2 and has 5 conductive posts 18b which is a greater number than the conductive posts in SA3.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee to have wherein the first region of the first set of micro-bumps has a first area, and a first number of micro-bumps; and the second region of the second set of micro-bumps has the first area, and a second number of micro-bumps greater than the first number of micro-bumps as taught by Nakamura for purpose of having more conductive posts in contact will each other in the central portion of the sub-area (Nakamura, [0046]) and improve the mounting quality for the semiconductor chip. (Nakamura, [0011])
Regarding claim 2, Lee as modified by Nakamura disclose all the elements of claim 1.
Lee further discloses:
the first set of conductors is configured to supply a set of signals to the first IC chip (Lee, [0054] the second semiconductor 800 is connected to the first semiconductor package 200. Therefore has to be have conductors that are configured to supply the signal to the first IC chip); and
the second set of conductors is configured to supply a supply voltage or a reference supply voltage to the first IC chip. ([0024], the power pattern or ground pattern are supplied through the conductive wiring. Therefore to power the device of 800, there must be a set of conductors that configured to supply the supply voltage or reference supply voltage.)
Regarding claim 3, Lee as modified by Nakamura, disclose all the elements of claim 1.
Lee further discloses:
a second redistribution layer (redistribution structure 400) below the chip layer (Fig. 3, [0018], the redistribution structure 400 is under the frame structure 100), wherein the chip layer is positioned between the first redistribution layer and the second redistribution layer. (Fig. 3)
Regarding claim 4, Lee as modified by Nakamura, disclose all the elements of claim 3.
Lee further discloses:
a printed circuit board (PCB) below the second redistribution layer. (Lee, [0044], a printed circuit board (PCB) is connected to the semiconductor package by the external connection terminal 500 which under the redistribution structure 400.)
Regarding claim 5, Lee as modified by Nakamura, disclose all the elements of claim 4.
Lee further discloses: a first set of under-bump metallurgies (UBMs) between the PCB and the second redistribution layer. (Fig. 12 which is describes the manufacturing method of the semiconductor package of Fig. 3, [0043], connection cap 433 is a under bump metal (UBM) layer and is between redistribution layer 400 and the PCB.)
Regarding claim 7, Lee as modified by Nakamura disclose all the elements of claim 1.
Lee further discloses:
the first set of conductors (annotated Fig. 3, first connection pad 820a) is the first set of micro-bumps; (the first connection is connected to a lower connection pad by solder balls 830 which can be considered micro-bumps.)
the second set of conductors (annotated Fig. 3, second connection pad 820b) is the second set of micro-bumps; and (the second connection is connected to a lower connection pad by solder balls 830 which can be considered micro-bumps.)
each micro-bump in the first set of micro-bumps is separated from an adjacent micro-bump in the first set of micro-bumps by a first pitch. (Fig. 3 shows that the micro-bumps are separated by a pitch P.)
Regarding claim 8, Lee as modified by Nakamura disclose all the elements of claim 7.
Lee further teaches “wherein a second diameter is equal to (Lee, annotated figure 3, shows that the first area 820a and the second area 820b both have the same bumps 830. Therefor the bumps 830 would have the same diameter.)
Regarding claim 13, Lee discloses:
A package structure comprising: (Lee, Fig. 3, semiconductor package)
a first integrated circuit (IC) chip (second semiconductor 800);
a first set of micro-bumps on the first IC chip, the first set of micro-bumps having a first diameter and a first region; (annotated Fig. 3, first connection pad 820a. Lee shows that the that the first set of conductors 820a includes solder balls 830 that based on the graphical representation would be around a similar thickness of the bump pad 220 which would be between 5 μm to 20 μm. Therefore may be considered micro-bumps and Lee can be considered to disclose that the first set of conductor is a first set of micro-bumps and the second set of conductor is a second set of micro-bumps. The micro-bumps would inherently have a diameter. )
a second set of micro-bumps on the first IC chip, the second set of micro-bumps having the first diameter and a second region (annotated Fig. 3, second connection pad 820b the micro-bumps in the first second and the second section are the same therefore would have the same diameter and the regions do not overlap),
a first redistribution layer (second redistribution structure 700) coupled to the first set of micro-bumps and the second set of micro-bumps (Fig. 3, [0059], second redistribution structure conductive layers 720 couples the second redistribution structure 700 with the connection pads 820a and 820b); and
a chip layer (Fig. 3, [0036], frame structure 100) below the first redistribution layer (Fig. 3), the chip layer comprising:
a second IC chip (first semiconductor chip 200) electrically coupled to the first IC chip; ([0054]the first semiconductor chip 200 and the second semiconductor chip 800 are electrically connected)
a molding material; and (molding member 300)
a first through-via positioned (through via 140) in the molding material; (Fig. 3, [0056])
Lee does not disclose:
“wherein the first region of the first set of micro-bumps has a first area, and a first number of micro-bumps; and
the second region of the second set of micro-bumps has the first area, and a second number of micro-bumps greater than the first number of micro-bumps.”
Nakamura, which teaches a semiconductor package including a semiconductor chip joined to an electrode pad (Nakamura, Abstract), discloses:
wherein the first region of the first set of micro-bumps has a first area, and a first number of micro-bumps; and (Nakamura, Fig. 7A, sub-region SA3 is a subregion with an area that is defined by SA3 and has a number of conductive posts 18b (3 conductive posts 18b))
the second region of the second set of micro-bumps has the first area, and a second number of micro-bumps greater than the first number of micro-bumps. (Nakamura, Fig. 7A, sub-region SA2 is a subregion with an area that is defined by SA2 and has 5 conductive posts 18b which is a greater number than the conductive posts in SA3.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee to have wherein the first region of the first set of micro-bumps has a first area, and a first number of micro-bumps; and the second region of the second set of micro-bumps has the first area, and a second number of micro-bumps greater than the first number of micro-bumps as taught by Nakamura for purpose of having more conductive posts in contact will each other in the central portion of the sub-area (Nakamura, [0046]) and improve the mounting quality for the semiconductor chip. (Nakamura, [0011])
Regarding claim 14, Lee as modified by Nakamura disclose all the elements of claim 13.
Lee further discloses:
the first set of conductors is configured to supply a set of signals to the first IC chip (Lee, [0054] the second semiconductor 800 is connected to the first semiconductor package 200. Therefore has to be have conductors that are configured to supply the signal to the first IC chip); and
the second set of conductors is configured to supply a supply voltage or a reference supply voltage to the first IC chip. ([0024], the power pattern or ground pattern are supplied through the conductive wiring. Therefore to power the device of 800, there must be a set of conductors that configured to supply the supply voltage or reference supply voltage.)
Regarding claim 19, Lee discloses:
A method of manufacturing a package structure comprising: (Lee, Fig. 3, semiconductor package)
forming a first set of conductors (annotated Fig. 3, first connection pad 820a) and a second set of conductors (annotated Fig. 3, second connection pad 820b) on a first surface of a first integrated circuit (IC) chip, (second semiconductor 800)
forming a first redistribution layer (RDL) (second redistribution structure 700) on a first surface of the first set of conductors (annotated Fig. 3, first connection pad 820a) and the second set of conductors(annotated Fig. 3, second connection pad 820b), the first RDL being coupled to the first set of conductors and the second set of conductors; and (Fig. 3)
forming a chip layer on a first surface of the first RDL, the forming the chip layer comprises: (Fig. 3, [0036], frame structure 100)
coupling a second IC chip (first semiconductor chip 200) to the first surface of the RDL, the second IC chip being electrically coupled to the first IC chip; (Fig. 3)
forming a molding material (molding member 300) around the second IC chip; and (Fig. 3)
forming a first through-via (through via 140) in the molding material(molding member 300); (Fig. 3)
wherein the first set of conductors is a first set of micro-bumps having a diameter, and being in a first region, (annotated Fig. 3, first connection pad 820a. Lee shows that the that the first set of conductors 820a includes solder balls 830 that based on the graphical representation would be around a similar thickness of the bump pad 220 which would be between 5 μm to 20 μm. Therefore may be considered micro-bumps and Lee can be considered to disclose that the first set of conductor is a first set of micro-bumps and the second set of conductor is a second set of micro-bumps. The micro-bumps would inherently have a diameter. )
and the second set of conductors is a second set of micro-bumps having the first diameter the second set of micro-bumps being in a second region, the second region and the first region do not overlap, (annotated Fig. 3, second connection pad 820b the micro-bumps in the first second and the second section are the same therefore would have the same diameter and the regions do not overlap),
Lee shows that the that the first set of conductors 820a includes solder balls 830 that based on the graphical representation would be around a similar thickness of the bump pad 220 which would be between 5 μm to 20 μm. Therefore may be considered micro-bumps and Lee can be considered to disclose that the first set of conductor is a first set of micro-bumps and the second set of conductor is a second set of micro-bumps.
However, Lee does not appear to disclose:
the first region of the first set of micro-bumps has a first area, and a first number of micro- bumps; and
the second region of the second set of micro-bumps has the first area, and a second number of micro-bumps greater than the first number of micro-bumps.
Nakamura, which teaches a semiconductor package including a semiconductor chip joined to an electrode pad (Nakamura, Abstract), discloses:
wherein the first region of the first set of micro-bumps has a first area, and a first number of micro-bumps; and (Nakamura, Fig. 7A, sub-region SA3 is a subregion with an area that is defined by SA3 and has a number of conductive posts 18b (3 conductive posts 18b))
the second region of the second set of micro-bumps has the first area, and a second number of micro-bumps greater than the first number of micro-bumps. (Nakamura, Fig. 7A, sub-region SA2 is a subregion with an area that is defined by SA2 and has 5 conductive posts 18b which is a greater number than the conductive posts in SA3.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee to have wherein the first region of the first set of micro-bumps has a first area, and a first number of micro-bumps; and the second region of the second set of micro-bumps has the first area, and a second number of micro-bumps greater than the first number of micro-bumps as taught by Nakamura for purpose of having more conductive posts in contact will each other in the central portion of the sub-area (Nakamura, [0046]) and improve the mounting quality for the semiconductor chip. (Nakamura, [0011])
Claims 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee as modified by Nakamura as applied to claim 1 and 19 above, and further in view of Jeng et al. US 20200091029 A1 (hereinafter Jeng).
Regarding claim 6, Lee as modified by Nakamura, disclose all the elements of claim 5.
Neither Lee or Nakamura appear to disclose:
forming a second set of UBMs on a first surface of the PCB.
However, Jeng, which teaches a package structure including stacked dies (Jeng, Abstract), discloses:
forming a second set of UBMs (Jeng, Fig. 1L, conductive connectors 164) on a first surface of the PCB. (interconnect structure 164)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee as modified by Nakamura to have a second set of UBMs on a first surface of the PCB as taught by Jeng for purposes of enabling fan-out connections. (Jeng, [0042].)
Regarding claim 20, Lee as modified by Nakamura disclose all the elements of claim 19.
Lee further discloses:
forming a second RDL (redistribution structure 400) on a first surface of the chip layer (Fig. 3, [0018], the redistribution structure 400 is under the frame structure 100), wherein the chip layer is positioned between the first redistribution layer and the second RDL; (Fig. 3)
forming a first set of under-bump metallurgies (UBMs) on a first surface of the second RDL; (Fig. 12 which is describes the manufacturing method of the semiconductor package of Fig. 3, [0043], connection cap 433 is a under bump metal (UBM) layer and is between redistribution layer 400 and the PCB.)
coupling a printed circuit board (PCB) to the second RDL by the first set of UBMs; (Lee, [0044], a printed circuit board (PCB) is connected to the semiconductor package by the external connection terminal 500 which under the redistribution structure 400.)
Neither Lee or Nakamura appear to disclose:
forming a second set of UBMs on a first surface of the PCB.
However, Jeng, which teaches a package structure including stacked dies (Jeng, Abstract), discloses:
forming a second set of UBMs (Jeng, Fig. 1L, conductive connectors 164) on a first surface of the PCB. (interconnect structure 164)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee as modified by Nakamura to have a second set of UBMs on a first surface of the PCB as taught by Jeng for purposes of enabling fan-out connections. (Jeng, [0042].)
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee as modified by Nakamura as applied to claim 1 above, and further in view of Li US 20220367400 A1 (hereinafter Li).
Regarding claim 9, Lee as modified by Nakamura disclose all the elements of claim 1.
Neither Lee as modified by Nakamura disclose:
the first set of conductors is a first set of pillars; and the second set of conductors is a second set of pillars … .
Li, which teaches forming electrical connectors in a package component (Li, Abstract), discloses that the first set of conductors (Fig. 1, electrical connectors 36_1) and second set of conductors (Fig. 1, electrical connectors 36_2) can be metal bumps or metal pillars.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee as modified by Nakamura to have the first set of conductors is a first set of pillars ..., and the second set of conductors is a second set of pillars ... as taught by Li for purposes of physically joining the corresponding electrical connectors. (Li, [0023].)
Since Li teaches that bumps and pillars are interchangeable method of electrically connecting the semiconductor package device. Lee would also disclose;
the first set of conductors (annotated Fig. 3, first connection pad 820a) is the first set of pillars; (where the set of conductors are pillars as taught by Li for electric connection instead of bumps.)
the second set of conductors (annotated Fig. 3, second connection pad 820b) is the second set of pillars; and (where the set of conductors are pillars as taught by Li for electric connection instead of bumps.)
each pillar in the first set of pillars is separated from an adjacent pillar in the first set of pillars by a first pitch. (Fig. 3 shows that the electric connection is are separated by a pitch P.)
Regarding claim 10, Lee as modified by Nakamura disclose all the elements of claim 9.
Lee further teaches “wherein a second diameter is equal to (Lee, annotated figure 3, shows that the first area 820a and the second area 820b both have the same bumps 830. Therefor the bumps 830 would have the same diameter.)
Claims 11, 12, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee as modified by Nakamura as applied to claim 1 and 13 above, and further in view of Lai et al US 20220406730 A1 (hereinafter Lai).
For claims 11, 15 and 16 the following annotated Figure will be used:
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Regarding claim 11, Lee as modified by Nakamura disclose all the elements of claim 1.
Lee as modified by Nakamura do not appear to explicitly disclose:
wherein the first set of conductors and the second set of conductors are arranged in an array including a set of rows and a set of columns, each row of the set of rows being arranged in a first direction, and each column of the set of columns being arranged in a second direction different from the first direction;
the second set of conductors is located at an intersection of a first row of the set of rows and a first column of the set of columns; and
the first set of conductors is located in a second row of the set of rows different from the first row of the set of rows, and is further located in a second column of the set of columns different from the first column of the set of columns.
Lai, which teaches a package structure which includes a bonding elements in an array (Lai, [0069]), discloses:
wherein the first set of conductors (annotated Fig. 1G-2A including boding elements 148 in area_1) and the second set of conductors (annotated Fig. 1G-2A including boding elements 148 in area_2) are arranged in an array including a set of rows and a set of columns (the bonding element in both areas are arranged on an grid shown), each row of the set of rows being arranged in a first direction (the A row is in one direction), and each column of the set of columns being arranged in a second direction different from the first direction; (the B column is in the orthogonal direction from the A row)
the second set of conductors is located at an intersection of a first row of the set of rows and a first column of the set of columns; and (See Fig. 1G-2)
the first set of conductors is located in a second row of the set of rows different from the first row of the set of rows, and is further located in a second column of the set of columns different from the first column of the set of columns. (See Fig. 1G-2)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee as modified by Nakamura to have “the first set of conductors and the second set of conductors are arranged in an array including a set of rows and a set of columns, each row of the set of rows being arranged in a first direction, and each column of the set of columns being arranged in a second direction different from the first direction, the second set of conductors is located at an intersection of a first row of the set of rows and a first column of the set of columns, and the first set of conductors is located in a second row of the set of rows different from the first row of the set of rows, and is further located in a second column of the set of columns different from the first column of the set of columns” as taught by Lai for purposes of The bonding elements having a resulting package structure having reduced or mitigated tensile stress which improved reliability of the package structure. (Lai, [0090].)
Regarding claim 15, Lee as modified by Nakamura disclose all the elements of claim 13.
Lee as modified by Nakamura do not appear to explicitly disclose:
wherein the first set of conductors and the second set of conductors are arranged in an array including a set of rows and a set of columns, each row of the set of rows being arranged in a first direction, and each column of the set of columns being arranged in a second direction different from the first direction;
the second set of conductors is located at an intersection of a first row of the set of rows and a first column of the set of columns; and
the first set of conductors is located in a second row of the set of rows different from the first row of the set of rows, and is further located in a second column of the set of columns different from the first column of the set of columns.
Lai, which teaches a package structure which includes a bonding elements in an array (Lai, [0069]), discloses:
wherein the first set of conductors (annotated Fig. 1G-2A including boding elements 148 in area_1) and the second set of conductors (annotated Fig. 1G-2A including boding elements 148 in area_2) are arranged in an array including a set of rows and a set of columns (the bonding element in both areas are arranged on an grid shown), each row of the set of rows being arranged in a first direction (the B row is in one direction), and each column of the set of columns being arranged in a second direction different from the first direction; (the A column is in the orthogonal direction from the B row)
the second set of conductors is located at an intersection of a first row of the set of rows and a first column of the set of columns; and (See Fig. 1G-2A)
the first set of conductors is located in a second row of the set of rows different from the first row of the set of rows, and is further located in a second column of the set of columns different from the first column of the set of columns. (See Fig. 1G-2A)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee as modified by Nakamura to have “the first set of conductors and the second set of conductors are arranged in an array including a set of rows and a set of columns, each row of the set of rows being arranged in a first direction, and each column of the set of columns being arranged in a second direction different from the first direction, the second set of conductors is located at an intersection of a first row of the set of rows and a first column of the set of columns, and the first set of conductors is located in a second row of the set of rows different from the first row of the set of rows, and is further located in a second column of the set of columns different from the first column of the set of columns” as taught by Lai for purposes of The bonding elements having a resulting package structure having reduced or mitigated tensile stress which improved reliability of the package structure. (Lai, [0090].)
Regarding claim 16, Lee, Nakamura, and Lai disclose all the elements of claim 15.
Lai further discloses:
wherein the first region includes a first micro-bump, a second micro-bump, a third micro-bump and a fourth micro-bump; (annotated Fig. 1G-2A, including bumps labeled 1, 2, 3, 4)
the second region includes a fifth micro-bump, a sixth micro-bump, a seventh micro-bump, an eighth micro-bump and a ninth micro-bump; (annotated Fig. 1G-2A including bumps labeled 5, 6, 7, 8, 9)
the first micro-bump, the second micro-bump, the fifth micro-bump, and the sixth micro- bump are aligned with each other in the first direction; (See annotated Fig. 1G-2A)
the third micro-bump, the fourth micro-bump, the seventh micro-bump, and the eighth micro-bump are aligned with each other in the first direction; and (See annotated Fig. 1G-2A)
the ninth micro-bump is located between the fifth micro-bump, the sixth micro-bump, the seventh micro-bump, and the eighth micro-bump. (See annotated Fig. 1G-2A)
For discussion of claims 12, 17, and 18 the following annotated figure will be used:
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Regarding claim 12, Lee as modified by Nakamura disclose all the elements of claim 1.
Lee as modified by Nakamura do not appear to explicitly disclose:
wherein the first set of conductors and the second set of conductors are arranged in an array including a set of rows and a set of columns, each row of the set of rows being arranged in a first direction, and each column of the set of columns being arranged in a second direction different from the first direction;
the second set of conductors is located in a first column of the set of columns; and
the first set of conductors is located in a sub-set of columns of the set of columns different from the first column of the set of columns.
Lai, which teaches a package structure which includes a bonding elements in an array (Lai, [0069]), discloses:
the first set of conductors (annotated Fig. 1G-2B including boding elements 148 in area_1) and the second set of conductors (annotated Fig. 1G-2B including boding elements 148 in area_2) are arranged in an array including a set of rows and a set of columns(the bonding element in both areas are arranged on an grid shown with the rows B and the columns A),, each row of the set of rows being arranged in a first direction (the rows B are arranged in a first direction), and each column of the set of columns being arranged in a second direction different from the first direction;(the columns A are arranged in an orthogonal direction to the rows B)
the second set of conductors is located in a first column of the set of columns; and
the first set of conductors is located in a sub-set of columns of the set of columns different from the first column of the set of columns.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee as modified by Nakamura and Li to have “the first set of conductors and the second set of conductors are arranged in an array including a set of rows and a set of columns, each row of the set of rows being arranged in a first direction, and each column of the set of columns being arranged in a second direction different from the first direction, the second set of conductors is located in a first column of the set of columns, and the first set of conductors is located in a sub-set of columns of the set of columns different from the first column of the set of columns” as taught by Lai for purposes of The bonding elements having a resulting package structure having reduced or mitigated tensile stress which improved reliability of the package structure. (Lai, [0090].)
Regarding claim 17, Lee as modified by Nakamura disclose all the elements of claim 13.
Lee as modified by Nakamura do not appear to explicitly disclose:
wherein the first set of micro-bumps and the second set of micro-bumps are arranged in an array including a set of rows and a set of columns, each row of the set of rows being arranged in a first direction, and each column of the set of columns being arranged in a second direction different from the first direction;
the second set of micro-bumps is located in a first column of the set of columns; and
the first set of micro-bumps is located in a sub-set of columns of the set of columns different from the first column of the set of columns.
Lai, which teaches a package structure which includes a bonding elements in an array (Lai, [0069]), discloses:
the first set of conductors (annotated Fig. 1G-2B including boding elements 148 in area_1) and the second set of conductors (annotated Fig. 1G-2B including boding elements 148 in area_2) are arranged in an array including a set of rows and a set of columns(the bonding element in both areas are arranged on an grid shown with the rows B and the columns A),, each row of the set of rows being arranged in a first direction (the rows B are arranged in a first direction), and each column of the set of columns being arranged in a second direction different from the first direction;(the columns A are arranged in an orthogonal direction to the rows B)
the second set of conductors is located in a first column of the set of columns; and
the first set of conductors is located in a sub-set of columns of the set of columns different from the first column of the set of columns.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee as modified by Nakamura and Li to have “the first set of conductors and the second set of conductors are arranged in an array including a set of rows and a set of columns, each row of the set of rows being arranged in a first direction, and each column of the set of columns being arranged in a second direction different from the first direction, the second set of conductors is located in a first column of the set of columns, and the first set of conductors is located in a sub-set of columns of the set of columns different from the first column of the set of columns” as taught by Lai for purposes of The bonding elements having a resulting package structure having reduced or mitigated tensile stress which improved reliability of the package structure. (Lai, [0090].)
Regarding claim 18, Lee, Nakamura, and Lai disclose all the elements of claim 13.
Lai further discloses:
wherein the first region includes a first micro-bump, a second micro-bump, a third micro-bump and a fourth micro-bump; (annotated Fig. 1G-2B, including bumps labeled 1, 2, 3, 4)
the second region includes a fifth micro-bump, a sixth micro-bump, a seventh micro-bump, an eighth micro-bump, a ninth micro-bump and at least a portion of a tenth micro-bump; (annotated Fig. 1G-2D including bumps labeled 5, 6, 7, 8, 9)
the first micro-bump, the second micro-bump, the fifth micro-bump, and the sixth micro- bump are aligned with each other in the first direction; (See annotated Fig. 1G-2B)
the third micro-bump, the fourth micro-bump, the seventh micro-bump, and the eighth micro-bump are aligned with each other in the first direction; (See annotated Fig. 1G-2B)
the ninth micro-bump is located between the fifth micro-bump, the sixth micro-bump, the seventh micro-bump, and the eighth micro-bump; and (See annotated Fig. 1G-2B)
at least a portion of the tenth micro-bump is located along a boundary between adjacent rows of the set of rows within the first column of the set of columns. (See annotated Fig. 1G-2B)
Conclusion
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/HEIM KIRIN GREWAL/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812