DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/04/2025 have been fully considered but they are moot in view of the new grounds of rejection as necessitated by Applicant’s claim amendments or indication of allowable subject matter as detailed below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1,4-13 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Number 7,985,986 B2 to Heikman et al., “Heikman”, in view of U.S. Patent Application Publication Number 2016/0196971 A1 to Hsu et al., “Hsu”, and U.S. Patent Application Publication Number 2020/0044067 A1 to Banerjee et al., “Banerjee”.
Regarding claim 1, Heikman discloses a method for forming a high electron mobility transistor (e.g. Figure 5A), comprising:
providing (Figure 1A) a substrate (10, column 7 lines 10-46);
forming (Figure 1A) a channel layer (20, includes 2DEG 33, column 7 line 47 to column 8 line 4) on the substrate;
forming (Figure 1A) an electron supply layer (22, column 8 lines 5-67) on the channel layer;
forming (Figure 1A) a dielectric passivation layer (23, column 9 lines 1-5) on the electron supply layer;
forming (Figure 1B, alternately Figure 7B) a gate recess (75, column 9 lines 6-20, alternately 76) into the dielectric passivation layer (23) and the electron supply layer (22);
conformally depositing (Figure 1C) a single-layered surface modification layer (35, column 9 line 59 to column 10 line 17) on an interior surface of the gate recess, wherein the single-layered surface modification layer (35) is in direct contact (as pictured) with a top surface of the dielectric passivation layer (23);
forming (Figure 1D) a gate layer (32, column 11 line 55 to column 12 line 2) in the gate recess and on the single-layered surface modification layer (35), wherein the single-layered surface modification layer (35) is in direct contact with a bottom surface of the gate layer (32).
Heikman fails to clearly teach subjecting the single-layered surface modification layer (35) to an oxidation treatment or a nitridation treatment, wherein the single-layered surface modification layer is first subjected to the nitride treatment and is then subjected to the oxidation treatment. Heikman teaches wherein the single-layered surface modification layer (35) may be formed of silicon oxynitride (column 9 line 61).
Hsu teaches forming a silicon oxynitride gate oxide by forming (FIG. 1) a single-layered surface modification layer (120, ¶ [0012]) which is first subjected to a nitride treatment (FIG. 2 nitridation process P1, ¶ [0013]) and then subjected to (FIG. 3) an oxidation treatment (multi-step post nitridation annealing P2, “oxygen-containing” ¶ [0014]). Additionally, Hsu teaches wherein the method may be applied to a III-V substrate (¶ [0012]) and Heikman teaches a III-V device (Abstract).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Heikman using the nitridation and oxygen-containing post-anneal process of Hsu in order to tune the properties of the gate oxide to improve reliability, yields, circuit leakage and negative bias temperature instability (NBTI) (Hsu ¶ [0006],[0008],[0023]).
Heikman fails to clearly teach wherein the gate layer includes P-type GaN.
Banerjee teaches (FIG. 5) wherein a gate layer includes P-type GaN (lower gate electrode film 344, ¶ [0040]-[0042]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Heikman in view of Hsu with the gate including P-type GaN as a lower gate electrode film as taught by Banerjee in order to tune the work function of the gate since when the lower gate electrode film includes P-type GaN the work function is approximately 6 eV to 7 eV and can increase the threshold voltage by more than 2V as compared to TiN (Banerjee ¶ [0041]) which can improve carrier mobility and reduce on resistance (Banerjee Abstract, ¶ [0021],[0022]).
Regarding claim 4, Heikman in view of Hsu and Banerjee yields the method according to claim 1, and Heikman further teaches (Figure 7B) wherein the gate recess (76) does not penetrate through the electron supply layer (“the barrier layer 22 may be etched during formation of the trench 76” column 14 lines 34-45).
Regarding claim 5, although Heikman in view of Hsu and Banerjee yields the method according to claim 1, Heikman fails to clearly teach wherein the dielectric passivation layer (23) comprises oxide or aluminum nitride. Rather, Heikman teaches wherein the dielectric passivation layer (23) comprises silicon nitride (column 9 lines 1-4).
Banerjee teaches wherein a dielectric passivation layer (110) comprises a single silicon nitride film, or a layer of aluminum nitride sandwiched between two silicon nitride films (¶ [0030]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Heikman in view of Hsu and Banerjee with aluminum nitride sandwiched between silicon nitride films as the dielectric passivation layer as taught by Banerjee since it has been held in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) that exemplary rationales that may support a conclusion of obviousness include:
(A) Combining prior art elements according to known methods to yield predictable results;
(B) Simple substitution of one known element for another to obtain predictable results;
(C) Use of known technique to improve similar devices (methods, or products) in the same way;
(D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results;
(E) “Obvious to try” – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success;
(F) Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art;
(G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention,
wherein in the instant case one having ordinary skill in the art could have and would have been able to apply (B) Simple substitution of the single silicon nitride film of Heikman with the layer of aluminum nitride sandwiched between silicon oxide films as taught by Banerjee with the predictable and desirable result of forming a suitable dielectric passivation layer.
Regarding claim 6, although Heikman in view of Hsu and Banerjee yields the method according to claim 1, Heikman fails to clearly teach in sufficient specificity for anticipation (MPEP 2131.03) wherein the dielectric passivation layer (23) is thicker than the single-layered surface modification layer (35).
Heikman teaches wherein the dielectric passivation layer (23) has a thickness of from about 30 nm to 30 nm to about 300 nm (300 Å to about 3000 Å column 9 line 5) and wherein the single-layered surface modification layer (35) has a thickness of 6 nm to about 60 nm (60 Å to about 600 Å column 9 line 58) which includes ranges wherein the dielectric passivation layer (23) is thicker than the single-layered surface modification layer (35).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Heikman in view of Hsu and Banerjee with the dielectric passivation layer (23) thicker than the single-layered surface modification layer (35) as suggested by the overlapping ranges of Heikman since it has been held that in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), and/or since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the single-layered surface modification layer is the gate oxide and the thickness determines the operating characteristics of the transistor such as the threshold voltage making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Regarding claim 7, although Heikman in view of Hsu and Banerjee yields the method according to claim 1, Heikman fails to clearly teach in sufficient specificity for anticipation (MPEP 2131.03) wherein the dielectric passivation layer (23) has a thickness of about 20 nanometers.
Banerjee teaches wherein the thickness of the passivation layer (108) ranges from 2 nm to 150 nm (¶ [0030]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the passivation layer of Heikman with the thickness as claimed as taught by Banerjee since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the thickness of the passivation layer determines the overall dimensions and electrical characteristics of the transistor making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Regarding claim 8, Heikman in view of Hsu and Banerjee yields the method according to claim 1, and Heikman further teaches wherein before forming the channel layer (20) on the substrate, the method further comprises: forming a buffer layer on the substrate (column 7 lines 21-25).
Regarding claim 9, Heikman in view of Hsu and Banerjee yields the method according to claim 8, and Heikman further teaches wherein the buffer layer comprises AIN (column 7 line 23).
Regarding claim 10, Heikman in view of Hsu and Banerjee yields the method according to claim 1, and Heikman further teaches wherein the substrate is a silicon substrate (column 7 line 43).
Regarding claim 11, Heikman in view of Hsu and Banerjee yields the method according to claim 1, and Heikman further teaches wherein the channel layer (20) comprises intrinsic GaN (column 7 lines 64,67).
Regarding claim 12, Heikman in view of Hsu and Banerjee yields the method according to claim 11, and Heikman further teaches wherein the electron supply layer (22) comprises AlGaN (column 8 lines 25-26).
Regarding claim 13, Heikman in view of Hsu and Banerjee yields the method according to claim 1, and Banerjee further teaches wherein after forming the P-type GaN gate layer in the gate recess (FIG. 3 forming 344 in recess), the method further comprises: forming (FIG. 4) a gate electrode (444, ¶ [0043]) on the P-type GaN layer (344); and Heikman further teaches a source electrode (30) in a source region and a drain electrode (31) in a drain region.
Heikman fails to clearly teach forming the source (30) and drain (31) electrodes after the gate.
Banerjee teaches (FIG. 5) forming a source electrode (522, ¶ [0046]) in a source region and a drain electrode (526, ¶ [0046]) in a drain region after forming the P-type GaN (344).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Heikman in view of Hsu and Banerjee with the source and drain electrodes formed after the p-type GaN gate layer as taught by Banerjee since it has been held in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) that exemplary rationales that may support a conclusion of obviousness include:
(A) Combining prior art elements according to known methods to yield predictable results;
(B) Simple substitution of one known element for another to obtain predictable results;
(C) Use of known technique to improve similar devices (methods, or products) in the same way;
(D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results;
(E) “Obvious to try” – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success;
(F) Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art;
(G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention,
wherein in the instant case one having ordinary skill in the art could have and would have found it obvious to form the source and drain electrodes after the P-type GaN gate layer in applying (B) Simple substitution with the predictable and desired result of forming suitable source and drain electrodes.
Allowable Subject Matter
Claims 2 and 3 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Although prior art e.g. U.S. Patent Application Publication Number 2006/0172473 A1 to Cheng et al. teaches wherein a surface modification layer (54) is an amorphous silicon layer (¶ [0014]) as discussed previously, Cheng fails to clearly teach wherein the surface modification layer is a single-layered and therefore prior art fails to reasonably teach or suggest wherein the single-layered surface modification layer is an amorphous silicon layer together as claimed in claim 2 together with all of the limitations of claim 1 as claimed. Claim 3 is objected to as allowable insofar as it depends upon and includes all of the limitations of claims 2 and 1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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/Eric A. Ward/ Primary Examiner, Art Unit 2891