Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments filed 1/14/2026 have been entered and considered. The amendments to claims 1, 8, 10, 12, 14, 17, and 18 are acknowledged.
Response to Arguments
Applicant’s arguments, filed 1/14/2026, with respect to the rejection(s) of claim 1 under 35 U.S.C. 112 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the limitation “embodied as an alignment mark” which is not supported in the specification.
Applicant’s arguments with respect to claim 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claim recites that the dicing path is embodied as an alignment mark but there is not passage in the specification that teaches such a dicing path. There is no indication that the dicing path is a structural feature of the scribe line.
Claims 2-11 are rejected based on the dependency on claim 1.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 includes language at a different stage of manufacturing from the claims it depends on, rendering the claim indefinite. The claim recites “wherein the scribe line region has a kerf portion and a remaining scribe-line structure and wherein each of the one or more icruit probing pads has a kerf portion and a remaining circuit probing pad”. Kerf portions are portions left over after being cut, such that the claim language is directed to a stage of manufacturing after a dicing process is taken. Meanwhile, claims 1, 8 and 9 contain limitations directed to an intermediate product.
Claim 18 includes language at a different stage of manufacturing from the claims it depends on, rendering the claim indefinite. The claim recites “wherein a dicing process is performed on the semiconductor wafer along dicing path; wherein the semiconductor wafer is diced along the dicing path to separate the die regions; wherein a portion of each of the probing pads is diced out from the semiconductor wafer to form a remaining circuit probing pad on the scribe line region, wherein the remaining circuit probing pad is disabled for testing.” The semiconductor device of claim 12 pertains to a wafer before being diced while claim 18 teaches the dicing of the wafer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 unpatentable over Chen et al. US 20230120504 A1 (hereinafter referred to as Chen), in view of Takahashi US 20230064636 A1 (hereinafter referred to as Takahashi), in view of Katkar et al. US 20150262972 A1 (hereinafter referred to as Katkar).
A scribe line structure, comprising:
a die region (region with “die 110aa” within, para. 0049 FIG. 1C), disposed on a semiconductor wafer (“semiconductor substrate 102” para. 0049);
a scribe line region (“dicing region 120” para. 0049), extended from the die region (“dicing region 120” extends from the region where “die 110aa” is), wherein a dicing path, which is embodied as an alignment mark, is formed on the scribe line region and is arranged for the semiconductor wafer being diced along the dicing path to dice the scribe line region from the die region (“a dicing region may include markers (e.g., dicing lines, optical alignment structures, etc.) arranged for separating the dies during a wafer dicing process”, para. 0049);
one or more bump pads (“device pads 160” para. 0050), disposed on a first top surface of an edge region of the die region (“device pads 160” are disposed on an edge portion of the surface of “die 110aa”);
one or more circuit probing pads (“test pads 170”), disposed on a second top surface of the scribe line region (“testing pads 170” are in the “dicing region 120” on “example wafer 100”),
one or more metal wires (“wiring structures 180” para. 0054), disposed on the first top surface of the die region and the second top surface of the scribe line region, and configured to electrically connect the one or more bump pads to the one or more circuit probing pads (“wiring structures 180” extend along the top surface of “example wafer 110” to connect “device pads 160” in the “die 110aa” to the “testing pads 170” in the “dicing region 120”, para. 0054);
wherein the one or more metal wires are formed on and in contact with the first top surface of the die region and the second top surface of the scribe line (since “wiring structures 180" are formed on “substrate portion 106” of an “exposed area 106” of the wafer, the examiner understands that the conductive structures including “wiring structures180” are formed directly on “example wafer 110”, para. 0049), such that the one or more metal wires are extended across the first top surface of the die region and the second top surface of the scribe line region (“wiring structures 180” extend from “dicing region 120” to “die 110aa”).
However, Chen fails to expressly teach wherein the dicing path is extended across the one or more circuit probing pads, such that when the semiconductor wafer is diced along the dicing path to separate the scribe line region from the die region, a portion of each of the one or more circuit probing pads is diced along the dicing path.
Nevertheless, Chen teaches that a marker for dicing is formed in the “dicing region 120”. The examiner understands that the amount of portions of “test pads 170” that are diced depends on the dicing path, the area of the “testing pads 170”, and the dimensions of the saw blade or laser beam used for dicing in Chen. For example, Takahashi discusses in para. 0010 how smaller conductive patterns in a dicing region can be easier to remove completely, though contact with the pad for testing may be more difficult. Furthermore, Katkar teaches “test pads 1610” in a dicing lane (para. 0082 FIG. 16). After dicing, portions of the “test pads 1610” may remain so that testing can still be done. As indicated in Takahashi, the possibility of testing with the conductive pattern depends on its size (para. 0010), and the examiner understands that this extends to a remaining portion of the conductive pattern: if the remaining portion of “conductive pattern CP3” after dicing is too small, testing may be difficult or not possible. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the amount of remaining “test pads 170” depends on the dicing path and the relative sizes of the “test pads 170” and the dicing apparatus and portions of “test pads 170” may remain after dicing if testing is desired the dicing process.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjusting the dicing path in Chen with the teachings of Takahashi and Katkar. The dicing path may be formed across the probing pads so that at least portions of the probing pads are removed and the amount of remaining probing pads is determined by the dicing path, the dicing instrument width, and the size of the probing pads.
Regarding claim 2, Chen, modified by Takahashi and Katkar, teaches the scribe line structure of Claim 1, Chen teaches the semiconductor device of Claim 12, wherein each die region comprises functional circuitry (“die 110aa” includes “active area 140” which contains active devices, para. 0050), and the scribe line region is a non-functional region (since the “dicing regions 120 and 122” are to be diced away for the formation of other devices, the examiner understands the region has no functional circuitry beyond testing means, para. 0054).
However, Chen, modified by Takahashi and Katkar, fails to expressly teach wherein the one or more bump pads and the one or more metal wires are formed concurrently before the one or more circuit probing pads are formed.
Claim 2 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed “wherein the die region comprises functional circuitry, and the scribe line region is a non-functional region” need not be formed by the process of wherein “the one or more bump pads and the one or more metal wires are formed concurrently before the one or more circuit probing pads are formed”. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
Regarding claim 3, Chen, modified by Takahashi and Katkar, teaches the scribe line structure of Claim 2, wherein the one or more bump pads are electrically connected to the functional circuitry of the die region (“device pads 160” are electrically coupled to the circuitry in “active area 140”, para. 0050).
Regarding claim 4, Chen, modified by Takahashi and Katkar, teaches the scribe line structure of Claim 3, wherein the functional circuitry of the die region is tested via one or more circuit probing needles electrically connected to external test equipment and placed on the one or more circuit probing pads (“device pads 160” are coupled to the “active area 140” and “testing pads 170” are connected to “device pads 160” and are “arranged to receive one or more external probes for determining one or more characteristics of the one or more first active devices of the plurality of testing dies 110aa, 110ab”, para. 0054).
Regarding claim 6, Chen, modified by Takahashi and Katkar, teaches the scribe line structure of Claim 1, wherein a center of each circuit probing pad is disposed on a center line of the scribe line region (FIG. 1C suggests that “testing pads 170” are aligned in a substantially central area of “dicing region 120”), such that the center line of the scribe line region is positioned between two side edges of each circuit probing pad (since the “testing pads 170” appear to be aligned along the center of “dicing region 120”, a line drawn through the center is within the area of each “testing pads 170” as shown in annotated FIG. 1C).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, modified by Takahashi and Katkar, as applied to claim 1 above, in view of Sakumoto et al US 5239191 A (hereinafter referred to as Sakumoto).
Chen, modified by Takahashi and Katkar, teaches the scribe line structure of Claim 12 but fails to teach wherein each circuit probing pad is larger than each bump pad.
Nevertheless, Sakumoto teaches wherein each circuit probing pad (“testing pad 15” col 3 lines 6-7 FIG. 2) is larger than each bump pad (“pad 13” col 3 line 13).
Chen, modified by Takahashi and Katkar, and Sakumoto teach the use of circuit probing pads in scribe line regions. Each “testing pad 15” is connected to a plurality of “pads 13” of each “chip area 12” (col 3 lines 12- 13). Because of this, “testing pad 15” acts as a common testing pad and its size can be made larger as long as it can fit in the “dicing line area 11” (col 3 lines 13-20). Furthermore, the examiner understands that a larger “testing pad 15” is easier to contact with a probe needle than a smaller testing pad since there is more area to make contact with. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that large “testing pads 15” can be used as common test pad for a plurality of the “pads 13” that is easier to contact with probing equipment.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the scribe line structure taught between Chen Takahashi and Katkar, with the circuit probing pads taught in Sakumoto. A circuit probing pad can contact multiple bump pads and be made larger so that the bump pads can be tested by a common pad and the larger size makes it easier for probing equipment to contact the circuit probing pad.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, modified by Takahashi and Katkar, as applied to claim 1 above, in view of Ishii US 20190164923 A1 (hereinafter referred to as Ishii).
Chen, modified by Takahashi and Katkar, the scribe line structure of Claim 1, further comprising: one or more copper pillar bumps disposed on the one or more bump pads, such that the one or more copper pillar bumps are formed above the first top surface of the die region, wherein a diameter of each of the one or more copper pillar bumps is less than a width of each of the one or more bump pads.
Nevertheless, Ishii teaches
one or more copper pillar bumps (“metal post 25” para. 0041 FIG. 1) disposed on the one or more bump pads (“electrode pads 21” para. 0041), such that the one or more copper pillar bumps are formed above the first top surface of the die region (“metal posts 25” are formed on the top surface of “semiconductor substrate 20”, wherein a semiconductor chip is mounted, para. 0038), wherein a diameter of each of the one or more copper pillar bumps is less than a width of each of the one or more bump pads (the “first opening portions 82” within which “metal posts 25” are made have a smaller width than “electrode pads 21”, para. 0056 FIG. 6-7).
Chen, modified by Takahashi and Katkar, and Ishii teach semiconductor die regions with interconnections for external devices. Ishii teaches “metal posts 25” on “electrode pads 21” that are used for external connection. A “bump 30” is formed on each “metal post 25” for interconnection with “wiring substrate 40” (para. 0050). Such a connection establishes a large enough gap between the devices so that sealing resin can be poured in the gap, improving the bonding strength between “semiconductor substrate 20” and “wiring substrate 40” (para. 0051). The examiner understands that by forming “first opening portions 82” in “photosensitive material layer 83” smaller than “electrode pad 21”, the deposited metal that forms “metal post 25” is guaranteed to be over “electrode pad 21”. In other words, by making by making “opening portions 82”, formation of “metal posts 25” outside of “electrode pad 21” can be avoided even with minor misalignment. Darveaux et al. US 20220189866 A1, Yu et al., and Chuang et al. US 20210217703 A1, and US 20120306073 A1 all form a conductive pillar through a mask or resist pattern that is smaller than the pad similar to how Ishii forms “metal posts 25”. The formation process is understood to be well-known. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “metal posts 25” are rigid conductive structures that help establish a gap between bonded devices and openings in mask patterns are commonly made smaller than the pad they are formed over, such as “first opening portions 82” over “electrode pad 21”. This guarantees that “metal post 25” is not formed outside of “electrode pad 21”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the scribe line structure taught between Chen, Takahashi, and Katkar with the copper pillar bumps taught in Ishii. Copper pillar bumps offer a minimum standoff between bonded chips and area made in a well-known process involving openings in a mask pattern. Forming the openings smaller than the bump pads compensates for any potential deviation in the formation of the copper pillar bumps.
Regarding claim 8, Chen, modified by Takahashi, Katkar, and Ishii, teach the scribe line structure of Claim 7, wherein each of the one or more metal wires is extended to one of the two side edges of each circuit probing pad (“wiring structures 180” are connected to a side of each “testing pad 170”.
However, Chen, modified by Takahashi, Katkar, and Ishi, fails to teach wherein the dicing path is formed across the one or more circuit probing pads between two side edges thereof.
Nevertheless, the “test pads 170” in Chen, the “conductor pattern CP3” in Takahashi, and the “test pad 1610” in Katkar are shown being in a substantially central region of a dicing region. By dicing through the pads, the material removed will predominantly be in the dicing region and not the die region. Conversely, by cutting through a dicing path outside the area of the probing pads, portions of the die region and portions of the wires such as “wiring structures 180” may be removed. For example, Takahashi shows in FIG. 3-5 how dicing over “conductive pattern CP3” leaves remaining “conductor pattern pieces CP3a” while not affecting the “chip region CR” (para. 0068 and 0074). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that forming the dicing path across the areas of the “test pads 170” allows for portions of “test pads 170” to be removed while ensuring more or all of the region with “die 110aa” is intact.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that having the dicing path formed along and within the side edges of the circuit probing pad leads to removal of portions of the scribe line region while the die region is untouched.
Regarding claim 9, Chen, modified by Takahashi, Katkar, and Ishii, teach the scribe line structure of Claim 8, wherein the die region, the one or more bump pads, and the one or more copper pillar bumps are packaged into a semiconductor chip package (the region including the “die 110a”, the “device pads 160”, and the “metal posts 25” formed as taught in Ishi are considered a package).
Regarding claim 10, Chen, modified by Takahashi, Katkar, and Ishii, teach the scribe line structure of Claim 9 but fail to expressly teach wherein the scribe line region has a kerf portion and a remaining scribe line portion, wherein the dicing path is formed between the kerf portion and the remaining scribe line portion, wherein each of the one or more circuit probing pads has a kerf pad portion and a remaining circuit probing pad disposed on the kerf portion and a remaining scribe line portion respectively, wherein the remaining circuit probing pad is a remaining portion of each of the one or more circuit probing pads after the portion of each of the one or more circuit probing pads is diced out from the semiconductor wafer, wherein the remaining circuit probing pad is disabled for testing.
Nevertheless, the “test pads 170” in “dicing region 120” in Chen are understood to be later diced in a manner similar to how Takahashi dices through “conductive pattern 160” and Katkar dices through “test pad 1610”, as combined, where there are portions of the scribe region and probing pads that remain. The kerf region is considered the portion of “dicing region 120” away from the region with “die 110a” that remains after dicing while the remaining scribe line region is the remaining portion of “dicing region 120” adjacent to the region with “die 110a”. Similarly, the kerf pad portion is the remaining portion of “test pad 170” away from the “die 110a” after dicing and the remaining pad portion is the remaining portion of “test pad 170” in the “scribe region 120” adjacent to the region with “die 110a”. There is a remaining pad portion so that testing can still be done after dicing, as suggested by Katkar. However, Takahashi teaches that the possibility of testing with the conductive pattern depends on its size (para. 0010), and the examiner understands that this extends to a remaining portion of the conductive pattern: if the remaining portion of “conductive pattern CP3” after dicing is too small, testing may be difficult or not possible. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that dicing along the “test pads 170” will produce a kerf portion and a remaining portion, the remaining portion being part of the semiconductor chip package containing “die 110a”. The remaining portion of “test pad 170” may be disabled for testing if is too small.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that there will be a kerf portion with a kerf pad portion as well as a remaining scribe line portion with a remaining circuit probing pad portion when dicing is done along the circuit probing pads. The remaining circuit probing pad portion may be disabled for testing if it is too small to make contact with.
Regarding claim 11, Chen, modified by Takahashi, Katkar, and Ishii, teach the scribe line structure of Claim 9, wherein the die region (“semiconductor substrate 20” in Ishi is analogous to the region containing “die 110a” in Chen, para. 0038 FIG. 2) is electrically connected to a substrate of a printed circuit board (“wiring substrate 40” para. 0050) through the one or more copper pillar bumps (metal posts 25” para. 0041) using flip-chip packaging on the die region (“semiconductor substrate 20” and “wiring substrate 40” are packaged in a flip-chip manner as seen in FIG. 2, para. 0050).
Claim 12 and 17 are rejected under 35 U.S.C. 103 unpatentable over Chen et al. US 20230120504 A1 (hereinafter referred to as Chen), in view of Takahashi US 20230064636 A1 (hereinafter referred to as Takahashi), in view of Katkar et al. US 20150262972 A1 (hereinafter referred to as Katkar).
Regarding claim 12, Chen teaches
A semiconductor device (“example wafer 100”, para. 0049 FIG. 1A-1C), comprising:
a plurality of die regions (“plurality of dies 110aa, 110ab, 110ba, 110bb”, para. 0049 FIG. 1B-1C), disposed on a semiconductor wafer (“semiconductor substrate 102” para. 0049);
a scribe line region (“dicing regions 120” and “dicing regions 122” para. 0049 FIG. 1B, only one “dicing region 120” shown in FIG. 1C), disposed between the plurality of die regions;
a plurality of bump pads (“device pads 160” para. 0050), disposed on a first top surface of an edge region of each die region (“device pads 160” are disposed on an edge portion of the surface of “die 110aa”), for testing the die regions (“device pads 160” are connected to “testing pads 170” for testing in die region, para. 0054.)
a plurality of circuit probing pads (“test pads 170”), disposed on a second top surface of the scribe line region (“testing pads 170” are in the “dicing region 120” on “example wafer 100”); and
a plurality of metal wires (“wiring structures 180” para. 0054), disposed on the first top surface of each die region and the second top surface of the scribe line region, and configured to electrically connect the plurality of bump pads to the corresponding circuit probing pads (“wiring structures 180” extend along the top surface of “example wafer 110” to connect “device pads 160” in the “die 110aa” to the “testing pads 170” in the “dicing region 120”, para. 0054);
wherein the metal wires are formed on and in contact with the first top surface of the die region and the second top surface of the scribe line (since “wiring structures 180" are formed on “substrate portion 106” of an “exposed area 106” of the wafer, the examiner understands that the conductive structures including “wiring structures180” are formed directly on “example wafer 110”, para. 0049), such that the more metal wires are extended across the first top surface of the die region and the second top surface of the scribe line region (“wiring structures 180” extend from “dicing region 120” to “die 110aa”).
However, Chen fails to expressly teach wherein the dicing path is extended across the one or more circuit probing pads, such that when the semiconductor wafer is diced along the dicing path to separate the scribe line region from the die region, a portion of each of the one or more circuit probing pads is diced along the dicing path, wherein the dicing path is spaced apart from the metal wires.
Nevertheless, Chen teaches that a marker for dicing is formed in the “dicing region 120”. The examiner understands that the amount of portions of “test pads 170” that are diced depends on the dicing path, the area of the “testing pads 170”, and the dimensions of the saw blade or laser beam used for dicing in Chen. For example, Takahashi discusses in para. 0010 how smaller conductive patterns in a dicing region can be easier to remove completely, though contact with the pad for testing may be more difficult. Furthermore, Katkar teaches “test pads 1610” in a dicing lane (para. 0082 FIG. 16). After dicing, portions of the “test pads 1610” may remain so that testing can still be done. For testing to still be possible after dicing, the wire between “test pad 1610” and “die 110” must still be present. If the dicing path were along the wires, they would be removed and testing would not be possible. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the amount of remaining “test pads 170” in Chen depends on the dicing path and the relative sizes of the “test pads 170” and the dicing apparatus and portions of “test pads 170” may remain after dicing if testing is desired the dicing process. For testing to take place, the dicing path must be spaced away from wiring structures 180” so they are not broken.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjusting the dicing path in Chen with the teachings of Takahashi and Katkar. The dicing path may be formed across the probing pads so that at least portions of the probing pads are removed and the amount of remaining probing pads is determined by the dicing path, the dicing instrument width, and the size of the probing pads. By having remaining probing pad portions connected to the wires, testing can be done after dicing.
Regarding claim 17, Chen, modified by Takahashi and Katkar, teaches the semiconductor device of Claim 12, wherein a center of each circuit probing pad is disposed on a center line of the scribe line region (FIG. 1C suggests that “testing pads 170” are aligned in a substantially central area of “dicing region 120”), such that the center line of the scribe line region is positioned between two side edges of each circuit probing pad (since the “testing pads 170” appear to be aligned along the center of “dicing region 120”, a line drawn through the center is within the area of each “testing pads 170” as shown in annotated FIG. 1C).
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Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, modified by Takahashi and Katkar, as applied to claim 12 above.
Regarding claim 13, Chen teaches the semiconductor device of Claim 12, wherein each die region comprises functional circuitry (“die 110aa” includes “active area 140” which contains active devices, para. 0050), and the scribe line region is a non-functional region (since the “dicing regions 120 and 122” are to be diced away for the formation of other devices, the examiner understands the region has no functional circuitry beyond testing means, para. 0054).
However, Chen, modified by Takahashi and Katkar, fails to expressly teach wherein the one or more bump pads and the one or more metal wires are formed concurrently before the one or more circuit probing pads are formed.
Claim 13 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed “wherein the die region comprises functional circuitry, and the scribe line region is a non-functional region” need not be formed by the process of wherein “the one or more bump pads and the one or more metal wires are formed concurrently before the one or more circuit probing pads are formed”. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
Regarding claim 14, Chen, modified by Takahashi and Katkar, teaches the semiconductor device of Claim 13, wherein the bump pads are electrically connected to the functional circuitry of the die region (“device pads 160” are electrically coupled to the circuitry in “active area 140”, para. 0050).
Regarding claim 15, Chen, modified by Takahashi and Katkar, teaches the semiconductor device of Claim 14, wherein the functional circuitry of each die region is tested via a plurality of circuit probing needles electrically connected to external test equipment and placed on the circuit probing pads (“device pads 160” are coupled to the “active area 140” and “testing pads 170” are connected to “device pads 160” and are “arranged to receive one or more external probes for determining one or more characteristics of the one or more first active devices of the plurality of testing dies 110aa, 110ab”, para. 0054).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, modified by Takahashi and Katkar, as applied to claim 12 above, in view of Sakumoto et al US 5239191 A (hereinafter referred to as Sakumoto).
Chen, modified by Takahashi and Katkar, teaches the scribe line structure of Claim 12 but fails to teach wherein each circuit probing pad is larger than each bump pad.
Nevertheless, Sakumoto teaches wherein each circuit probing pad (“testing pad 15” col 3 lines 6-7 FIG. 2) is larger than each bump pad (“pad 13” col 3 line 13).
Chen, modified by Takahashi and Katkar, and Sakumoto teach the use of circuit probing pads in scribe line regions. Each “testing pad 15” is connected to a plurality of “pads 13” of each “chip area 12” (col 3 lines 12- 13). Because of this, “testing pad 15” acts as a common testing pad and its size can be made larger as long as it can fit in the “dicing line area 11” (col 3 lines 13-20). Furthermore, the examiner understands that a larger “testing pad 15” is easier to contact with a probe needle than a smaller testing pad since there is more area to make contact with. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that large “testing pads 15” can be used as common test pad for a plurality of the “pads 13” that is easier to contact with probing equipment.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the scribe line structure taught between Chen, Takahashi, and Katkar with the circuit probing pads taught in Sakumoto. A circuit probing pad can contact multiple bump pads and be made larger so that the bump pads can be tested by a common pad and the larger size makes it easier for probing equipment to contact the circuit probing pad.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, modified by Takahashi and Katkar, as applied to claim 12 above, in view of Ishii US 20190164923 A1 (hereinafter referred to as Ishii).
Chen, modified by Takahashi and Katkar, tach the semiconductor device of Claim 12, but fail to teach further comprising: a plurality of copper pillar bumps disposed on the bump pads, wherein the copper pillar bumps are formed above the first top surface of the die region, wherein a diameter of each of the copper pillar bumps is less than a width of each of bump pads; wherein a dicing process is performed on the semiconductor wafer along dicing path;
wherein the die region, the bump pads, and the copper pillar bumps are packaged into a semiconductor chip package; wherein the semiconductor wafer is diced along the dicing path to separate the die regions; wherein a portion of each of the probing pads is diced out from the semiconductor wafer to form a remaining circuit probing pad on the scribe line region, wherein the remaining circuit probing pad is disabled for testing.
Nevertheless, Ishii teaches
A plurality of copper pillar bumps (“metal post 25” para. 0041 FIG. 1) disposed on the bump pads (“electrode pads 21” para. 0041), wherein the copper pillar bumps are formed above the first top surface of the die region (“metal posts 25” are formed on the top surface of “semiconductor substrate 20”, wherein a semiconductor chip is mounted, para. 0038), wherein a diameter of each of the one or more copper pillar bumps is less than a width of each of the one or more bump pads (the “first opening portions 82” within which “metal posts 25” are made have a smaller width than “electrode pads 21”, para. 0056 FIG. 6-7);
wherein the die region, the bump pads, and the copper pillar bumps are packaged into a semiconductor chip package (“semiconductor substrate 20”, “electrode pads 21”, and “metal posts 25” can be considered a package);
Chen, modified by Takahashi and Katkar, and Ishii teach semiconductor die regions with interconnections for external devices. Ishii teaches “metal posts 25” on “electrode pads 21” that are used for external connection. A “bump 30” is formed on each “metal post 25” for interconnection with “wiring substrate 40” (para. 0050). Such a connection establishes a large enough gap between the devices so that sealing resin can be poured in the gap, improving the bonding strength between “semiconductor substrate 20” and “wiring substrate 40” (para. 0051). The examiner understands that by forming “first opening portions 82” in “photosensitive material layer 83” smaller than “electrode pad 21”, the deposited metal that forms “metal post 25” is guaranteed to be over “electrode pad 21”. In other words, by making by making “opening portions 82”, formation of “metal posts 25” outside of “electrode pad 21” can be avoided even with minor misalignment. Darveaux et al. US 20220189866 A1, Yu et al., and Chuang et al. US 20210217703 A1, and US 20120306073 A1 all form a conductive pillar through a mask or resist pattern that is smaller than the pad similar to how Ishii forms “metal posts 25”. The formation process is understood to be well-known. TheOne of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “metal posts 25” are rigid conductive structures that help establish a gap between bonded devices and openings in mask patterns are commonly made smaller than the pad they are formed over, such as “first opening portions 82” over “electrode pad 21”. This guarantees that “metal post 25” is not formed outside of “electrode pad 21”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the scribe line structure taught between Chen, Takahashi, and Katkar with the copper pillar bumps taught in Ishii. Copper pillar bumps offer a minimum standoff between bonded chips and area made in a well-known process involving openings in a mask pattern. Forming the openings smaller than the bump pads compensates for any potential deviation in the formation of the copper pillar bumps.
However, Chen, modified by Takahashi, Katkar, and Ishii fail to teach wherein a dicing process is performed on the semiconductor wafer along dicing path, wherein the semiconductor wafer is diced along the dicing path to separate the die regions; wherein a portion of each of the probing pads is diced out from the semiconductor wafer to form a remaining circuit probing pad on the scribe line region, wherein the remaining circuit probing pad is disabled for testing.
Nevertheless, claim 18 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. Furthermore, the process steps pertain to a different step in manufacturing to that of claim 12. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed “a plurality of copper pillar bumps disposed on the bump pads, wherein the copper pillar bumps are formed above the first top surface of the die region, wherein a diameter of each of the copper pillar bumps is less than a width of each of bump pads; wherein the die region, the bump pads, and the copper pillar bumps are packaged into a semiconductor chip package” need not be formed by the process of wherein “a dicing process is performed on the semiconductor wafer along dicing path, wherein the semiconductor wafer is diced along the dicing path to separate the die regions; wherein a portion of each of the probing pads is diced out from the semiconductor wafer to form a remaining circuit probing pad on the scribe line region, wherein the remaining circuit probing pad is disabled for testing”. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898