DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/5/2026 has been entered.
Response to Amendment
Applicant’s amendments filed 1/14/2026 have been entered and considered. The amendments to claims 1-5, 7, 10-12, and 17, and the cancellation of claims 6, 8-9, and 18 are acknowledged.
In view of the amendment to claims 1-2 regarding the removal of “a dicing path, which is embodied as an alignment mark”, the rejection under 35 U.S.C. 112(b) is withdrawn.
In view of the amendments of claim 1 to direct the claim to a device after dicing, the rejection under 35 U.S.C. 112(a) is withdrawn.
Response to Arguments
Applicant’s arguments, filed 5/5/2026, with respect to the rejection of claim 1 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lin, Kaltalioglu, and Chen as set forth below.
Applicant’s arguments with respect to claim 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5, 7, 10, and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 includes language at different stages of manufacturing rendering the claim indefinite. The claim recites "a die region, disposed on a semiconductor wafer”. A wafer typically includes a plurality of die regions before they are cut, so the use of the term wafer implies a structure before dicing takes place. Meanwhile, kerf portions and remaining scribe line portions are described as extending from the die region. Kerf portions and remaining scribe line portions are formed after a wafer is diced, such that the existence of kerf portions imply that there is no longer a whole wafer.
Claims 2-5, 7, 10 and 11 are rejected based on the dependency on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 unpatentable over Lin et al. US 20240079301 A1 (hereinafter referred to as Lin), in view of Kaltalioglu et al. US 20100314619 A1 (hereinafter referred to as Kaltalioglu, in view of Chen et al. US 20230120504 A1 (hereinafter referred to as Chen).
Regarding claim 1, Lin teaches
A semiconductor chip package (“electronic package 3 para. 0039 FIG. 3B), comprising:
a die region (“electronic element 22” para. 0043), disposed on a semiconductor wafer;
one or more bump pads (“electrode pads 220, 220a” para. 0043), disposed on a first top surface of an edge region of the die region (“electrode pads 220” are on the surface of “electronic element 20” facing “circuit structure 24”);
one or more copper pillar bumps (“conductive bumps 221, 221a such as copper pillars” para. 0051) disposed on top surfaces of the one or more bump pads (“conductive bumps 221, 221” are formed on “electrode pads 220, 220a”, para. 0051), respectively; and
a substrate (“circuit structure 24” para. 0042) comprising one or more second metal wires (“circuit layers 241” with “conductive sheet 243” para. 0051) and one or more solder balls (“conductive elements 25” para. 0044) disposed on the one or more second metal wires, wherein the one or more copper pillar bumps are electrically connected to the substrate via the one or more second metal wires (“conductive bumps 221” connect to “conductive sheet 243” and “conductive bumps 221a” connect to a “circuit layer 241”, para. 0051), and the one or more solder balls are disposed on a surface of the substrate opposite to the die region (“conductive elements 25” are disposed on a side of “circuit structure 24” opposite to “electronic element 22”);
However, Lin fails to teach a scribe line region extended from the die region, having a kerf portion and a remaining scribe line portion, wherein the kerf portion is formed by dicing an original scribe line region along a boundary of the die region a dicing path; one or more circuit probing pads, disposed on a second top surface of the scribe line region and along the boundary of the die region, wherein each of the one or more circuit probing pads has a kerf portion and a remaining circuit probing pad, wherein the kerf portion of each circuit probing pad is disposed on the kerf portion of the scribe line region, and the remaining portion of each circuit probing pad is disposed on the remaining scribe line portion; one or more first metal wires, disposed on the first top surface of the die region and the second top surface of the scribe line region, and configured to electrically connect the one or more bump pads to the remaining circuit probing pads of the one or more circuit probing pads, respectively; wherein the one or more first metal wires are formed on and in contact with the first top surface of the die region and the second top surface of the scribe line, such that the one or more first metal wires are extended across the first top surface of the die region and the second top surface of the scribe line region.
Nevertheless, Kaltalioglu teaches
a scribe line region (“regions 210” with exposed side edge of “die 201” para. 0057 FIG. 5-7 and 9) extended from the die region, having a kerf (exposed side edge of “die 201” as seen after the singulation in FIG. 7 and 9) portion and a remaining scribe line portion (“region 210”), wherein the kerf portion is formed by dicing an original scribe line region along a boundary of the die region (side edge of “die 201” is exposed after the singulation in FIG 7);
one or more circuit probing pads (remaining “second contact pad 244c” and exposed edge portion, para. 0052 FIG. 7), disposed on a second top surface of the scribe line region and along the boundary of the die region (remaining “second contact pad 244c” and exposed edge portion are disposed on the outer edge top surface of “die 210”), wherein each of the one or more circuit probing pads has a kerf portion (exposed edge portion of “second contact pad 244c”) and a remaining circuit probing pad (remaining “second contact pad 244c” in “die 210” is a remaining portion after singulation), wherein the kerf portion of each circuit probing pad is disposed on the kerf portion of the scribe line region (exposed edge portion of “second contact pad 244c” is disposed on the exposed portion of “die 210”), and the remaining portion of each circuit probing pad is disposed on the remaining scribe line portion (remaining “second contact pad 244c” is disposed on the “region 210”);
Lin and Kaltalioglu teach semiconductor packages comprising a die on a substrate. The “die 210” in Kaltalioglu includes remaining portion of “second contact pad 244c” after the “die 210” are singulated. “Second contact pad 244c” is part of a “test structure 240” used to test electrical performance before singulation (para. 0051). The examiner understands that portions of “second contact pad 244c” remain because the dicing apparatus has a smaller width than the “second contact pad 244c”; if the width of the dicing apparatus, a saw blade or a laser (para. 0026) were equal or greater than the width of “second contact pad 244c”, it is reasonable to expect that no “second contact pad 244c” would remain. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “second contact pad 244c” can be used for testing the “die 210” before singulation and portion of “second contact pad 244c” remain when the saw blade or laser are of a smaller width than the width of “second contact pad 244c”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package taught in Lin with the remaining probing pads in a remaining scribe line region taught in Kaltalioglu. Probing pads enable testing of the die while still in a wafer and parts of the probing pads will remain after singulation when the cutting apparatus has a smaller width than the probing pads.
However, Lin, modified by Kaltalioglu fail to teach one or more first metal wires, disposed on the first top surface of the die region and the second top surface of the scribe line region, and configured to electrically connect the one or more bump pads to the remaining circuit probing pads of the one or more circuit probing pads, respectively; wherein the one or more first metal wires are formed on and in contact with the first top surface of the die region and the second top surface of the scribe line, such that the one or more first metal wires are extended across the first top surface of the die region and the second top surface of the scribe line region.
Nevertheless, Chen teaches
one or more first metal wires (“wiring structures 180” para. 0054 FIG. 1C), disposed on the first top surface of the die region and the second top surface of the scribe line region (“wiring structures 180” are disposed on the top surface of “die 110aa” and the top surface of “scribe line region 120”, para. 0049), and configured to electrically connect the one or more bump pads (“device pads 160”, para. 0050) to the one or more circuit probing pads (“test pads 170” para.0054), respectively;
wherein the one or more first metal wires are formed on and in contact with the first top surface of the die region and the second top surface of the scribe line, such that the one or more first metal wires are extended across the first top surface of the die region and the second top surface of the scribe line region (“wiring structures 180” are disposed on and extend across the top surface of “die 110aa” and the top surface of “scribe line region 120”, para. 0049).
Lin, modified by Kaltalioglu, and Chen teach semiconductor die connected to testing structures. While the “second contact pad 244c” connects to “active areas 249” directly below through a series of vias and pads (Kaltalioglu para. 0038), the “test pads 170” are connected to “device pads 160” through “wiring structures 180”. “Device pads 160” are coupled to the to the active devices in the “active area 140” of each die region (Chen para. 0050), such that the active devices can be tested through use of the “test pads 170”. The examiner understands that the “wiring structures 180” will remain after the singulation process in Kaltalioglu since the width of the saw blade or laser beam is less than that of the probing pads. In Kaltalioglu, the singulation removes the via and pad structures that connect to the “active areas 249” (para. 0073). Meanwhile, since “wiring structures 180” and “second contact pad 244c” remain, testing may still be done after singulation. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “wiring structures 180” can be used as an alternative to connect to the active devices in “electronic element 22” in Lin with the “second contact pad 244c” in Kaltalioglu that offers the ability of testing the “electronic element 22” after dicing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package taught between Lin and Kaltalioglu with the metal wires taught in Chen. Metal wires can directly connect the probing pads to the bump pads to be electrically connected to the active devices in the die region and enable testing after dicing.
Lin, modified by Kaltalioglu and Chen, further teaches
The one or more metal wires configured to electrically connect the one or more bump pads to the remaining circuit probing pads of the one or more circuit probing pads, respectively (“wiring structures 180” from Chen are formed between the remaining “second bonding pads 244c” and the “electrode pads 220, 220a”);
Regarding claim 2, Lin, modified by Kaltalioglu and Chen, teach the semiconductor chip package of Claim 1, wherein the die region comprises functional circuitry (“electronic element 22” is an active element, passive element, or combination of both, and is understood to have circuitry that has a function over an electrical signal, para. 0024), and the scribe line region is a non-functional region (“region 210” and the exposed sides of “die 201” contain remaining “second contact pads 244c” and “wiring structures 180” as modified, which may be considered to not have a function over an electrical signal other than transmission).
However, Lin, modified by Kaltalioglu and Chen, fails to expressly teach wherein the one or more bump pads and the one or more metal wires are formed concurrently before the one or more circuit probing pads are formed.
Claim 2 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed “wherein the die region comprises functional circuitry, and the scribe line region is a non-functional region” need not be formed by the process of wherein “the one or more bump pads and the one or more metal wires are formed concurrently before the one or more circuit probing pads are formed”. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
Regarding claim 3, Lin, modified by Kaltalioglu and Chen, teaches the semiconductor chip package of Claim 2, wherein the one or more bump pads are electrically connected to the functional circuitry of the die region (“electrode pads 220, 220a” serve as power contacts and signal contacts, para. 0024, which are understood to go to and from the circuitry in “electronic element 22”. Similarly, “device pads 160” are coupled to the to the active devices in the “active area 140” of each die region, Chen para. 0050).
Regarding claim 4, Lin, modified by Kaltalioglu and Chen, teaches the semiconductor chip package of Claim 3, wherein the functional circuitry of the die region is tested via one or more circuit probing needles electrically connected to external test equipment and placed on the one or more circuit probing pads (as modified, the active and/or passive elements in “electronic element 22” are tested through the “second contact pad 244c” from Kaltalioglu with a probing apparatus like an ohmmeter, para. 0051. The prior art structure is capable of performing the intended use.).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lin, modified by Kaltalioglu and Chen, as applied to claim 1 above, in view of Sakumoto et al US 5239191 A (hereinafter referred to as Sakumoto).
Lin, modified by Kaltalioglu and Chen, teaches the scribe line structure of Claim 12, wherein the one or more copper pillar bumps are in direct contact with the one or more second metal wires disposed on a surface of the substrate facing toward the die region (“conductive sheet 243” of “circuit structure 24” directly contacts “conductive bumps 221” and “circuit layer 24” is in contact with “conductive bumps 241a”, para. 0033).
However, Lin, modified by Kaltalioglu and Chen, fails to teach wherein each circuit probing pad is larger than each bump pad.
Nevertheless, Sakumoto teaches wherein each circuit probing pad (“testing pad 15” col 3 lines 6-7 FIG. 2) is larger than each bump pad (“pad 13” col 3 line 13).
Lin, modified by Kaltalioglu and Chen, and Sakumoto teach the use of circuit probing pads in scribe line regions. Each “testing pad 15” is connected to a plurality of “pads 13” of each “chip area 12” (col 3 lines 12- 13). Because of this, “testing pad 15” acts as a common testing pad and its size can be made larger as long as it can fit in the “dicing line area 11” (col 3 lines 13-20). Furthermore, the examiner understands that a larger “testing pad 15” is easier to contact with a probe needle than a smaller testing pad since there is more area to make contact with. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that large “testing pads 15” can be used as common test pad for a plurality of the “pads 13” that is easier to contact with probing equipment.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the scribe line structure taught between Lin, Kaltalioglu, and Chen, with the circuit probing pads taught in Sakumoto. A single circuit probing pad can contact multiple bump pads and be made larger so that the bump pads can be tested by a common pad and the larger size makes it easier for probing equipment to contact the circuit probing pad.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lin, modified by Kaltalioglu and Chen, and Sakumoto, as applied to claim 1 above, in view of Ishii US 20190164923 A1 (hereinafter referred to as Ishii).
Lin, modified by Kaltalioglu and Chen, and Sakumoto the scribe line structure of Claim 1, wherein the one or more copper pillar bumps are disposed on the one or more bump pads, such that the one or more copper pillar bumps are formed above the first top surface of the die region (“conductive bumps 221, 221” are formed on “electrode pads 220, 220a” on the surface of “electronic element 22” facing the “circuit structure 24”, para. 0051).
However, Lin, modified by Kaltalioglu and Chen, and Sakumoto fail to expressly teach wherein a diameter of each of the one or more copper pillar bumps is less than a width of each of the one or more bump pads.
Nevertheless, Ishii teaches
wherein a diameter of each of the one or more copper pillar bumps is less than a width of each of the one or more bump pads (the “first opening portions 82” within which “metal posts 25” are made have a smaller width than “electrode pads 21”, para. 0056 FIG. 6-7).
Lin, modified by Kaltalioglu and Chen, and Sakumoto and Ishii teach semiconductor die regions with interconnections for external devices. Ishii teaches “metal posts 25” on “electrode pads 21” that are used for external connection. A “bump 30” is formed on each “metal post 25” for interconnection with “wiring substrate 40” (para. 0050). The “electrode pads 21” remain covered during the formation of “metal posts 25” and “solder balls 31” to avoid exposure of the seed layer under “electrode pads 21” (para. 0059 FIG. 4-12). From this, the examiner understands the diameter of “metal posts 25” are at least slightly greater than “electrode pads 21”.) Furthermore, by making by making “opening portions 82” smaller, formation of “metal posts 25” outside of “electrode pad 21” can be avoided even with minor misalignment. Darveaux et al. US 20220189866 A1, Yu et al., and Chuang et al. US 20210217703 A1, and US 20120306073 A1 all form a conductive pillar through a mask or resist pattern that is smaller than the pad similar to how Ishii forms “metal posts 25”. The formation process is understood to be well-known. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that openings in mask patterns are commonly made smaller than the pad they are formed over, such as “first opening portions 82” over “electrode pad 21”. This guarantees that “metal post 25” is not formed outside of “electrode pad 21” and avoids exposing the seed layer of “electrode pad 21”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the scribe line structure taught between Lin, Kaltalioglu, and Chen with the copper pillar bumps taught in Ishii. Copper pillar bumps are made in a well-known process involving openings in a mask pattern. Forming the openings smaller than the bump pads compensates for any potential deviation in the formation of the copper pillar bumps and prevents exposing the bump pad and its seed layer during processing of the copper pillar bumps.
Claim 10 is rejected under 35 U.S.C. 103 unpatentable over Lin, modified by Kaltalioglu and Chen, in view of Katkar et al. US 20150262972 A1 (hereinafter referred to as Katkar), in view of Takahashi US 20230064636 A1 (hereinafter referred to as Takahashi).
Lin, modified by Kaltalioglu and Chen the semiconductor chip package of claim 1 but fail to teach wherein the remaining circuit probing pad is disabled for testing.
Nevertheless, there is a remaining “second contact pad 244c” portion after dicing. The examiner understands testing can still be done after dicing. Katkar indicates in para. 0082. That a “test pad 1610” can be divided and used for further testing or destroyed due to dicing. However, Takahashi teaches that the possibility of testing with the conductive pattern depends on its size (para. 0010), and the examiner understands that this extends to a remaining portion of the conductive pattern: if the remaining portion of “second contact pad 244c” after dicing is too small, testing may be difficult or not possible. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that dicing along the “second contact pad 244c” will leave a remaining portion disabled for testing if is too small.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the remaining circuit probing pad portion may be disabled for testing if it is too small to make contact with.
Regarding claim 11, Lin, modified by Kaltalioglu and Chen, teach the semiconductor chip package of Claim 1, wherein the die region is electrically connected to a substrate of a printed circuit board through the one or more copper pillar bumps using flip-chip packaging on the die region (“electronic element 22” is bonded to “circuit structure 24” in a flip-chip manner, “circuit structure 24” being a carrier board, para. 0041-0043).
Claim 12 and 17 are rejected under 35 U.S.C. 103 unpatentable over Chen et al. US 20230120504 A1 (hereinafter referred to as Chen), in view of Takahashi US 20230064636 A1 (hereinafter referred to as Takahashi), in view of Katkar et al. US 20150262972 A1 (hereinafter referred to as Katkar), in view of Hsieh et al. US 20150041985 A1 (hereinafter referred to as Hsieh), in view of Machida US 20130134594 A1 (hereinafter referred to as Machida), in view of Salinas et al. US 20210104468 A1 (hereinafter referred to as Salinas).
Regarding claim 12, Chen teaches
A semiconductor device (“example wafer 100”, para. 0049 FIG. 1A-1C), comprising:
a plurality of die regions (“plurality of dies 110aa, 110ab, 110ba, 110bb”, para. 0049 FIG. 1B-1C), disposed on a semiconductor wafer (“semiconductor substrate 102” para. 0049);
a scribe line region (“dicing regions 120” and “dicing regions 122” para. 0049 FIG. 1B, only one “dicing region 120” shown in FIG. 1C), disposed between the plurality of die regions;
a plurality of bump pads (“device pads 160” para. 0050), disposed on a first top surface of an edge region of each die region (“device pads 160” are disposed on an edge portion of the surface of “die 110aa”), for testing the die regions (“device pads 160” are connected to “testing pads 170” for testing in die region, para. 0054.)
a plurality of circuit probing pads (“test pads 170”), disposed on a second top surface of the scribe line region (“testing pads 170” are in the “dicing region 120” on “example wafer 100”); and
a plurality of metal wires (“wiring structures 180” para. 0054), disposed on the first top surface of each die region and the second top surface of the scribe line region, and configured to electrically connect the plurality of bump pads to the corresponding circuit probing pads (“wiring structures 180” extend along the top surface of “example wafer 110” to connect “device pads 160” in the “die 110aa” to the “testing pads 170” in the “dicing region 120”, para. 0054);
wherein the metal wires are formed on and in contact with the first top surface of the die region and the second top surface of the scribe line (since “wiring structures 180" are formed on “substrate portion 106” of an “exposed area 106” of the wafer, the examiner understands that the conductive structures including “wiring structures180” are formed directly on “example wafer 110”, para. 0049), such that the more metal wires are extended across the first top surface of the die region and the second top surface of the scribe line region (“wiring structures 180” extend from “dicing region 120” to “die 110aa”).
However, Chen fails to expressly teach wherein a dicing path is spaced apart from the metal wires, wherein an area of each die region is equal to 32mm2, and a total area of the plurality of bump pads is equal to 0.02mm2.
Nevertheless, Chen teaches that a marker for dicing is formed in the “dicing region 120”. The examiner understands that the number of portions of “test pads 170” that are diced depends on the dicing path, the area of the “testing pads 170”, and the dimensions of the saw blade or laser beam used for dicing in Chen. For example, Takahashi discusses in para. 0010 how smaller conductive patterns in a dicing region can be easier to remove completely, though contact with the pad for testing may be more difficult. Furthermore, Katkar teaches “test pads 1610” in a dicing lane (para. 0082 FIG. 16). After dicing, portions of the “test pads 1610” may remain so that testing can still be done. For testing to still be possible after dicing, the wire between “test pad 1610” and “die 110” must still be present. If the dicing path were along the wires, they would be removed and testing would not be possible. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the amount of remaining “test pads 170” in Chen depends on the dicing path and the relative sizes of the “test pads 170” and the dicing apparatus and portions of “test pads 170” may remain after dicing if testing is desired the dicing process. For testing to take place, the dicing path must be spaced away from wiring structures 180” so they are not broken.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjusting the dicing path in Chen with the teachings of Takahashi and Katkar. The dicing path may be formed across the probing pads so that at least portions of the probing pads are removed and the amount of remaining probing pads is determined by the dicing path, the dicing instrument width, and the size of the probing pads. By dicing away from the wires, testing can be done after dicing with remaining probing pad regions.
However, Chen, modified by Takahashi and Katkar, fails to teach wherein an area of each die region is equal to 32mm2, and a total area of the plurality of bump pads is equal to 0.02mm2.
Nevertheless, it is known that die can have different sizes depending on factors such as package size requirements, capability of performing their function, or thermal characteristics. Die may have areas in the range of 4-100mm2 as shown in Hsieh para. 0041, for example. Larger die having sizes such as 10mm x 10mm may be subject to warpage during flip chip binding, as taught by Chu US 20180090460 A1 in para. 0007. As further indicated in Hsieh, a specific example is mentioned of dies being 5.8mm x 5.3mm, or 30.74mm2, and the die may have functions such as signal processors, memory devices, or MEMs devices (Hsieh para. 0041). Such a die can be accommodated into smaller packages and be less susceptible to warpage than a die of a larger size. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the area of each die is chosen based on desired final package size, capability, and the possibility of warpage during bonding.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Chen, Takahashi, and Katka with the die size taught in Hsieh. Die of different functionality can be made in those sizes, where the smaller die may fit into smaller packages and be less susceptible to warpage.
Furthermore, the applicant must show that the particular value is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range (MPEP 2144.05 (III)(A)).
However, and a total area of the plurality of bump pads is equal to 0.02mm2.
Nevertheless, Machida teaches an “electrode pad 11” having a square shape with side lengths of 50microns and a “pillar-shaped electrode terminal 13” bonded to its surface (para. 0025 FIG. 1B). In this example, each “electrode pad 11” has an area of 0.0025mm2. Meanwhile, Salinas teaches a “redistribution chip pad 131” of a “semiconductor chip 100” with a greatest width between 3.02-10.07 microns (Salinas para. 0019 and 0030). Salinas is silent to the shape of the “redistribution chip pad 131” but the examiner understands the area is at most that of a square of about 9.12-101.40microns2, or about 9.12x10-6 – 101.40x10-6 mm2. The total area of all the pads in a wafer will depend on the number of pads and the sizes of each. In the case of the “electrode pad 11” of Machida, 10-100 pads across a plurality of die will have a total pad area of 0.025-0.25mm2. Meanwhile, 10-100 “redistribution chip pads 131” with areas 101.40x10-6 mm2 from multiple chip in Salinas will have a total area of about 0.101 mm2. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the total area of “device pads 160” will depend on the desired size of the pads and the amount of “device pads 160” required for interconnections with the “active area 120”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the total area of the bump pads depends on size and number of bump pads in each die region in the semiconductor wafer.
Furthermore, the applicant must show that the particular value is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range (MPEP 2144.05 (III)(A)).
Regarding claim 17, Chen, modified by Takahashi, Katkar, Hsieh, Machida, and Salinas, teaches the semiconductor device of Claim 12, wherein a center of each circuit probing pad is disposed on a center line of the scribe line region (FIG. 1C suggests that “testing pads 170” are aligned in a substantially central area of “dicing region 120”), such that the center line of the scribe line region is positioned between two side edges of each circuit probing pad (since the “testing pads 170” appear to be aligned along the center of “dicing region 120”, a line drawn through the center is within the area of each “testing pads 170” as shown in annotated FIG. 1C).
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Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, modified by Takahashi and Katkar, Hsieh, Machida, and Salinas, as applied to claim 12 above.
Regarding claim 13, Chen, modified by Takahashi, Katkar, Hsieh, Machida, and Salinas, teaches the semiconductor device of Claim 12, wherein each die region comprises functional circuitry (“die 110aa” includes “active area 140” which contains active devices, para. 0050), and the scribe line region is a non-functional region (since the “dicing regions 120 and 122” are to be diced away for the formation of other devices, the examiner understands the region has no functional circuitry beyond testing means, para. 0054).
However, Chen, modified by Takahashi and Katkar, Hsieh, Machida, and Salinas, fails to expressly teach wherein the one or more bump pads and the one or more metal wires are formed concurrently before the one or more circuit probing pads are formed.
Claim 13 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed “wherein the die region comprises functional circuitry, and the scribe line region is a non-functional region” need not be formed by the process of wherein “the one or more bump pads and the one or more metal wires are formed concurrently before the one or more circuit probing pads are formed”. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
Regarding claim 14, Chen, modified by Takahashi, Katkar, Hsieh, Machida, and Salinas, teaches the semiconductor device of Claim 13, wherein the bump pads are electrically connected to the functional circuitry of the die region (“device pads 160” are electrically coupled to the circuitry in “active area 140”, para. 0050).
Regarding claim 15, Chen, modified by Takahashi, Katkar, Hsieh, Machida, and Salinas, teaches the semiconductor device of Claim 14, wherein the functional circuitry of each die region is tested via a plurality of circuit probing needles electrically connected to external test equipment and placed on the circuit probing pads (“device pads 160” are coupled to the “active area 140” and “testing pads 170” are connected to “device pads 160” and are “arranged to receive one or more external probes for determining one or more characteristics of the one or more first active devices of the plurality of testing dies 110aa, 110ab”, para. 0054).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, modified by Takahashi and Katkar, Hsieh, Machida, and Salinas, as applied to claim 12 above, in view of Sakumoto et al US 5239191 A (hereinafter referred to as Sakumoto).
Chen, modified by Takahashi, Katkar, Hsieh, Machida, and Salinas, teaches the scribe line structure of Claim 12 but fails to teach wherein each circuit probing pad is larger than each bump pad.
Nevertheless, Sakumoto teaches wherein each circuit probing pad (“testing pad 15” col 3 lines 6-7 FIG. 2) is larger than each bump pad (“pad 13” col 3 line 13).
Chen, modified by Takahashi, Katkar, Hsieh, Machida, and Salinas, and Sakumoto teach the use of circuit probing pads in scribe line regions. Each “testing pad 15” is connected to a plurality of “pads 13” of each “chip area 12” (col 3 lines 12- 13). Because of this, “testing pad 15” acts as a common testing pad and its size can be made larger as long as it can fit in the “dicing line area 11” (col 3 lines 13-20). Furthermore, the examiner understands that a larger “testing pad 15” is easier to contact with a probe needle than a smaller testing pad since there is more area to make contact with. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that large “testing pads 15” can be used as common test pad for a plurality of the “pads 13” that is easier to contact with probing equipment.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the scribe line structure taught between Chen, Takahashi, Katkar, Hsieh, Machida, and Salinas, with the circuit probing pads taught in Sakumoto. A circuit probing pad can contact multiple bump pads and be made larger so that the bump pads can be tested by a common pad and the larger size makes it easier for probing equipment to contact the circuit probing pad.
Conclusion
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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