DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
This is a final office action in response to the applicant’s arguments and remarks filed on 11/24/2025. Claims 1-9 are pending in the current office action. Claims 1-9 have been amended by the applicant.
Status of the Rejection
The Claim objections have been overcome by the applicant's amendments.
All 35 U.S.C. § 112(b) rejections from the previous office action are withdrawn in view of the Applicant’s amendment.
All 35 U.S.C. § 102 and 103 rejections from the previous office action are withdrawn in view of the Applicant’s amendment.
New grounds of rejection under 35 U.S.C. § 103 are necessitated by the amendments.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 4, 5, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Tu et al. (US-20130164930-A1) in view of Cai et al. (CN-114724952-A, machine translation) and Li et al. (CN-108766878-A, machine translation).
Regarding Claim 1, Tu teaches a method for improving a height difference between gates (Paragraph [0008] method for forming a gate structure), wherein the method comprises:
step 1: providing a silicon substrate (Paragraph [0010] the substrate provided can be a silicon substrate),
forming narrower dummy gate structures and wider dummy gate structures on the silicon substrate, wherein the wider dummy gate structures are disposed adjacent to the narrower dummy gate structures, wherein heights of the narrower dummy gate structures and heights of the wider dummy gate structures are equal (Paragraph [0013] Figure 3 lower pattern density region gate structures (elements 130), which are the gates with the iso region (element 150), can be considered equivalent to the claimed "narrower dummy gate structures" and higher pattern density pattern gate structures (elements 140), which are the gates within the dense region (element 160), can be considered equivalent to the claimed "wider dummy gate structures") Paragraph [0014] the height of the gate structures is substantially similar);
forming a silicon nitride layer on surfaces of the narrower dummy gate structures and on surfaces of the wider dummy gate structures (Paragraph [0018] Figure 5 a polishing-stop layer (element 240) is formed over the surfaces of the gate structures, and may comprise silicon nitride);
depositing an interlayer dielectric layer on the silicon nitride layer over the narrower dummy gate structures and the wider dummy gate structures, wherein the interlayer dielectric layer fills gaps between adjacent narrower dummy gate structures and wider dummy gate structures (Paragraph [0018] an inter-layer dielectric layer (element 250) is formed over the polishing-stop layer and fills the gaps between the gate structures as shown in Figure 5);
step 2: polishing the interlayer dielectric layer until top surfaces of the wider dummy gate structures are higher than top surfaces of the narrower dummy gate structures by a first height difference (Paragraphs [0016-0017] Figure 4 gates in the iso region (element 150), equivalent to the "narrower dummy gate structures", have a gate height (element 210) and gates in the dense region (element 160), equivalent to the "wider dummy gate structures", have a gate height (element 220). The gate height can be 220 greater than the gate height 210. Paragraph [0019] Figure 6 a polishing process is performed on the interlayer dielectric layer, and at the end of this process the gate heights 220 is still greater than the gate height 210 and the top surface of the wider gate structure further comprises the sacrificial layer (element 250A), and therefore is even higher and the polishing was conducted until the top surface of the wider gate structure was higher);
step 3: removing the narrower dummy gate structures and the wider dummy gate structures to form wider trenches and narrower trenches, wherein a height of the silicon nitride layer on sidewalls of the wider trenches is equal to a height of an interlayer dielectric layer adjacent to the wider trenches, and a height of the silicon nitride layer on sidewalls of the narrower trenches is equal to a height of an interlayer dielectric layer adjacent to the narrower trenches (Paragraph [0028] Figure 8 the dummy gate electrode layer (element 110) is removed to form trenches from both narrower and wider gate structures. On the sidewall of both the wider and narrower trenches, there is a height of a silicon nitride layer (element 240) has the same height as the interlayer dielectric layer (element 250). See Reference Image 1 below);
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step 4: depositing a dielectric material on the wider trenches and the narrower trenches (Paragraph [0032] can include a deposition of a high-k layer that is formed in the trenches);
step 5: depositing an aluminum layer to fill the wider trenches and the narrower trenches and to cover the dielectric material (Paragraph [0029] metal gate electrodes are formed, that can contain aluminum. Paragraph [0032] a metal gate electrode layer is formed over the high-k layer); and
step 6: performing chemical-mechanical polishing on the aluminum layer (Paragraph [0029] a CMP process is conducted after the deposition process of for the metal gate electrodes).
Tu fails to explicitly teach that the dielectric material deposited in step 4 is deposited over the bottoms and the sidewalls of the trenches and on a top surface of the interlayer dielectric layer.
Cai teaches method of forming metal gate structures ([abstract]). Cai teaches a method where a dummy gate is replaced with a metal gate (Paragraph [0042]). Cai teaches that in the process of forming a metal gate structure a gate dielectric layer is deposited conformally in the recess left from the dummy gate and on a top surface of an interlayer dielectric material (Paragraph [0043] gate dielectric layer (element 94) is conformally deposited in the recesses and over an interlayer dielectric (ILD, element 90). As can be seen in Figure 9, the conformal deposition results in a deposition on the sidewalls and bottom of the recess).
It would have been obvious to one of ordinary skill in the art to have modified the method of Tu by modifying the deposition of a dielectric material such that the deposition included a conformal deposition within the recess left by the removal of the dummy gate structures and included a deposition over a top surface of the interlayer dielectric material, as taught by Cai.
This modification would have been obvious as it would have been the combination of prior art elements according to known methods to yield predictable results. The deposition would have created the conformal layer within the recess and over the interlayer dielectric as taught by Cai, and the further processing steps taught by Tu would have functioned the same in completing the creation of the metal gate. See MPEP 2143(I)(A).
Tu fails to explicitly teach that the aluminum layer is deposited over the dielectric material on the top surface of the interlayer dielectric layer.
Li teaches a method for forming gates (Paragraph [0006]). Li teaches a method where dummy gate structures are formed (Paragraphs [0049] and [0063]). Li teaches that after the removal of the dummy gate structures (Paragraph [0071]) the metal gate material is deposited such that it fills the trenches left and covers the interlayer film between the gates (Paragraph [0072]).
It would have been obvious to one of ordinary skill in the art to have modified the method of modified Tu, such that the deposition of the aluminum both filled the trenches and covered the areas outside of the trenches that included the interlayer dielectric layer. With this modification, given the modification from the teachings of Cai above, the aluminum layer would be deposited over the dielectric material on the top surface of the interlayer dielectric layer.
This modification would have been obvious as it would have been the combination of prior art elements according to known methods to yield predictable results. The deposition would have created an aluminum layer over the dielectric layer and the further processing steps taught by Tu would have functioned the same in completing the creation of the metal gate. See MPEP 2143(I)(A).
Tu fails to explicitly teach that the chemical-mechanical polishing of the aluminum layer is conducted until a top surface of the aluminum layer in the wider trenches is lower than a top surface of the aluminum layer in the narrower trenches by a second height difference after the dielectric material on the interlayer dielectric layer is removed, wherein the first height difference is larger than the second height difference.
However, Tu teaches that the difference in height between the top surface of the aluminum layer in the wider trenches and the height difference between the top surface of the aluminum layer in the narrower trenches can be less than about 50 angstroms (Paragraph [0027] the height difference between the gate height 310, equivalent to the height of the narrower gate structures, and the gate height 320, equivalent to the height of the wider gate structures, is less than about 50 angstroms. Paragraph [0030] the gate heights 360 and 370, after the metal gate electrode layer has been deposited and polished, are only slightly less than the gate heights 310 and 320, with a gate loss amount of 0-200 angstroms). Tu further teaches that the first height difference can be greater than 100 angstroms (Paragraphs [0016-0017] Figure 4 gates in the iso region (element 150), equivalent to the "narrower dummy gate structures", have a gate height (element 210) and gates in the dense region (element 160), equivalent to the "wider dummy gate structures", have a gate height (element 220). The gate height 220 is greater than the gate height 210. Paragraph [0019] Figure 6 a polishing process is performed on the interlayer dielectric layer, and at the end of this process the gate heights 220 is still greater than the gate height 210 and the top surface of the wider gate structure further comprises the sacrificial layer (element 250A). Paragraph [0021] the thickness of the sacrificial layer can be about 100 to about 600 angstroms. Therefore, the total height difference equivalent to the claimed first height difference can be greater than about 100 to greater than about 600 angstroms).
It would have been obvious to one of ordinary skill in the art to have selected and incorporated gate height 360 and gate height 370 at levels such the value of ( [gate height 360] – [gate height 370] ) was within the disclosed range of about -50 to about 50 angstroms, including at amounts that overlap with the claimed range greater than 0. With such a selection, the first height difference would be greater than about 100 to greater than about 600 angstroms and therefore, greater than the second height difference that would be greater than 0 to about 50 angstroms. It has been held that obviousness exists where the claimed ranges overlap or lie inside ranges disclosed by the prior art. See MPEP 2144.05 (I).
Regarding Claim 4, modified Tu teaches all the limitations of claim 1 as outlined above. Tu further teaches wherein, in step 1, the narrower dummy gate structures and the wider dummy gate structures are formed of polysilicon (Paragraph [0012] the gate electrode layer (element 110) can be polysilicon. Figure 3 the gate electrode layer (element 110) is part of the gate structures (elements 130 and 140)).
Regarding Claim 5, modified Tu teaches all the limitations of claim 1 as outlined above. Tu further teaches wherein, in step 2, a method for polishing the interlayer dielectric layer is a chemical-mechanical polishing method (Paragraph [0019] the polishing process includes a CMP process).
Regarding Claim 8, modified Tu teaches all the limitations of claim 1 as outlined above. Tu further teaches wherein in step 6, after the chemical-mechanical polishing is performed on the aluminum layer, the aluminum layer, the dielectric material, and the silicon nitride layer in the wider trenches form wider metal gates, and wherein the aluminum layer, the dielectric material, and the silicon nitride layer in the narrower trenches form narrower metal gates (Paragraph [0030] gate structures elements 130A, equivalent to narrower metal gates, and elements 140A, equivalent to wider metal gates, are formed and comprise the metal gate electrode portion (element 350), the silicon nitride layer (element 240)).
Regarding Claim 9, modified Tu teaches all the limitations of claim 1 as outlined above.
Tu fails to explicitly teach wherein in step 6, after the chemical-mechanical polishing is performed, heights of the wider metal gates are approximately 361A, and heights of the narrower metal gates are approximately 415A.
However, Tu further teaches that the gate heights after the chemical-mechanical polishing are in the range of about 100 to about 600 angstroms (Paragraph [0030] gate heights 360 and 370 are in the range of about 100 to about 600 angstroms). Tu teaches that the difference in height between the top surface of the aluminum layer in the wider trenches and the height difference between the top surface of the aluminum layer in the narrower trenches can be less than about 50 angstroms (Paragraph [0027] the height difference between the gate height 310, equivalent to the height of the narrower gate structures, and the gate height 320, equivalent to the height of the wider gate structures, is less than about 50 angstroms. Paragraph [0030] the gate heights 360 and 370, after the metal gate electrode layer has been deposited and polished, are only slightly less than the gate heights 310 and 320, with a gate loss amount of 0-200 angstroms).
It would have been obvious to one of ordinary skill in the art to have selected and incorporated a height for the wider metal gates at a level within the disclosed range of about 100 to about 600 angstroms, including at amounts that overlap with the claimed range of approximately 361 angstroms. It would have been obvious to one of ordinary skill in the art to have selected and incorporated a height for the narrower metal gates at a level within the disclosed range of about 100 to about 600 angstroms, including at amounts that overlap with the claimed range of approximately 415 angstroms. Examiner takes the position that there are values for the heights that could be selected such that the teaching of Tu that the height difference is “less than or about 50 angstroms” could be satisfied while also meeting the claimed limitation for the “approximate” heights of the wider and narrower gates. It has been held that obviousness exists where the claimed ranges overlap or lie inside ranges disclosed by the prior art. See MPEP 2144.05 (I).
Claims 2, 3, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Tu in view of Cai and Li, as applied to Claim 1 above, and further in view of Ho et al. (US-20170098581-A1).
Regarding Claim 2, modified Tu teaches all the limitations of claim 1 as outlined above.
Tu fails to explicitly teach wherein the first height difference is approximately 110 angstroms, and the second height difference is approximately 50 angstroms.
However, Tu further teaches that the first height difference can be greater than about 100 angstroms (Paragraphs [0016-0017] Figure 4 gates in the iso region (element 150), equivalent to the "narrower dummy gate structures", have a gate height (element 210) and gates in the dense region (element 160), equivalent to the "wider dummy gate structures", have a gate height (element 220). The gate height 220 is greater than the gate height 210. Paragraph [0019] Figure 6 a polishing process is performed on the interlayer dielectric layer, and at the end of this process the gate heights 220 is still greater than the gate height 210 and the top surface of the wider gate structure further comprises the sacrificial layer (element 250A). Paragraph [0021] the thickness of the sacrificial layer can be about 100 to about 600 angstroms. Therefore, the total height difference equivalent to the claimed first height difference can be greater than about 100 to greater than about 600 angstroms).
It would have been obvious to one of ordinary skill in the art to have selected and incorporated heights for the dummy gate structures, such that the first height difference was at a level within the disclosed range of greater than about 100 to greater than about 600 angstroms, including at amounts that overlap with the claimed range of approximately 110 angstroms. It has been held that obviousness exists where the claimed ranges overlap or lie inside ranges disclosed by the prior art. See MPEP 2144.05 (I).
Tu also teaches that after the chemical-mechanical polishing, the equivalent of claimed “step 6”, the gate heights are in the range of about 100 to about 600 angstroms (Paragraph [0030] gate heights 360 and 370 are in the range of about 100 to about 600 angstroms). Tu teaches that the difference in height between the top surface of the aluminum layer in the wider trenches and the height difference between the top surface of the aluminum layer in the narrower trenches can be less than about 50 angstroms (Paragraph [0027] the height difference between the gate height 310, equivalent to the height of the narrower gate structures, and the gate height 320, equivalent to the height of the wider gate structures, is less than about 50 angstroms. Paragraph [0030] the gate heights 360 and 370, after the metal gate electrode layer has been deposited and polished, are only slightly less than the gate heights 310 and 320, with a gate loss amount of 0-200 angstroms).
It would have been obvious to one of ordinary skill in the art to have selected and incorporated heights for the metal gate structures, such that the second height difference was at a level within the disclosed range of less than about 50 angstroms, including at amounts that overlap with the claimed range of approximately 50 angstroms. It has been held that obviousness exists where the claimed ranges overlap or lie inside ranges disclosed by the prior art. See MPEP 2144.05 (I).
Modified Tu fails to teach wherein, in step 1, a width dimension of the narrower dummy gate structures is less than 200nm, a width dimension of the wider dummy gate structures is more than 200nm.
Ho teaches methods related to forming metal gate structures, that include metal gates with a larger width and metal gates with a smaller width ([Abstract]). Ho teaches that the width of a wider dummy gate structure can be 10-500nm and that the width or a narrower dummy gate structure can be 5-250nm (Paragraph [0022]).
It would have been obvious to one of ordinary skill in the art to have modified the method of modified Tu by using the gate widths taught by Ho for the gate structures formed.
This modification would have been obvious as it would have been the combination of prior art elements according to known methods to yield predictable results. This combination would have had the predictable result of providing suitable gate structure widths for both wider and narrower gate structures. See MPEP 2143(I)(A).
It would have been obvious to one of ordinary skill in the art to have selected and incorporated a width for the narrower dummy gate structures at a level within the disclosed range of 5-250nm, including at amounts that overlap with the claimed range of less than 200nm. It would have been obvious to one of ordinary skill in the art to have selected and incorporated a width for the wider dummy gate structures at a level within the disclosed range of 10-500nm, including at amounts that overlap with the claimed range of more than 200nm. It has been held that obviousness exists where the claimed ranges overlap or lie inside ranges disclosed by the prior art. See MPEP 2144.05 (I).
Regarding Claim 3, modified Tu teaches all the limitations of claims 1 and 2 as outlined above. Tu further teaches wherein, in step 1, a number of the narrower dummy gate structures and a number of the wider dummy gate structures are respectively plurals, wherein the narrower dummy gate structures are spaced apart, the wider dummy gate structures are spaced apart, and wherein the narrower dummy gate structures are arranged at one side of the wider dummy gate structures (Paragraph [0013] Figure 3 a plurality of gate structures are formed, two wider gates and two narrower gates are shown in Figure 3 arranged with the wider gates on the right and narrower gates on the left).
Regarding Claim 6, modified Tu teaches all the limitations of claim 1 as outlined above.
Modified Tu fails to teach wherein, in step 3, a dimension of the wider trenches is more than 200nm; and a dimension of the narrower trenches is less than 200nm; and a dimension of the narrower dummy gate structures is less than 200nm; and a dimension of the wider dummy gate structures is more than 200nm.
Ho teaches methods related to forming metal gate structures, that include metal gates with a larger width and metal gates with a smaller width ([Abstract]). Ho teaches that the width of a wider dummy gate structure can be 10-500nm and that the width or a narrower dummy gate structure can be 5-250nm (Paragraph [0022]).
It would have been obvious to one of ordinary skill in the art to have modified the method of modified Tu by using the gate widths taught by Ho for the gate structures formed. When following the method of modified Tu as outlined with regards to Claim 1, the dummy gates would be removed and resulting in trenches that have the width as the dummy gates. Therefore, the selection of dummy gate widths as outlined above would result in trenches that meet the limitations of claim 6.
This modification would have been obvious as it would have been the combination of prior art elements according to known methods to yield predictable results. This combination would have had the predictable result of providing suitable gate structure widths for both wider and narrower gate structures. See MPEP 2143(I)(A).
It would have been obvious to one of ordinary skill in the art to have selected and incorporated a width for the narrower dummy gate structures at a level within the disclosed range of 5-250nm, including at amounts that overlap with the claimed range of less than 200nm. It would have been obvious to one of ordinary skill in the art to have selected and incorporated a width for the wider dummy gate structures at a level within the disclosed range of 10-500nm, including at amounts that overlap with the claimed range of more than 200nm. It has been held that obviousness exists where the claimed ranges overlap or lie inside ranges disclosed by the prior art. See MPEP 2144.05 (I).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Tu in view of Cai and Li, as applied to Claim 1 above, and further in view of Zhu et al. (US-20150187863-A1).
Regarding Claim 7, modified Tu teaches all the limitations of claim 1 as outlined above. Tu teaches that a high-k dielectric material can be deposited in the trenches (Paragraph [0032]).
Modified Tu fails to teach that wherein, in step 4, the dielectric material comprises tungsten.
Zhu teaches methods related to forming a gate that include the use of gate dielectric layer (Paragraph [0006]). Zhu teaches that tungsten oxide is a high-k dielectric material that is suitable for use in a gate dielectric layer (Paragraph [0018]).
It would have been obvious to one of ordinary skill in the art to have modified the method of modified Tu by selecting as the high-k dielectric material tungsten oxide, as taught by Zhu.
It would be obvious to one of ordinary skill in the art to substitute the unspecified high-k dielectric material taught by Tu with tungsten oxide taught by Zhu since tungsten oxide is a high-k dielectric material known to be suitable for use in gate dielectric layers and the selection of a known material, which is based upon its suitability for the intended use, is within the ambit of one of ordinary skill in the art. See MPEP 2144.07.
Response to Arguments
Applicant’s arguments, see Remarks Pg. 1-7, filed 11/24/2025, with respect to the 35 U.S.C. § 103 rejection have been fully considered and are not persuasive.
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.K.L./ Examiner, Art Unit 1713 /DUY VU N DEO/Primary Examiner, Art Unit 1713
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