Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
OFFICE ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) The claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) The claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Wann (US 2012/0273899)
Regarding claim 1, the prior art discloses:
A method for modeling mandrel tolerance (fig 1-13 are about modeling mandrel tolerance, i.e., mandrel aligned or not aligned, mandrel checked against design rules, variation/adjustment of the mandrels, mandrel minimum spacing violations/rules) in a design of a semiconductor device, the method comprising:
accessing design parameters (two or more of: technology nodes, design rules/spacings, lithography/process techniques/limitations, minimum space/ distance, components (devices) or parameters (par 4, 29, 33, 45, 55, 68, 79, 86-88, 106)) of a plurality of transistors that form at least part of the semiconductor device, the design parameters corresponding to plurality of fins associated with each of the plurality of transistors (see one or more of abstract, par 2-4, fig 1-2, 9-10, 14 for transistor finfet parameters);
generating a fin index (i.e., fin aspect ratio (par 3), fins with different kinds of symmetry / boundaries (par 30, 34, 36), different finfet cells, finfet cell groups, (par 43-44), finfet ratio/beta/type, odd number of fins, fin boundary, fin size/shape/pitch (par 49-51, 53-63, 66-67, 109)) identifying each of the plurality of fins;
grouping the fin indexes of the plurality of fins into two or more groups based on a type of fin (see par 3, 34, 43-44, 55);
responsive to determining that a first fin index associated with a first transistor of the plurality of transistors belongs to a group that is different from a second fin index associated with a second transistor of the plurality of transistors, identifying a mandrel mismatch (see finfet with different kinds, different symmetry and unmatched mandrel/ not match mandrel in par 33-34, 45), non-parallel/ different finfets and misaligned/ not aligned mandrels (par 77-80, 91) ) ; and
determining, by a processing device (see one or more of CAD (par 4), computer/ processor (fig 17), a device parameter (see one or more of area, power, gain, properties, dimension/beta/ratio optimization, new layout in one or more of par 3, 22, 25-26, 32, 45-48, 62, 64, 94, 109-110) based on the identified mandrel mismatch.
(Claim 2) wherein the device parameter comprises one or more of threshold voltage, device gain, device noise, saturation current, subthreshold current, device power, device layout area, velocity saturation, mobility, or any accessible device parameter (see one or more of par 3, 22, 25-26, 32, 45-48, 62, 64, 94, 109-110)
(Claim 3) responsive to determining that the first fin index associated with the first transistor of the plurality of transistors belongs to a same group as the second fin index associated with the second transistor of the plurality of transistors, identifying a mandrel match (par 10, 26, 28, 30-37, 43-44, 63, 77-81, 86); and determining the device parameter based on the identified mandrel match (par 10, 26, 28, 30-37, 43-44, 63, 77-81, 86)
(Claim 4) identifying a partial match if at least one fin index associated with the first transistor of the plurality of transistors belongs to the same group as one or more fin indexes associated with the second transistor of the plurality of transistors (par 30-43, 78-81, fig 3-8).
(Claim 5) determining the type of fin based on a first spacing on one side of the fin and a second spacing on another side of the fin (par 22, 29, 32, 38, 45, 55, 67, 84, 77-78, 85-86, 90, 92)
(Claim 6) wherein the design parameters of the plurality of fins comprises at least a critical dimension (par 65) of the plurality of fins.
(Claim 7) wherein the design parameters are included in a multi-patterning technology (MPT) process design kit (PDK), and the MPT process comprises one or more of self-aligned double patterning (SADP), self-aligned triple patterning (SATP), self-aligned quadruple patterning (SAQP), or litho-etch-litho-etch LELE (par 22-22, 45, 67-68, 106).
Claim 8-20 recite similar subject matter and are rejected for the same reason. For masking layer mismatch, see mask/photomask variation/ unmatched/mis-match/mis-align, finfet boundary, hard mask and design rule violations/unmatched/mis-match (par 4, 22, 29, 33, 45, 105-106)
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL DINH whose telephone number is 571-272-1890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s Supervisor, Jack Chiang can be reached on 571-272-7483. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL DINH/Primary Examiner, Art Unit 2851