Prosecution Insights
Last updated: July 17, 2026
Application No. 18/130,229

PIXEL, DISPLAY DEVICE HAVING THE SAME, AND METHOD OF FABRICATING THE DISPLAY DEVICE

Non-Final OA §102
Filed
Apr 03, 2023
Priority
Apr 04, 2022 — RE 10-2022-0041715
Examiner
CHEN, DAVID Z
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
45%
Grant Probability
Moderate
1-2
OA Rounds
3m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 45% of resolved cases
45%
Career Allowance Rate
306 granted / 685 resolved
-23.3% vs TC avg
Strong +50% interview lift
Without
With
+49.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
49 currently pending
Career history
751
Total Applications
across all art units

Statute-Specific Performance

§103
78.9%
+38.9% vs TC avg
§102
16.6%
-23.4% vs TC avg
§112
3.9%
-36.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 685 resolved cases

Office Action

§102
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Amendment/Restriction Applicant’s election without traverse of Species I, embodiment 1 (Fig. 8), Sub A (Fig. 12A), Sub-sub 1 (Fig. 27), and Claims 1-18 and 20 in the reply filed on February 27, 2026 is acknowledged. Thus, Claim 19 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention. Further, Claim 20 is never present in the Application. Election was made without traverse in the reply filed on February 27, 2026. Specification The title of the invention is broad and not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-6 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2019/0326348 A1 to Im et al. (“Im”). As to claim 1, Im discloses a pixel comprising: a substrate (301) including an emission area (at L) and a non-emission area (outside L); a first conductive pattern (DE2), a second conductive pattern (340, VSL), and a third conductive pattern (SE2) in the non-emission area (outside L) and spaced from each other; a via layer (in 305) on the first to the third conductive patterns (DE2, 340, VSL, SE2), and comprising a first contactor (60) exposing one area of the first conductive pattern (DE2), a second contactor (40) exposing one area of the second conductive pattern (340, VSL), and a third contactor (70) exposing another area of the second conductive pattern (340, VSL); a first alignment electrode (341) and a second alignment electrode (342) on the via layer (in 305), and spaced from each other; a light emitting element (LED) between the first alignment electrode (341) and the second alignment electrode (342); and a first electrode (371) and a second electrode (372) spaced from each other, and electrically connected to the light emitting element (LED), wherein, in at least the non-emission area (outside L), at least one of the first (371) and the second (372) electrodes directly contacts the one area of the first conductive pattern (DE2) through the first contactor (60), and at least one of the first (341) and the second (342) alignment electrodes directly contacts the one area of the second conductive pattern (VSL) through the second contactor (40) (See Fig. 2, Fig. 4, Fig. 5, ¶ 0071, ¶ 0073, ¶ 0074, ¶ 0076, ¶ 0078, ¶ 0079, ¶ 0093, ¶ 0095, ¶ 0099, ¶ 0100, ¶ 0101, ¶ 0103, ¶ 0104, ¶ 0106, ¶ 0109, ¶ 0111, ¶ 0123, ¶ 0129, ¶ 0132, ¶ 0138). As to claim 2, Im discloses further comprising: a passivation layer (304, 305 multiple-layer) between the via layer (in 305) and the first (DE2) and second (340, VSL) conductive patterns; a first insulating layer (306) between the light emitting element (LED) and the first (341) and the second (342) alignment electrodes; a second insulating layer (307/470) on the light emitting element (LED), and exposing first and second ends of the light emitting element (LED); and a third insulating layer (470/307) on the second insulating layer (307/470), wherein the first insulating layer (306) includes a first through hole corresponding to the first contactor (60), and a second through hole corresponding to the third contactor (70) (See Fig. 4, Fig. 5, ¶ 0111, ¶ 0138). As to claim 3, Im further discloses wherein an inclination angle of each of opposite side surfaces of the via layer (in 305) that oppose each other with the first contactor (60) located therebetween is same as an inclination angle of each of opposite side surfaces of the first insulating layer (306) that oppose each other with the first through hole located therebetween, and wherein an inclination angle of each of opposite side surfaces of the via layer (in 305) that oppose each other with the third contactor (70) located therebetween is same as an inclination angle of each of opposite side surfaces of the first insulating layer (306) that oppose each other with the second through hole located therebetween. (See Fig. 4) (Notes: the continuous and uniform contactors provide the same inclination angle). As to claim 4, Im further discloses wherein the passivation layer (304, 305 multiple-layer) includes a first contact hole overlapping the first contactor (60) and exposing the one area of the first conductive pattern (DE2), a second contact hole overlapping the second contactor (40) and exposing the one area of the second conductive pattern (340, VSL), and a third contact hole overlapping the third contactor (70) and exposing the another area of the second conductive pattern (340, VSL), wherein the second insulating layer (307) includes a first opening corresponding to the first contact hole, and a second opening corresponding to the third contact hole, and wherein the third insulating layer (307) includes a first via hole corresponding to the first opening, and a second via hole corresponding to the second opening (See Fig. 4, Fig. 6, ¶ 0104, ¶ 0111) (Notes: the plurality second and third insulating layers may be formed, similar to the multiple-layer structure). As to claim 5, Im further discloses wherein the first electrode (371) directly contacts the one area of the first conductive pattern (DE2) through the first via hole of the third insulating layer (307), the first opening of the second insulating layer (307), the first through hole of the first insulating layer (306), the first contactor (60) of the via layer (in 305), and the first contact hole of the passivation layer (304, 305 multiple-layer), and wherein the second alignment electrode (342) directly contacts the one area of the second conductive pattern (340, VSL) through the second contactor (40) of the via layer (in 305) and the second contact hole of the passivation layer (304, 305 multiple-layer) (See Fig. 4). As to claim 6, Im discloses further comprising: at least one transistor (Tr2) located between the substrate (301) and the passivation layer (304, 305 multiple-layer), and electrically connected to the light emitting element (LED); a capacitor (Cst) between the substrate (301) and the passivation layer (304, 305 multiple-layer), and including a first storage electrode (333) connected to a gate electrode (GE2) of the transistor (Tr2), and a second storage electrode (opposite 333) electrically connected to the light emitting element (LED); a first power line (VDD) between the substrate (301) and the passivation layer (304, 305 multiple-layer), and configured to receive a voltage of a first driving power supply; and a second power line (VSS) spaced from the first power line (VDD), and configured to receive a voltage of a second driving power supply different from the first driving power supply. (See Fig. 2). Allowable Subject Matter Claims 16-18 are allowed. Claims 7-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID CHEN/Primary Examiner, Art Unit 2815
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Prosecution Timeline

Apr 03, 2023
Application Filed
Jun 03, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Patent 12660674
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
45%
Grant Probability
94%
With Interview (+49.8%)
3y 7m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 685 resolved cases by this examiner. Grant probability derived from career allowance rate.

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