DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant election of group I, Claims 1-9, without traverse, is acknowledged. Applicant has cancelled Claims 10-20 and added Claims 21-22. Claims 1-9, 21 and 22 are examined on the merit.
Claim Rejections - 35 USC § 102 / 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 1, 2, 8 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Michimata et al. (US 20050230712), (hereinafter, Michimata) as evidenced by NOBILI et al. ("TITANIUM SILICIDE FORMATION IN PRESENCE OF OXYGEN," Active and Passive Elec. Comp., Vol. 15, pp. 9-26, 1992), (hereinafter, NOBILI) or in the alternative Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Michimata et al. (US 20050230712), (hereinafter, Michimata) in view of NOBILI et al. ("TITANIUM SILICIDE FORMATION IN PRESENCE OF OXYGEN," Active and Passive Elec. Comp., Vol. 15, pp. 9-26, 1992), (hereinafter, NOBILI).
RE Claim 1, Michimata discloses a semiconductor device “MOS transistor” and a method of making the same. Examiner notes that “MOS transistors” and “bipolar transistors” are commonly formed a part of an entire integrated circuit to perform specific functions, hence “an integrated circuit” limitation is implicitly met. Michimata discloses in FIGS. 1-11 an integrated circuit, comprising:
at least one silicon region 11/14 “silicon substrate”, referring to FIGS. 1 and 3; and
at least one metal pillar 20 “tungsten”, as part of the contact plug 21 in contact with said silicon region at an ohmic coupling region 29;
wherein the ohmic coupling region 29 comprises titanium silicide, of C49-crystal structure or C54-crystal structure, which has a lower resistivity than titanium silicide of a C49-crystal structure [0038, 0046-0048], including oxygen atoms in proportions below 10% and silicon atoms in proportions in a range from 60% to 80%. Examiner notes that C49-crystal structure titanium silicide has 50-70 micro-ohm-cm resistivity [0038], while C54-crystal structure titanium silicide has 15-20 micro-ohm-cm resistivity, which are very low resistivity, hence imply ohmic contacts, hence meeting the claimed limitation of ohmic coupling region. Furthermore, the C49-crystal and C54-crystal structures titanium silicide is of titanium disilicide TiSi2 having 66.67% silicon, between 60%-80% of silicon and with no oxygen detection, which is less than 10%, hence is inherently met, as evidenced NOBILI’s disclosure, which discloses a TiS2 annealed at 800oC has RBS “Rutherford Back Scattering” study with a sensitivity of 5% has no oxygen contribution, hence oxygen atoms in proportions below 10%. Therefore, the limitation is inherently met.
However, in applicant prove that the C49-crystal and C54-crystal structures titanium silicide do not posses such oxygen and silicon concentration inherently, it would have been obvious for one of ordinary skill in the art, at the effective filing date of the instant application, to have the titanium silicide layer Michimata discloses of to be annealed under the same annealing conditions, at 800oC, in order to achieve the C54-crystal structures titanium silicide with 66.67% silicon concentration, which lies between 60%-80% of silicon and with no oxygen detection, which is less than 10% referring to the entire NOBILI’s disclosure particularly the highlighted portions, as well-known titanium silicide with well-controlled properties with ohmic characteristics.
RE Claim 2, Michimata discloses an integrated circuit, wherein the ohmic coupling region 29 has a volume defined by a spherical “semispherical” segment, referring to FISG. 1, 3 and 4A .
RE Claim 8, Michimata discloses an integrated circuit, wherein the at least one silicon region 14 is p+ doped silicon [0042] with a dosage of 1015cm2 at a projected range of 15nm [0042], which is equivalent to p dopant concertation of 3.76 × 1020 cm-3 which falls in the claimed range of a concentration of p dopants greater than or equal to 1018 atoms per cubic centimeter, which falls in the claimed range.
RE Claim 21, Michimata discloses an integrated circuit, wherein the ohmic coupling region 29 has a volume defined by a spherical cap, referring to FIGS. 1 and 3 [0039, 0045 and 0059].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 3-7, 9 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Michimata et al. (US 20050230712), (hereinafter, Michimata) in view of NOBILI et al. ("TITANIUM SILICIDE FORMATION IN PRESENCE OF OXYGEN," Active and Passive Elec. Comp., Vol. 15, pp. 9-26, 1992), (hereinafter, NOBILI) and in further view of Lee (US 2021/0250480), (hereinafter, Lee).
RE Claim 3 and 22, Michimata discloses an integrated circuit, wherein the spherical “semispherical” segment 29 has a first base disc with radius, which is inherently met.
However, Michimata does not disclose a base disc with radius in a range of 45 nanometers to 57 nanometers, and a height in a range of 14 nanometers to 26 nanometers.
However, it would have been obvious to one having ordinary skill in the art at the effective filing date the instant application was filed to use the claimed base disc dimensions, absent unexpected results, in order to optimize the ohmic contact value, since it has been held that discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233; In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996).
RE Claim 4, Michimata discloses an integrated circuit, wherein the ohmic coupling region comprises:
a layer of titanium nitride 10; and
a layer of titanium silicide;
wherein a thickest part of the layer of titanium nitride has a thickness of 10nm However, Michimata does not disclose titanium nitride has a thickness between 5 nanometers and 6 nanometers; and
wherein a thickest part of the layer of titanium silicide has a thickness of between 9 nanometers and 20 nanometers.
However, it would have been obvious to one having ordinary skill in the art at the effective filing date the instant application was filed to use the claimed layer thickness dimensions, absent unexpected results, in order to optimize the ohmic contact value, since it has been held that discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233; In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996).
RE Claim 5, Michimata does not disclose an integrated circuit, further including a matrix of photosensitive pixels, wherein the at least one silicon region is located in the matrix of photosensitive pixels.
However, in the same filed of endeavor, Lee discloses in FIG. 2 an integrated image sensor includes a color sensor chip, wherein including a matrix of photosensitive pixels 220 “photoelectric conversion element”, wherein the at least one silicon region 210 is located in the matrix of photosensitive pixels 220 [0040, 0046]. Since the substrate 201 has through-silicon via pad, it is implicit that the substrate 210 is made of silicon, hence meeting the claimed limitation.
Therefore, it would have been obvious for one of ordinary skill in the art at the effective filing date of the instant application, to use a matrix of photosensitive pixels 210 “photodiode” integrated with Michimata disclosed circuitry in order to obtain an integrated controlled image sensor.
RE Claim 6, Michimata does not disclose an integrated circuit, wherein said matrix of photosensitive pixels includes a transistor having a gate region “pixel gate”, and wherein the at least one silicon region is the gate region of the transistor pixel transistor.
However, in the same filed of endeavor, Lee discloses in FIG. 2 an integrated image sensor includes a color sensor chip, wherein said matrix of photosensitive pixels 220 “photoelectric conversion element” includes a transistor having a gate region “pixel gate”, and wherein the at least one silicon region is the gate region of the transistor pixel transistor [0046].
Therefore, it would have been obvious for one of ordinary skill in the art at the effective filing date of the instant application, to use a matrix of photosensitive pixels 220 “photodiode” integrated with Michimata disclosed circuitry in order to obtain an integrated controlled image sensor.
RE Claim 7, Michimata does not disclose an integrated circuit, wherein the transistor comprises one of a transfer transistor or a vertical transistor buried in a substrate.
However, in the same filed of endeavor, Lee discloses in FIG. 2 an integrated image sensor includes a color sensor chip, wherein the transistor comprises one of a transfer transistor or a vertical transistor buried in a substrate [0046].
Therefore, it would have been obvious for one of ordinary skill in the art at the effective filing date of the instant application, to use a matrix of photosensitive pixels 220 “photodiode” with a transfer transistor integrated with Michimata disclosed circuitry in order to obtain an integrated controlled image sensor.
RE Claim 9, Michimata does not disclose an integrated circuit, comprising an assembly in a three-dimensional integration of two superimposed integrated circuit chips.
However, in the same filed of endeavor, Lee discloses in FIG. 2 an integrated image sensor includes a color sensor chip, comprising an assembly in a three-dimensional integration of two superimposed integrated circuit chips 400 “logic chip”, 300 “depth sensor chip” and 200 “color sensor chip.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ajay Ojha can be reached at (571)272-8936. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898