Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
New claim 17 has been added. Currently, claims 1-17 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 3-5, 7, 9, 10 and 12 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of copending Application No. 18/118243 in view of Lei et al. (CN 111769160 A, herein Lei, English translation attached). Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding claims 1 and 12, claims 1 and 10 of the Application No. 18/118243 say “a method of making a semiconductor device, the method comprising: a) etching a substrate to form a trench in the substrate; b) filling the trench with an insulating material layer, wherein a top surface of the insulating material layer is higher than a top surface of the trench; c) etching the insulating material layer to form a side groove between the insulating material layer and a top side wall of the trench to expose a corner at a top of the trench; and d) forming a field oxide layer on a top surface of the substrate by an oxidation process, wherein the corner at the top of the trench is correspondingly oxidized to form into a round corner by the oxidation process, wherein after the forming of the field oxide layer, the side groove is fully filled due to an increase of a volume of the field oxide layer, and the substrate at the corner of the top of the trench is oxidized to form a round corner” and claim 14 of the Application No. 18/118243 say “a semiconductor structure formed by the method of claim 1”.
Application No. 18/118243 does not specifically say fully covering the insulating material in the trench.
However, in the same field of endeavor, Lei teaches forming a field oxide layer 23 on a portion of the upper surface of the substrate 20 and the insulating material 22 (Lei: paragraphs [0065]-[0067] and Figs. 2-4), wherein the field oxide layer covers one of the sharp corners and fully covers the insulating material in the trench, which improves the breakdown voltage of the semiconductor device without increasing the on-resistance (Lei: “Specific Implementation Examples” and Figs. 2-4).
Therefore, given the teachings of Lei, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Application No. 18/118243 in view of Lei by employing the field oxide layer fully covering the top surface of the STI region.
Claims 2, 3, 5, 9, 11, 13 of the Application No. 18/118243 disclose the limitations of the claims 3, 4, 5, 7, 10, 9 of the current application respectively.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
The claims of copending application 18/080870 are similar to the claims of the current application. The applicant is advised to exercise caution to prevent any potential double-patenting issues.
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Tung (Pat. No. US 6,376,296 B2) in view of Lei et al. (CN 111769160 A, herein Lei).
Regarding claim 12, Tung discloses a semiconductor device, comprising: a) a semiconductor substrate 200 having a trench 215 therein; b) an insulating material filled 216 in the trench; c) a field oxide layer 212 formed on a portion of an upper surface of the substrate and the insulating material, wherein a junction between sidewalls of the trench and the upper surface of the substrate is rounded (Tung: Figs. 2A-2D and column 3, line 67 to column 4, line 33).
Tung does not specifically say fully covering the insulating material in the trench.
However, in the same field of endeavor, Lei teaches forming a field oxide layer 23 on a portion of the upper surface of the substrate 20 and the insulating material 22 (Lei: paragraphs [0065]-[0067] and Figs. 2-4), wherein the field oxide layer covers one of the sharp corners and fully covers the insulating material in the trench, which improves the breakdown voltage of the semiconductor device without increasing the on-resistance (Lei: “Specific Implementation Examples” and Figs. 2-4).
Therefore, given the teachings of Lei, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Tung in view of Lei by employing the field oxide layer fully covering the top surface of the STI region.
Regarding claim 13, Tung in view of Lei teaches the semiconductor device of claim 12, further comprising: a) 218a/202a/220a/204b and a drift region 204a/202b located in the substrate; b) a source region 224a/226a located in the body region; c) a drain region 224b/226b located in the drift region; and d) wherein the trench is located in the drift region, and the drain region and the source region are located at opposite sides of the trench (Tung: Figs. 2A-2D and column 4, line 34 to column 4, line 63).
Regarding claims 14 and 15, Tung in view of Lei teaches the semiconductor device of claim 12, wherein a thickness of the field oxide layer is between 300 Å and 1000 Å (Lei: paragraph [0076], Figs. 2-4 and Tung: Figs. 2A-2D). The claimed thickness range is recognized as a result-effective variable, i.e., a variable which achieves a recognized result. A thick oxide stops parasitic conduction between neighboring devices, if it is too thin; leakage currents or punch-through can occur. The thicker the oxide over the field region, the weaker the coupling between the gate and the substrate underneath which causes higher threshold to invert that area and prevents unwanted channels. Too thin oxides don’t provide enough isolation. Therefore, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose the particular claimed thickness range because applicant has not disclosed that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another range. The claim(s) is(are) obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. See In re Aller, 105 USPQ 233 (CCPA 1955) and In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Regarding claim 16, Tung in view of Lei teaches the semiconductor device of claim 13, further comprising a gate structure having a gate oxide layer 214c/214d and a conductor layer 222a/222b, wherein the gate oxide layer extends on a substrate surface between the source region and the field oxide layer, and the conductor layer extends on the gate oxide layer and a portion of the field oxide layer (Tung: Figs. 2A-2D and column 4, lines 57-66).
Claims 1-11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (Pub. No. US 2007/0235835 A1, herein Ko) in view of Tung (Pat. No. US 6,376,296 B2), and further in view of Lei et al. (CN 111769160 A, herein Lei).
Regarding claim 1, Ko discloses a method of making a semiconductor device, the method comprising: a) providing a semiconductor substrate 318 (Ko: paragraph [0018]); b) etching the substrate to form a trench 310 therein (Ko: Figs. 1A-1C and paragraph [0020]); c) filling the trench with an insulating material 312/STI, wherein a top surface of the insulating material is higher than a top surface of the trench (Ko: Figs. 1D-2A and paragraph [0021]); d) etching the insulating material to expose sharp corners 372 at a junction of sidewalls of the trench and an upper surface of the substrate (Ko: Figs. 2B-3 and paragraphs [0024]-[0026]).
Ko does not specifically show e) forming a field oxide layer on a portion of the upper surface of the substrate and the insulating material, wherein the field oxide layer covers one of the sharp corners and fully covers the insulating material in the trench; and f) oxidizing correspondingly the sharp corner covered by the field oxide layer, at the junction of the trench sidewalls and the upper surface of the substrate, in order to form into a round corner.
However, in the same field of endeavor, Tung teaches a method of manufacturing a high voltage device, comprising: e) forming a field oxide layer 212 on a portion of the upper surface of the substrate 200 (Tung: Figs. 2A-2D and column 3, line 67 to column 4, line 17) and the insulating material 216, wherein the field oxide layer covers one of the sharp corners; and f) oxidizing correspondingly the sharp corner covered by the field oxide layer, at the junction of the trench sidewalls and the upper surface of the substrate, in order to form into a round corner (Tung: Figs. 2A-2D and column 4, lines 18-33) to increase the breakdown voltage and to enhance the current-driving performance (Tung: column 1 lines 53-63).
Therefore, given the teachings of Tung, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying in view of Tung by employing the insulating features.
The previous combination does not specifically show wherein the field oxide layer fully covers the insulating material in the trench.
However, Lei teaches forming a field oxide layer 23 on a portion of the upper surface of the substrate 20 and the insulating material 22 (Lei: paragraphs [0065]-[0067] and Figs. 2-4), wherein the field oxide layer covers one of the sharp corners and fully covers the insulating material in the trench, which improves the breakdown voltage of the semiconductor device without increasing the on-resistance (Lei: Specific Implementation Examples and Figs. 2-4).
Therefore, given the teachings of Lei, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying the previous combination in view of Lei by employing the field oxide layer fully covering the top surface of the STI region.
Regarding claim 2, Ko in view of Tung and further in view of Lei teaches the method of claim 1, wherein the forming the field oxide layer comprises using a local oxidation of silicon method (Tung: Figs. 2A-2D and column 3, line 67 to column 4, line 17).
Regarding claim 3, Ko in view of Tung and further in view of Lei teaches the method of claim 1, wherein during the etching the insulating material to expose the sharp corners at the junction of the trench sidewalls and the upper surface of the substrate, the insulating material is back etched using wet etching process (Ko: Figs. 2B-3 and paragraph [0026]).
Regarding claim 4, Ko in view of Tung and further in view of Lei teaches the method of claim 3, wherein a solution of the wet etching process comprises hydrofluoric acid, buffered oxide etching solution (BOE), or hydrofluoric acid with different ratios (Ko: Figs. 2B-3 and paragraph [0026]).
Regarding claim 5, it is well-known in the art that higher concentration of the etchant generally means more reactive ions or molecules are available which increases the etch rate, if the solution is too concentrated, side effects such as roughness or undercutting can occur. It is further known in the art that longer immersion, means deeper etch as the chemistry keeps working. Therefore, Ko in view of Tung teaches a rate of the wet etching process is changed by changing the etching time or concentration of the solution for wet etching to control the exposure of the sharp corner at the junction of the trench sidewalls and the upper surface of the substrate (Ko: Figs. 2B-3 and paragraph [0026]).
Regarding claim 6, Ko in view of Tung and further in view of Lei teaches the method of claim 1, wherein between the etching the insulating material and the forming the field oxide layer on the insulating material, further comprising: a) forming a body region 218a/202a/220a/204b and a drift region 204a/202b in the semiconductor substrate using an ion implantation process (Tung: Figs. 2A-2D and column 4, lines 34-45); b) forming a source region 224a/226a in the body region and a drain region 224b/226b in the drift region; and c) wherein the trench is located in the drift region, and the drain region and the source region are located at opposite sides of the trench (Tung: Figs. 2A-2D and column 5, lines 9-26).
Regarding claims 7-8, Ko in view of Tung and further in view of Lei teaches the method of claim 2, wherein the forming the field oxide layer by the oxidation process comprises using a high-pressure field oxide furnace tube, and a thickness of the field oxide layer is between 300 Å and 1000 Å (Lei: paragraph [0076], Figs. 2-4 and Tung: Figs. 2A-2D). The claimed thickness range is recognized as a result-effective variable, i.e., a variable which achieves a recognized result. A thick oxide stops parasitic conduction between neighboring devices, if it is too thin; leakage currents or punch-through can occur. The thicker the oxide over the field region, the weaker the coupling between the gate and the substrate underneath which causes higher threshold to invert that area and prevents unwanted channels. Too thin oxides don’t provide enough isolation. Therefore, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose the particular claimed thickness range because applicant has not disclosed that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another range. The claim(s) is(are) obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. See In re Aller, 105 USPQ 233 (CCPA 1955) and In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Regarding claim 9, Ko in view of Tung and further in view of Lei teaches the method of claim 1, wherein the insulating material 312(Ko) / 216(Tung) comprises silicon dioxide, and the field oxide layer comprises silicon dioxide (Ko: paragraph [0021], and Tung: Figs. 2A-2D and column 3, line 67 to column 4, line 33).
Regarding claim 10, Ko in view of Tung and further in view of Lei teaches the method of claim 1, wherein after the forming the field oxide layer on the insulating material, further comprising forming a gate structure 222a on the surface of the field oxide layer and a portion surface of the substrate (Tung: Figs. 2A-2D and column 4, lines 57-66).
Regarding claim 11, Ko in view of Tung and further in view of Lei teaches the method of claim 10, wherein the forming the gate structure on the surface of the field oxide layer and a portion surface of the substrate comprises: a) depositing a gate oxide layer 214c on the surface of the substrate; b) depositing a conductive layer 222 on the surface of the field oxide layer and the gate oxide layer; c) etching the gate oxide layer and the conductor layer through a patterned mask; and d) wherein the gate oxide layer extends on the substrate surface between the source region and the field oxide layer, and the conductor layer extends on the gate oxide layer and a portion of the field oxide layer (Tung: Figs. 2A-2D and column 4, lines 57-66).
Regarding claim 17, Ko in view of Tung and further in view of Lei teaches the method of claim 1, wherein the top surface of the insulating material remains higher than the top surface of the trench after etching the insulating material (Ko: paragraph [0021], and Tung: Figs. 2A-2D and column 3, line 67 to column 4, line 33). In Figs. 2B-2D of Tung, it is seen that the top surface of the insulating material 216 is slightly above the top surface of the substrate, which is an indication of the top surface of the insulating material remaining higher than the top surface of the trench after etching the insulating material. In Ko, having the top surface of the insulating material 340 above the top surface of the trench after etching the insulating material does not appear to interfere with the purpose of the invention as the top surface of the insulating material is already above the locations 372.
Response to Arguments
Applicant’s arguments with respect to claims 1-17 have been fully considered, but are found to be moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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March 2, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813