DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-7) in the reply filed on August 15th, 2025 is acknowledged. Non-elected claims 8-10 have been withdrawn by the Applicant as being drawn to non-elected invention.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Method for manufacturing a 2.5D/3D electronic packaging structure by embedding a wafer into a cavity of a glass substrate.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the organic substrate" in line 16. There is insufficient antecedent basis for this limitation in the claim. Clarification and correction are respectfully requested. Claims 2-7 depend directly on base claim 1 and inherit the deficiencies.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, and 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (U.S. Pub. 2021/0074645) in view of Okamoto et al. (U.S. Pub. 2020/0098592).
In re claim 1, Tsai discloses a method for manufacturing a 2.5D/3D electronic packaging structure 100 (as shown in fig. 1), comprising: disposing a metal array over a wafer 20 (see paragraph [0023] and fig. 1, note that metallization made-up the interconnection bridge 20 constitutes the metal array), fixing a first die 21 and a second die 22 to the metal array, wherein a bottom surface of the first die 21 and a bottom surface of the second die 22 face the wafer 20 respectively (see paragraph [0023] and fig. 1, note that the interconnection bridge 20 is used for interconnection between the first die 21 and the second die 22 and is pre-made); removing a portion of the wafer to partially expose the bottom surfaces of the first die 21 and the second die 22 (see paragraph [0023] and fig. 1, note that part of each of the first die 21 and the second die 22 offsetting from the interconnection bridge 20 and thus having its bottom surface partially exposed due to removal of portions of the wafer); forming a cavity on a surface of a substrate 13 (see paragraph [0022] and fig. 1, note that, the molding layer 13 constitutes a substrate and includes a cavity for adapting the interconnection bridge 20); forming vias (11,12) in the substrate 13, wherein the vias (11,12) extend through the substrate 13 (see paragraph [0024] and fig. 1), and filling the vias with metal materials (i.e., copper) to form metal pillars (11,12) (see paragraph [0026] and fig. 1); forming first solder pads, wherein each of first solder pads is disposed at a first end of one of the metal pillars (11,12) (see paragraph [0024], note that solder pads in the first redistribution layer 30 electrically connected to second contacts 212 and fourth contacts 224, respectively), and forming second solder pads 41, wherein each of second solder pads 41 is disposed at a second end of said metal pillars (11,12) (see paragraph [0025] and fig. 1); and embedding the wafer 20 into the cavity (see paragraph [0022] and fig. 1), connecting the first solder pads of the metal pillars (11,12) to the first die 21 and the second die 22 respectively (see paragraph [0024] and fig. 1), and connecting the second solder pads 41 to a surface of the substrate 50 (see paragraphs [0022], [0024], [0025], [0026] and fig. 1).
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Tsai is silent to wherein the substrate in which a cavity is formed is a glass substrate and the substrate in which the second solder pads are connected to is an organic substrate.
However, Okamoto discloses in a same field of endeavor, a method for manufacturing a 2.5D/3D electronic packaging structure, including, inter-alia, a support substrate may be formed of glass, semiconductor, or ceramic, as long as it provides adequate rigidity and stability and preferably the substrate being glass for its transparency and thermal expansion coefficient (CTE) of approximately between 3 to 12 ppm/ °C (see paragraph [0084]) closer to that of organic material used to build the interconnection layer in order to avoid problem of mechanical stress due to CTE mismatch between the organic substrate and the silicon bridge interconnect assembly which negatively impacts on interconnection reliability and production yield (see paragraph [0004]). Okamoto further discloses wherein an organic base substrate 110 in which solder pads (112-1,118-1) are connected thereto can be used (see paragraphs [0070], [0073] and figs. 1A-B).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Okamoto into the method for manufacturing the 2.5D/3D electronic packaging structure of Tsai in order to enable the substrate in which the cavity is formed therein to be a glass substrate and the substrate in which the second solder pads are connected thereto to be an organic substrate in Tsai to be performed in order to avoid the problem of mechanical stress due to CTE mismatch between the organic substrate and the silicon bridge interconnect assembly which resulting in negative impacts on interconnection reliability and production yield of the electronic packaging structure (see paragraph [0004] of Okamoto). Further, when the substrate is a glass substrate and being transparent, UV or IR light can be irradiated to a release layer on from the back side of the substrate (see paragraph [0085] of Okamoto). Additionally, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
In re claim 3, as applied to claim 1 above, Tsai is silent to wherein the glass substrate has a coefficient of thermal expansion in a range of 3 ppm/° C. to 4 ppm/° C. or in a range of 6 ppm/° C. to 9 ppm/° C.
However, Okamoto discloses in a same field of endeavor, a method for manufacturing a 2.5D/3D electronic packaging structure, including, inter-alia, wherein the glass substrate has a coefficient of thermal expansion (CTE) in a range of approximately 3 to 12 ppm/° C (see paragraph [0084]) in order to avoid problem of mechanical stress due to CTE mismatch between the organic substrate and the silicon bridge interconnect assembly which negatively impacts on interconnection reliability and production yield (see paragraph [0004]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Okamoto into the method for manufacturing the 2.5D/3D electronic packaging structure of Tsai in order to enable wherein the glass substrate has a coefficient of thermal expansion in a range of 3 ppm/° C. to 4 ppm/° C. or in a range of 6 ppm/° C. to 9 ppm/° C in Tsai to be performed in order to avoid problem of mechanical stress due to CTE mismatch between the organic substrate and the silicon bridge interconnect assembly which negatively impacts on interconnection reliability and production yield (see paragraph [0004] of Okamoto). Additionally, it is respectfully submitted that there is no evidence indicating the CTE ranges for the glass substrate is critical and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); In re Aller, 220 F.2d 454, 456, 105 USPQ 233,235 (CCPA 1955).
In re claim 5, as applied to claim 1 above, Tsai in combination with Okamoto discloses wherein a material of the metal pillars comprises copper, and wherein a material of the metal array comprises copper or tungsten (see paragraphs [0008], [0026] of Tsai). Additionally, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. It would have been obvious to one of ordinary skill in the art to use copper or tungsten for the metal array due to its good conductivity and resistance to mechanical wear.
In re claim 6, as applied to claim 1 above, Tsai in combination with Okamoto disclose wherein the first solder pads are connected to the first die and the second die using a micro-bump reflow process and a thermal compression bonding (TCB) process (see paragraph [0130] of Okamoto).
In re claim 7, as applied to claim 1 above, Tsai in combination with Okamoto discloses wherein the second solder pads are connected to the organic substrate using a micro-bump reflow process and a TCB process (see paragraph [0130] of Okamoto).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (U.S. Pub. 2021/0074645) in view of Okamoto et al. (U.S. Pub. 2020/0098592), as applied to claim 1 above, and further in view of Hou et al. (U.S. Pub. 2021/0043571).
In re claim 2, as applied to claim 1 above, Tsai and Okamoto disclose wherein the metal array comprises a line width or spacing equal to or less than 1 micron (see paragraph [0023] of Tsai) but are silent to wherein the first die and the second die are fixed to the metal array by fusion bonding or by hybrid bonding.
However, Hou discloses in a same field of endeavor, a method for manufacturing a 2.5D/3D electronic packaging structure, including, inter-alia, wherein the first die 200 and the second die 300 are fixed to the metal array (located in the bridge component 403) by fusion bonding or by hybrid bonding (see paragraph [0074] and fig. 5).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Hou into the method for manufacturing a 2.5D/3D electronic packaging structure of Tsai in order to enable wherein the first die and the second die are fixed to the metal array by fusion bonding or by hybrid bonding in Tsai to be performed because in doing so would increase interconnect density, enabling finer pitches, shorter interconnects for lower power/faster signals, and better thermal performance.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (U.S. Pub. 2021/0074645) in view of Okamoto et al. (U.S. Pub. 2020/0098592), as applied to claim 1 above, and further in view of Knickerbocker et al. (U.S. Pub. 2018/0005982).
In re claim 4, as applied to claim 1 above, Tsai in combination with Okamoto discloses wherein the vias are through-glass-vias (TGVs) (see paragraph [0024] and fig. 1 of Tsai) but is silent to wherein the TGVs are formed using a laser-assisted dry etching process.
However, Knickerbocker discloses in a same field of endeavor, a method for manufacturing a 2.5D/3D electronic packaging structure, including, inter-alia, wherein the TGVs 1901 are formed using a laser-assisted dry etching process (see paragraph [0107] and fig. 19).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Knickerbocker into the method for manufacturing a 2.5D/3D electronic packaging structure of Tsai in order to enable wherein the TGVs are formed using a laser-assisted dry etching process in Tsai to be performed because it is well-known in the art to use a laser-assisted dry etching process to form the TGVs because of its highly controllable, anisotropic etching, creating sharp features for microelectronics.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Elsherbini et al. U.S. Pub. 2022/0406751 December 22, 2022.
Manusharow et al. U.S. Pub. 2022/0115326 April 14, 2022.
Han et al. U.S. Pub. 2021/0366860 November 25, 2021.
Jain et al. U.S. Pub. 2018/0286812 October 4, 2018.
Olson et al. U.S. Pub. 2022/0238445 July 28, 2022.
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892