DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 18-20 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/5/26.
Response to Arguments
Applicant's arguments filed 6/12/26 have been fully considered but they are not persuasive.
Applicant argues the combination of cited references fails because their intermediate surfaces are not used for connecting the semiconductor die.
In response, claim 11 recites the first lower surface is “for electrically connecting to a semiconductor die.” If applicant intends actual electrical connection to the semiconductor die to distinguish over the cited references, the claim should positively recited the die and the connection. Otherwise, the remarks are arguing a narrower invention than the claim actually requires.
Further, the claim language is indefinite as to what exactly does “for electrically connecting to a semiconductor die” require. The interpretation of claim 11 must be resolved before giving weight to applicant’s argument.
Applicant argues the cited references teach wirings extending entirely above the elevation of the upper surface of the lead.
In response, again the argument is based on an overly restrictive reading of the terminology “wiring extends between.” Claim 12 does not appear to require the entire wiring to be between two elevations. A wire can have one portion above the upper surface elevation while another portion extends into the region between the claimed elevations. Applicant’s observation that the cited prior art bonding wire arches above the lead’s upper surface does not, by itself, establish that the references lack a wiring that “extends between” the two claimed elevations.
In Fig. 1B of Nguyen, wire 122 arches upward, but terminates at the lead / bonding region 118. Thus, geometrically, the wire does not exist exclusively at its maximum arch elevation. It necessarily descends toward its termination. The same analysis applies to wires 111 of Shibuya.
Claim 12 does not recite that the wiring is “entirely disposed” or “confined” between the first and second elevations. Rather, claim 12 merely recites that “the wiring extends between” the respective elevations. Accordingly, applicant’s argument appears to rely upon a narrower interpretation than is expressly required by the claim.
Further, the claim language is indefinite as to what exactly does “extends between…an elevation…and…an elevation” require. The interpretation of claim 12 must be resolved before giving weight to applicant’s argument.
Drawings
The drawings are objected to because the first lower surface of first lead 12 should be labeled 12a2 and the second lower surface of first lead 12 should be labeled 12a3 for consistency. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the features of claim 30 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
the first lower surface of first lead 12 should be labeled 12a2 and the second lower surface of first lead 12 should be labeled 12a3 for consistency.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-33 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the order and arrangement among the encapsulant, conductive structure, lead surfaces, and semiconductor die.
The order listed in claim 11 is confusing because paragraph [0024] of the application as published reads: “[t]he carrier 10, the leads 12, and the tie bars 14 (connecting element) may be collectively referred as a conductive structure.” The claim recites an encapsulant, a conductive structure comprising a carrier, a connecting element, and a first lead, encapsulated by the encapsulant.
Then, the claim later recites, a first upper surface of the connecting element, a first upper surface of the first lead, and a second lower surface of the first lead are all exposed from the encapsulant. This is a contradiction since the entire conductive structure is encapsulated. If the encapsulant was recited after the conductive structure, then the portions that are exposed would be clear. For example, a conductive structure, a carrier, a connecting element, a first lead, wherein the elements are encapsulated and certain areas are exposed.
It is also unclear as to which surface of the encapsulant the first upper surface of the connecting element is exposed from. There is no association or spatial relationship of the upper surface of the connecting element to one of the encapsulant surfaces.
Further, the semiconductor die is part of the electronic device and should be positively recited rather than using the terminology “for electrically connecting to a semiconductor die”. This is an intended use / capability of the surface without requiring the electronic device to actually include a semiconductor die. The claim should recite --electrically connected to a semiconductor die--. The meanings of “for electrically connecting” versus “electrically connected” are not equivalent. If the argument depends upon the prior art intermediate surface not actually being connected to its die, applicant should arguably claim the actual cooperative relationship being relied upon. Otherwise, the claim merely requires the surface to be structurally capable of such a connection.
Furthermore, subsequent limitations require comparing locations of two surfaces relative to the semiconductor die. This is an antecedent / structural clarity issue since the claim defines the geometry of the first lead in reference to an object that has not clearly been positively included in the claimed electronic device.
The terminology “farther away” compounds the issues because the distance being measured cannot be determined. Since the semiconductor die is not positively recited it is difficult to determine which direction is “farther away”. A semiconductor die is three-dimensional so “farther away” could refer to a minimum distance to the die, distance to a lateral surface, distance to the die center, distance in the first direction, horizontal / lateral separation, Euclidean distance, or some other spatial relationship.
Another issue is the terminology “along a first direction perpendicular to the upper surface”. If that direction is intended to govern the “farther away” comparison, the claim should recite this. If “farther away” instead means lateral distance toward / away from the die, that should likewise be stated. Given how heavily the claim depends on this geometry, clarification is warranted.
In claim 12, the limitations do not make it clear whether the entire wiring must lie withing the elevation interval; only a portion must occupy it; the wiring must extend from one elevation to the other; or merely cross one or both elevations.
In claim 13, it is not clear what is meant by entirely overlap. There are at least two plausible readings: A. when viewed along the second direction, the entire wiring overlaps the first lead; or B. the wiring extends over the first lead along its entire dimension in that direction.
In claim 14, the larger issue remains inherited from claim 11 regarding the positive recitation of the semiconductor die and from claim 12 regarding the recitation of the elevations.
In claim 15, it is unclear as to how the two quantities are measured. Which direction? Minimum distance? perpendicular distance? Distance along the first direction? Distance between corresponding points?
In claim 16, an edge and surface do not ordinarily “overlap” within defining projection. If the bottom surface is not planar, the relationship is uncertain regarding “same elevation”.
In claim 17, “are intersected” is unclear because it is passive language without identifying what intersects the edges. Non-parallel edges do not necessarily intersect in a three-dimensional structure. Two finite edges can be non-parallel yet terminate before meeting.
In claim 21, positive and negative slope only exist relative to a coordinate system / reference direction. “Opposite signs” is indefinite because rotating / reversing the coordinate orientation changes the sign. The term “substantially” is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear whether “substantially a same” means the same.
Claim 22 inherits the later surfaces indefiniteness of claim 21.
In claim 23, it is unclear what structural configuration constitutes the “forked shape structure” and what relationship is required by the structure being “at” the bottom surface of the connecting element. Because the forked shape structure may extend over a range of elevations, the claim does not identify which surface, edge, point, or portion of the forked shape structure defines the elevation that is compared with the elevation of the first edge.
In claim 24, it is unclear how the recited depths and widths of the first and second recesses are to be determined. In particular, the claim does not clearly identify the surfaces, edges, or points from which the respective depths are measured or the boundaries between which the respective widths are measured.
In claim 25, it is unclear how the recited first depth of the first recess and the height of the carrier are to be determined and compared. The claim does not clearly specify the surfaces, edges, or points defining the beginning and end of the first depth or clearly establish that the height of the carrier is measured along the same first direction. It is also unclear as to which cross-sectional plane in which the separation is require.
In claim 26, it is unclear how the recited second depth of the second recess is to be determined and compared with the first depth. The claim does not clearly establish the surfaces, edges, or points defining the second depth or whether the second depth is measured along the same first direction and according to the same measurement criteria as the first depth. It is also unclear as to which cross-sectional plane in which the separation is require. The claim should be clarified to expressly identify the structural element to which the second portion belongs particularly because a “third portion” is introduced.
In claim 27, the term “substantially” is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear whether “substantially aligned” means coplanar or flush.
In claim 28, the terminology “disposed over” fails to clearly define the required structural relationship between the solder bumps and the corresponding surfaces of the first lead. It is unclear as to whether the terminology requires the solder bump to be in direct physical contact with the first lead.
In claim 29, it is unclear what structural relationship is required by the term “covering.” The claim does not specify whether the protective layer is required to be in direct physical contact with the first upper surface of the first lead and the top surface of the carrier. It is unclear whether the protective layer is distinct from the encapsulant.
In claim 30, it is unclear what structural relationship is required by “an interface is between…” The claim does not specify whether the protective layer and the encapsulant are in direct contact. Further, the claim does not identify the location or extent of the interface relative to the first lead, carrier, or other structures.
In claim 31, which leads are included in the “first number” is unclear. The term “surrounding” does not specify whether the first number includes all leads, only leads around the entire perimeter of the carrier, or only leads associated with the first and second wirings. The claim does not establish the manner in which the first and second wirings are to be counted. To the extent claim 11 does not positively recite the semiconductor die, the structural relationship of the first wirings to the semiconductor die is unclear.
In claim 32, it is unclear as to the degree of deviation from coplanarity is encompassed by the term “substantially coplanar”. The claim fails to clearly identify which lateral surface of the encapsulant provides the reference plane.
In claim 33, the terms “horizontal portion” and “vertical portion” fail to define the orientation of the respective portions with reasonable certainty because the claim does not identify a reference plane, axis, or direction relation to which the portions are horizontal and vertical. the term “adjacent” does not clearly establish the required structural relationship or spacing between the horizontal portion and the semiconductor die. It is unclear which respective surface of the horizontal and vertical portions constitute the first and second lower surfaces. The phrase “a recess connected between” fails to clearly define the structural relationship of the recess to the two recited surfaces. Since an electrical connection is not positively recited in claim 11, the antecedent and structural relationship of the semiconductor die is unclear.
The other claims are rejected as being dependent on claim 11.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 11-15, 27, 28, 32, 33 is/are, to the extent taught and understood, rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2024/0105537 (Shibuya) in view of U.S. Patent Application Publication No. 2024/0055331 (Nguyen) and U.S. Patent Application Publication No. 2003/0197290 (Crowley).
Shibuya discloses (Fig. 1A)
11. (Currently Amended) An electronic device, comprising:
an encapsulant 108; and
a conductive structure encapsulated by the encapsulant and comprising:
a carrier 109;
a connecting element 112 supporting the carrier 109 and having a first upper surface 113 exposed from the encapsulant 108; and
a first lead 107 spaced apart from the connecting element 112 and having a first upper surface (unlabeled) exposed from a first surface of the encapsulant 108.
Shibuya fails to disclose
wherein an area of the first upper surface of the connecting element is less than an area of the first upper surface of the first lead,
wherein the first lead has a first lower surface opposite to the first upper surface for electrically connecting to a semiconductor die, the first lower surface located inside the encapsulant,
wherein the first lead further has a second lower surface opposite to the first upper surface and farther away from the semiconductor die than the first lower surface is, the second lower surface being exposed from a second surface of the encapsulant opposite to the first surface, and
wherein the first lower surface is located between the first upper surface and the second lower surface along a first direction perpendicular to the first upper surface.
Nguyen teaches (Fig. 5)
An electronic device:
wherein an area of the first upper surface of the connecting element 214 is less than an area of the first upper surface of the first lead 218.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide an area of the first upper surface of the connecting element less than an area of the first upper surface of the first lead in Shibuya. The motivation would be so that short circuits between the connecting element and the first lead are reduced as taught by Nguyen (column 6, lines 1-21).
Crowley teaches
An electronic device comprising:
wherein the first lead 54 has a first lower surface 59 opposite to the first upper surface 61 for electrically connecting to a semiconductor die 52, the first lower surface 59 located inside the encapsulant 55,
wherein the first lead 54 further has a second lower surface 57 opposite to the first upper surface 59 and farther away from the semiconductor die 52 than the first lower surface 59 is, the second lower surface 57 being exposed from a second surface of the encapsulant 55 opposite to the first surface, and
wherein the first lower surface 59 is located between the first upper surface 59 and the second lower surface 57 along a first direction perpendicular to the first upper surface 59.
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a first lead having a first lower surface, a first upper surface, and a second lower surface exposed in the modified device of Shibuya. The motivation would be for electrical connection on both sides of the package, for stickability, spacing, internal and external connection, and to dissipate heat as taught by Crowley ([0005], [0033], [0037], [0050]).
Crowley teaches
12. (Currently Amended) The electronic device of claim 11, further comprising a wiring 53 connecting the first lower surface 59 of the first lead, 54 wherein the wiring 53 extends between a first elevation of the first upper surface 59 of the first lead 54 and a second elevation of the second lower surface 57 of the first lead 54.
Crowley teaches
13. (Currently Amended) The electronic device of claim 12, wherein the wiring 53 entirely overlaps the first lead 54 in a second direction perpendicular to the first direction.
Nguyen teaches
14. (Currently Amended) The electronic device of claim 11, wherein the wiring 53 has an end connecting the semiconductor die 52 and located between the first elevation and the second elevation.
Crowley teaches
15. (Currently Amended) The electronic device of claim 11, wherein a height of the first lead 53 is greater than a distance between a top surface of the carrier 51 and a first surface of the semiconductor die 52 for electrical connection.
Nguyen teaches (Fig. 1B)
27. (Currently Amended) The electronic device of claim 11, wherein the first upper surface of the first lead 116 is substantially aligned with the first surface of the encapsulant 106, and wherein the first lead 116 has a lateral surface substantially aligned with a lateral surface of the encapsulant 106.
Crowley teaches
28. (Currently Amended) The electronic device of claim 11, further comprising a first solder bump 61 / 89 disposed over the first upper surface of the first lead 54 and a second solder bump 60 / 89 disposed over the second lower surface of the first lead 54.
Crowley teaches
32. (New) The electronic device of claim 11, wherein the first upper surface 61 of the first lead 64 is substantially coplanar with the first surface of the encapsulant 55, the second lower surface 57 of the first lead 54 is substantially coplanar with the second surface of the encapsulant 55, and the first lead 54 further has a lateral surface 58 connected to the second lower surface 57 and substantially coplanar with a lateral surface of the encapsulant 55.
Crowley teaches
33. (New) The electronic device of claim 11,
wherein the first lead 54 comprises a horizontal portion adjacent to a lateral surface of the semiconductor die 52 and a vertical portion 58 connected to the horizontal portion 59,
wherein the first lower surface 59 is a surface of the horizontal portion and the second lower surface 57 is a surface of the vertical portion,
wherein the first lower surface 59 is located inside the encapsulant 55, and electrically connected to the semiconductor die 52 through a wiring 53 encapsulated by the encapsulant 55,
wherein the first lead 54 further comprises a recess (bend) connected between the first upper surface 59 and a lateral surface 58 of the vertical portion, the recess (bend) recessed from the first upper surface 59, and
wherein a portion of the encapsulant 55 is disposed in the recess (bend).
Claim(s) 16, 21, 22, 25, 26 is/are, to the extent taught and understood, rejected under 35 U.S.C. 103 as being unpatentable over Shibuya in view of Nguyen and Crowley as applied to claim 11 above, and further in view of U.S. Patent Application Publication No. 2019/0267310 (Rodriguez).
The combination of references fails to teach
16. (Currently Amended) The electronic device of claim 11, wherein the connecting element has a first edge and a second edge, and the first edge on the first upper surface of the connection element, and the second edge overlap a bottom surface of the connecting element in a direction perpendicular to the bottom surface, and wherein the connecting element has a bottom surface opposite to the first upper surface of the connecting element and exposed by the second surface of the encapsulant, and wherein the first edge and the second edge are at the same elevation relative to the bottom surface.
Rodriguez teaches ([0076]-[0078])
An electronic device comprising:
wherein the connecting element 12 has a first edge and a second edge, and the first edge on the first upper surface of the connection element 12, and the second edge overlap a bottom surface of the connecting element 12 in a direction perpendicular to the bottom surface, and wherein the connecting element 12 has a bottom surface opposite to the first upper surface of the connecting element 12 and exposed by the second surface of the encapsulant, and wherein the first edge and the second edge are at the same elevation relative to the bottom surface.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a connecting element having a surface exposed from the encapsulant in the modified device of Shibuya. The motivation would be to improve adhesion, and other well-known benefits such as thermal dissipation and electrical grounding as taught by Rodriguez ([0007]).
Rodriguez teaches
21. (Currently Amended) The electronic device of claim 12, wherein a first lateral surface of the carrier 16 and a second lateral surface of the first lead 14 face each other and have substantially a same magnitude of slope but opposite signs.
22. (Currently Amended) The electronic device of claim 21, wherein the second lateral surface is covered by the encapsulant ([0076]-[0078]) and the first lead 14 further has a third lateral surface exposed from the encapsulant ([0076]-[0078]), and wherein the second lateral surface of the first lead 14 and the third lateral surface of the first lead 14 are non-parallel with each other, wherein the connecting element 12 has a fourth lateral surface covered by the encapsulant ([0076]-[0078]), and wherein the fourth lateral surface and the second lateral surface are non-parallel with each other.
Rodriguez teaches
25. (Currently Amended) The electronic device of claim 11, wherein the connection element 12 comprises a first recess having a first depth in the first direction perpendicular, wherein the first depth is greater than a height of the carrier 16, and wherein the encapsulant ([0076]-[0078]) comprises a first portion disposed in the first recess and a second portion covering the carrier 16, and wherein the first portion is separated from the second portion in a cross-section.
Rodriguez teaches
26. (Currently Amended) The electronic device of claim 25, wherein the first lead 14 comprises a second recess having a second depth in the first direction shorter than the first depth, and the encapsulant ([0076]-[0078]) further comprises a third portion disposed in the second recess, and wherein the third portion is separated from the second portion in the cross-section.
Claim(s) 17 is/are, to the extent taught and understood, rejected under 35 U.S.C. 103 as being unpatentable over Shibuya in view of Nguyen, Crowley, and Rodriguez as applied to claim 16 above, and further in view of U.S. Patent Application Publication No. 2019/0198454 (Talledo).
The combination of references fails to teach
17. (Currently Amended) The electronic device of claim 16, wherein the first edge and the second edge are intersected, and wherein the first edge is non-parallel with the second edge.
Talledo teaches (at least Figs. 5A-D)
An electronic device comprising:
a connecting element 406, wherein the first edge and the second edge are intersected (at 431), and wherein the first edge is non-parallel with the second edge.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a connecting element having a sloped edge in the modified device of Shibuya. The motivation would be to assist in forming a tight bond or seal between molding compound that surrounds each tie bar as taught by Talledo ([0065]-[0067]).
Claim(s) 23, 24 is/are, to the extent taught and understood, rejected under 35 U.S.C. 103 as being unpatentable over Shibuya in view of Nguyen and Crowley and Rodriguez as applied to claim 16 above, and further in view of U.S. Patent No. 6,847,099 (Bancod).
The combination of references fails to teach
23. (Currently Amended) The electronic device of claim 16, wherein the connecting element has a forked shape structure at the bottom surface of the connecting element, and wherein the forked shape structure and the first edge are at different elevations relative to the bottom surface.
Bancod teaches (Figs. 2, 4)
An electronic device, comprising:
wherein the connecting element 24 has a forked shape structure at the bottom surface of the connecting element 24, and wherein the forked shape structure and the first edge are at different elevations relative to the bottom surface.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a forked shaped structure in the modified device of Shibuya. The motivation would be to provide adequate clearance parameters as taught by Bancod (column 4, line 66 to column 5, line 19).
Rodriguez teaches
24. (Currently Amended) The electronic device of claim 23, wherein the connection element 12 comprises a first recess recessed from the first upper surface of the connection element 12 and the first lead 14 comprises a second recess recessed from the first upper surface of the first lead 14, wherein a first depth of the first recess is greater than a second depth of the second recess in the first direction, and wherein a first width of the first recess is greater than a second width of the second recess in a second direction perpendicular to the first direction.
Claim(s) 29, 30 is/are, to the extent taught and understood, rejected under 35 U.S.C. 103 as being unpatentable over Shibuya in view of Nguyen and Crowley as applied to claim 11 above, and further in view of JP Publication No. 2014-154807 (Kuratomi).
The combination of references fails to teach
29. (Currently Amended) The electronic device of claim 11, further comprising a protective layer covering the first upper surface of the first lead and a top surface of the carrier.
Kuratomi teaches
An electronic device comprising:
a protective layer 33r / 33f covering the first upper surface of the first lead 34 and a top surface of the carrier 33.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide cover a surface of the lead and carrier with a protective layer in the modified device of Shibuya. The motivation would be to prevent solder bridging during assembly, protect exposed metal from corrosion and oxidation, and control solder flow to ensure precise, reliable electrical connections on high-density microelectronic packages, which is well-known in the art such as in Kuramoti. See MPEP 2144.03.
Kuratomi teaches
30. (Currently Amended) The electronic device of claim 29, wherein, an interface is between the protective layer 33f / 33r and the encapsulant 30.
Claim(s) 31 is/are, to the extent taught and understood, rejected under 35 U.S.C. 103 as being unpatentable over Shibuya in view of Nguyen and Crowley as applied to claim 11 above, and further in view of U.S. Patent No. 9,337,140 (Kumar).
The combination of references fails to teach
31. (New) The electronic device of claim 11, further comprising:
a plurality of leads surrounding the carrier and including the first lead;
a plurality of first wirings connecting the semiconductor die with the leads,
wherein a first number of the leads is greater than a second number of the first wirings; and
a plurality of second wirings connecting the carrier with the leads, wherein the first number of the leads is greater than a third number of the second wirings,
wherein the first number is greater than a sum of the second number and the third number.
Kumar teaches
An electronic device comprising:
a plurality of leads 120 / 124 surrounding the carrier 132 and including the first lead 120;
a plurality of first wirings 122 connecting the semiconductor die 112 with the leads 120,
wherein a first number of the leads 120 / 124 is greater than a second number of the first wirings 122; and
a plurality of second wirings 130 connecting the carrier 132 with the leads 124, wherein the first number of the leads 120 / 124 is greater than a third number of the second wirings 130,
wherein the first number is greater than a sum of the second number and the third number.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of leads and a plurality of wirings, one being greater in number in the modified device of Shibuya. The motivation would be to implement a shield that can reduce the noise effects on the signals traversing the bond wires as taught by Kumar. Further, extra leads allow future layout changes.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Nos. 6,459,148 (Chun-Jen), 6,008,528 (Go), U.S. Patent Application Publication Nos. 2012/0181555 (Yoo), 2008/0157297 (Kudoh) teach an electronic device including exposed and bent leads and tie bars.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
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