Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Sankman (US 2019/0371778, as disclosed in previous office action) in view of Park et al. (US 2009/0189272, as disclosed in previous office action) and Liu et al. (US 2023/0031430).
As for claims 1 and 6, Sankman et al. disclose in Fig. 16 and the related text a method for preparing a high-density-interconnection (HDI) packaging structure for semiconductor chips, comprising:
1) providing at least two chips 110/120, disposing a first metal array 230/260 with a first pitch and a second metal array 250/270 with a second pitch over each of the two clips;
2) providing a silicon connector 140 [0037], disposing a third metal array 310/320 over the silicon connector 140, and bonding the silicon connector across the two chips by arranging to connect the third metal array and the first metal array (fig. 4, [0039]),
3) forming a molding layer 150 covering the first metal array, second metal array, the two chips and the silicon connector 140 [0045];
4) grinding the molding layer 150 to expose the silicon connector first [0054], then continuing to grind the silicon connector until the silicon conductor becomes ultra-thin silicon [0101]
5) forming vias 1520 in the molding layer (Fig. 6), wherein the vias are aligned to the second metal array, filling the vias with metal materials (Fig. 16, [0078]), wherein the metal materials are connected to the second metal array 220; and
6) forming metal structures 1510 (Fig. 16) over the vias which are filled with metal material [0078], wherein the metal pillar structures 1510 are connected to the metal materials in the vias 1520, and connecting the metal structures 1510 to the substrate 160 and forming an underfill layer 170 material the substrate 160 and the molding layer 150, and between the substrate 160 and the silicon connector 140 (Fig. 16).
Sankman et al. do not disclose disposing a first dielectric layer over the two chip, wherein the first metal array and the second metal array form in the first dielectric layer; disposing a second dielectric layer, wherein the third metal array form in the second dielectric layer over the silicon connector, arranging to connect the third metal array and the first metal array by surface hybrid bonding, wherein the third metal array and the first metal array are aligned to each other and are bonded together, and wherein the first dielectric layer located under the silicon connector and the second dielectric layer are aligned to each other and are bonded together; and the substrate is an organic substrate.
Liu et al. teach in Figs. 1-5 and the related text disposing a first dielectric layer 213/313 over the two chip 202/302, wherein the first metal array and the second metal array 212/312 form in the first dielectric layer 213/313; disposing a second dielectric layer 113 over connector 102, wherein the third metal array 112 form in the second dielectric layer 113 over the silicon connector (Fig. 5); and arranging to connect the third metal array 112 and the first metal array 212/312 by surface hybrid bonding [0021], wherein the third metal array 112 and the first metal array are aligned to each other and are bonded together (fig. 3), and wherein the first dielectric layer 213/313 located under the silicon connector (Fig. 5) and the second dielectric layer 113 are aligned to each other and are bonded together (Fig. 3-5).
Park et al. teach in [0026] a substrate is an organic substrate.
Sankman et al., Liu et al. and Park et al. are analogous art because they both are directed packaging structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Sankman et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Sankman et al. to include the first dielectric layer and the second dielectric layer as claimed as taught by Liu et al., in order to protect the conductive pads and improve interconnections and include organic as a material of the substrate as taught by Park et al., at least to suitable material for a substrate.
As for claims 2-3 and 6-7, Sankman et al. disclosed substantially the entire claimed invention as applied in claim 1, except the first pitch is less than or equal to 10 µm; the second pitch is in a range between 20 µm and 150 µm; a thickness of the ultra-thin silicon is less than or equal to 30 µm; and the vias have a depth-to-diameter aspect ratio in a range of 3:1 to 5:1.
The determination and selection of parameters including dimensions (length, width, thickness, diameter, etc.), via layout/configuration, a pitch/spacing, a total number and a shape thereof, a ratio of dimensions, etc., of a via/plug, pad, trace/wiring, metal array, solder ball/bump, etc., in Semiconductor Device (SD) Packaging Technology art is a subject of routine experimentation and optimization to achieve improved metal fill, bonding strength, reliability and reduced stress.
Therefore, It would have been obvious to one having ordinary skill in the art at the time the invention was made to provide said limitations, in order to optimize the performance of the device. Furthermore, it has been held that discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233; In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Sankman) in view of Park et al., Liu et al. and further in view of Crane et al. (US 7109061).
As for claim 4, Sankman et al. and Park et al. disclosed substantially the entire claimed invention as applied in claim 1, except forming the underfill layer comprises one or more of ink let printing, dispensing, compression molding, transfer molding, liquid seal moldinq, vacuum lamination, and wherein a material of the underfill layer comprises one or more of polyimide, silicone, and epoxy resin.
Crane et al. teach in col. 6 lines 10-14 forming the underfill layer comprises one or more of ink let printing, dispensing; and in col. 14 lines 7-44 a material of the underfill layer comprise epoxy resin.
Sankman et al., Park et al. and Chen et al. are analogous art because they are directed packaging structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include said limitations as taught by Chen et al., in order to enhance adhesive strength (Col. 9 lines 45-52).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sankman in view of Park et al., Liu et al. and further in view of Lu (US 2021/0202395 as disclose in previous office action).
As for claims 8, Sankman et al. and Park et al. disclosed substantially the entire claimed invention as applied in claim 1, except forming the metal pillar structures over the vias filled with metal material further comprises: first, forming bumps connected to the metal materials of the vias; forming metal pillars on the bumps; and finally, forming solder caps on the metal pillars.
Lu teaches in Figs. 1-26 and the related text forming the metal pillar structures over the vias with metal material further comprises: first, forming bumps 42 connected to the metal materials of the vias 41; forming metal pillars 71 on the bumps 42; and finally, forming solder caps 62 on the metal pillars 42 (Fig. 23-26, [0088]-[0096]).
Sankman et al., Park et al. and Lu are analogous art because they are directed packaging structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include said limitations as taught by Lu, in order to improve interconnections.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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