Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-8) in the reply filed on 10/31/2025 is acknowledged.
Claims 9-15 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/31/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the metal-filled vias" in line 14. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the chip" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation "the filled vias" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Sankman (US 2019/0371778) in view of Park et al. (US 2009/0189272).
As for claim 1, Sankman et al. disclose in Figs. 1-8 and the related text a method for preparing a high-density-interconnection (HDI) packaging structure for semiconductor chips, comprising:
1) providing at least two chips 110/120, disposing a first metal array 230/260 with a first pitch and a second metal array 250/270 with a second pitch over each of the two clips;
2) providing a silicon connector 140 [0037], disposing a third metal array 310/320 over the silicon connector 140, and bonding the silicon connector across the chips by arranging to connect the third metal array and the first metal array (fig. 4, [0039]),
3) forming a molding layer 150 covering the ups and the silicon connector 140 [0045];
4) grinding the molding layer 150 to expose the silicon connector first [0054], then continuing to grind the silicon connector until the silicon conductor becomes ultra-thin silicon [0101]
5) forming vias 600 in the molding layer (Fig. 6), wherein the vias are aligned to the second metal array, filling the vias with metal materials, wherein the metal materials are connected to the second metal array [0050]; and
6) forming metal pillar structures 710 (Fig. 7) over the metal-filled vias wherein the metal pillar structures 710 are connected to the metal materials in the vias, and wherein the metal pillar structures 700 are also connected to a dielectric substrate 160.
Sankman et al. do not disclose the substrate is an organic substrate [0026].
Park et al. teach in [0026] a substrate is an organic substrate.
Sankman et al. and Park et al. are analogous art because they both are directed packaging structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Sankman et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Sankman et al. to include organic as a material of the substrate as taught by Park et al., at least to suitable material for a substrate.
As for claims 2-3 and 6-7, Sankman et al. disclosed substantially the entire claimed invention as applied in claim 1, except the first pitch is less than or equal to 10 µm; the second pitch is in a range between 20 µm and 150 µm; a thickness of the ultra-thin silicon is less than or equal to 30 µm; and the vias have a depth-to-diameter aspect ratio in a range of 3:1 to 5:1.
The determination and selection of parameters including dimensions (length, width, thickness, diameter, etc.), via layout/configuration, a pitch/spacing, a total number and a shape thereof, a ratio of dimensions, etc., of a via/plug, pad, trace/wiring, metal array, solder ball/bump, etc., in Semiconductor Device (SD) Packaging Technology art is a subject of routine experimentation and optimization to achieve improved metal fill, bonding strength, reliability and reduced stress.
Therefore, It would have been obvious to one having ordinary skill in the art at the time the invention was made to provide said limitations, in order to optimize the performance of the device. Furthermore, it has been held that discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233; In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Sankman (US 2019/0371778) in view of Park et al. (US 2009/0189272) and further in view of Chen et al. (US 2023/0095134).
As for claims 4-5, Sankman et al. and Park et al. disclosed substantially the entire claimed invention as applied in claim 1, except wherein the operation 1) further comprises: disposing a first dielectric layer over the chips, wherein the first metal array and the second metal array are formed in the first dielectric layer. wherein the operation 2) further comprises disposing a second dielectric layer over the silicone connector, wherein the third metal array is formed in the second dielectric layer.
Chen et al. teach in Fig. 15 and the related text disposing a first dielectric layer 18 over the chips 105a/105b, wherein the first metal array and the second metal array 20b/20d are formed in the first dielectric layer 18 (fig. 15), further comprises disposing a second dielectric layer 352 over the silicone connector 305, wherein the third metal array 351b/354d is formed in the second dielectric layer (Fig. 15); and arranging to connect the third metal array and the first metal array by surface hybrid bonding [0067], wherein the third metal array and the first metal array are aligned to each other and are bonded together (fig. 15), and wherein the first dielectric layer located under the silicon connector and the second dielectric layer are aligned to each other and are bonded together (Fig. 15).
Sankman et al., Park et al. and Chen et al. are analogous art because they are directed packaging structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include said limitations as taught by Chen et al., in order to improve bonding process and protect conductive pads.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sankman (US 2019/0371778) in view of Park et al. (US 2009/0189272) and further in view of Lu (US 2021/0202395).
As for claims 8, Sankman et al. and Park et al. disclosed substantially the entire claimed invention as applied in claim 1, except forming the metal pillar structures over the filled vias further comprises: first, forming bumps connected to the metal materials of the vias; forming metal pillars on the bumps; and finally, forming solder caps on the metal pillars.
Lu teaches in Figs. 1-26 and the related text forming the metal pillar structures over the filled vias further comprises: first, forming bumps 42 connected to the metal materials of the vias 41; forming metal pillars 71 on the bumps 42; and finally, forming solder caps 62 on the metal pillars 42 (Fig. 23-26, [0088]-[0096]).
Sankman et al., Park et al. and Lu are analogous art because they are directed packaging structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include said limitations as taught by Lu, in order to improve interconnections.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811