Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Argument & Amendment
The amendment filed on 03/13/2026 under 37 CFR 1.131 has been considered.
In regard to independent claims 1 & 14, applicant’s arguments are not persuasive.
Applicant argues that neither Takeuchi nor Hitora provides a motivation to apply the p-type semiconductor layer of secondary reference Hitora to the deep p- type layer of primary reference Takeuchi.
In response to applicant' s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the examiner would like to note that as disclosed in the non-final office action, Hitora provides a motivation “improving pressure resistance and suppressing leakage current”.
The applicant argues that Hitora neither discloses nor suggests an impurity concentration or a carrier concentration of the p-type semiconductor layer.
The examiner would like to note that primary reference Takeuchi teaches a carrier concentration of the deep p layer is higher than a carrier concentration of the channel layer (Fig. 1, element 5 is p type and element 3b is p- type). The secondary reference Hitora is disclosed to teach the deep p layer is formed by a crystalline oxide semiconductor and not the impurity concentration or a carrier concentration of the p-type semiconductor layer.
The applicant argues that Hitora does not contain any disclosure related to a deep p-type layer buried to a depth equal to or deeper than the lower embedded end of the gate, as taught by Takeuchi.
The examiner would like to note that as noted by the applicant and disclosed in the non-final office action, primary reference Takeuchi teaches a deep p-type layer buried to a depth equal to or deeper than the lower embedded end of the gate. The secondary reference Hitora is disclosed to teach the deep p layer is formed by a crystalline oxide semiconductor and not the depth of the p-type buried layer.
The applicant argues that the Examiner's proposed combination of Takeuchi and Hitora amounts to impermissible hindsight.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
The applicant further argues that one of ordinary skill in the art would not have had a reasonable expectation of success that, after such a substitution, the deep p-type layer would maintain the electric-field crowding mitigation function at the lower end of the gate electrode that is achieved by the deep p-type layer of -Takeuchi.
The examiner would like to note that the specification of Takeuchi does not appear to require a specific type of material for the p-type layer for the electric filed mitigation function.
In regards to amended independent claim 11, applicant’s argument on the amended limitation “Oda does not teach or suggest applying the alleged high-breakdown-field characteristic to both the semiconductor layer and the deep p-layer in Takeuchi simultaneously” is persuasive.
Accordingly, claims 11-12 are allowed (claim 13 will be rejoined pending completion of prosecution).
DETAILED ACTION
This action is responsive to application No. 18133246 filed on 4/11/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of claims 1-12, 14-15 in the reply filed on 9/2/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7, 9-10, 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi et al. (US 2019/0035882) in view of Hitora et al. (JP 2016025256 A).
Regarding Independent claim 1, Takeuchi et al. teach a semiconductor device, comprising:
a gate electrode (Fig. 1, element 8) having at least a part buried in a semiconductor layer (Fig. 1, element 2);
a deep p layer (Fig. 1, element 5) having at least a part buried in the semiconductor layer to a same depth as a buried lower end portion of the gate electrode or a position deeper than the buried lower end portion; and
a channel layer (Fig. 1, element 3b, paragraph 0034),
a carrier concentration of the deep p layer is higher than a carrier concentration of the channel layer (Fig. 1, element 5 is p type and element 3b is p- type).
Takeuchi et al. do not explicitly disclose wherein: the deep p layer is formed by a crystalline oxide semiconductor.
Hitora et al. teach a semiconductor device comprising a p layer is formed by a crystalline oxide semiconductor (specification discloses “The p-type semiconductor layer is a p-type semiconductor layer having a composition different from that of the n-type semiconductor layer, and is not particularly limited as long as it contains an inorganic compound having a hexagonal crystal structure as a main component. The inorganic compound is not particularly limited as long as it has a hexagonal crystal structure, and may be a known one. In the present invention, the “hexagonal crystal” may have a strain. Examples of the inorganic compound include silicon carbide (SiC), gallium nitride (GaN), and a metal compound, and a metal compound is particularly preferable. Examples of the metal compound include metal oxide, metal sulfide, metal nitride, metal halide, metal selenide, and metal telluride. In the present invention, metal oxide or metal sulfide is used”).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Takeuchi et al. according to the teachings of Hitora et al. with the motivation to “improving pressure resistance and suppressing leakage current”.
Regarding claim 3, Takeuchi et al. modified by Hitora et al. teach wherein the crystalline oxide semiconductor has a corundum structure or a β-gallia structure (specification of Hitora discloses “Examples of the other layer include a corundum structure crystal film having a different composition”).
Regarding claim 4, Takeuchi et al. modified by Hitora et al. teach wherein the crystalline oxide semiconductor is gallium oxide or mixed crystal of gallium oxide (specification discloses “The p-type semiconductor layer is a p-type semiconductor layer having a composition different from that of the n-type semiconductor layer, and is not particularly limited as long as it contains an inorganic compound having a hexagonal crystal structure as a main component. The inorganic compound is not particularly limited as long as it has a hexagonal crystal structure, and may be a known one. In the present invention, the “hexagonal crystal” may have a strain. Examples of the inorganic compound include silicon carbide (SiC), gallium nitride (GaN), and a metal compound, and a metal compound is particularly preferable. Examples of the metal compound include metal oxide, metal sulfide, metal nitride, metal halide, metal selenide, and metal telluride. In the present invention, metal oxide or metal sulfide is used”. Accordingly, before the effective filling date of the invention it would have been obvious to one having ordinary skill in the art to select a known gallium metal for the metal oxide, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416).
Regarding claim 5, Takeuchi et al. teach wherein the carrier concentration of the deep p layer is 1× 10.sup.17/cm.sup.3 or more (paragraph 0026).
Regarding claim 6, Takeuchi et al. teach wherein the semiconductor layer is an n-type semiconductor layer (Fig. 1).
Regarding claim 7, Takeuchi et al. modified by Hitora et al. teach wherein the semiconductor layer is a crystalline oxide semiconductor layer (Hitora discloses “The n-type semiconductor layer is not particularly limited as long as it includes a crystalline oxide semiconductor having a corundum structure as a main component”).
Regarding claim 9, Takeuchi et al. modified by Hitora et al. teach wherein the semiconductor layer has a corundum structure or a β-gallia structure (Hitora discloses “The n-type semiconductor layer is not particularly limited as long as it includes a crystalline oxide semiconductor having a corundum structure as a main component”).
Regarding claim 10, Takeuchi et al. modified by Hitora et al. teach wherein the semiconductor layer contains gallium oxide or mixed crystal of gallium oxide (Hitora discloses “The n-type semiconductor layer is not particularly limited as long as it includes a crystalline oxide semiconductor having a corundum structure as a main component. In the present invention, the crystalline oxide semiconductor preferably contains one or more elements selected from indium, aluminum and gallium”).
Regarding Independent claim 14, Takeuchi et al. teach semiconductor device, comprising:
a gate insulating film (Fig. 1, element 7) and a gate electrode (Fig. 1, element 8) each having at least a part buried in an n-type semiconductor layer (Fig. 1, element 2);
a first deep p layer (Fig. 1, element 5) and a second deep p layer (Fig. 1, element 5) each having at least a part buried in the semiconductor layer to a same depth as a buried lower end portion of the gate electrode or a position deeper than the buried lower end portion; and
a channel layer (Fig. 1, element 3b, paragraph 0034),
wherein: the gate insulating film and the gate electrode are provided on an upper side between the first deep p layer and the second deep p layer (Fig. 1);
a carrier concentration of each of the deep p layers is higher than a carrier concentration of the channel layer (Fig. 1, element 5 is p type and element 3b is p- type).
Takeuchi et al. do not explicitly disclose both of the deep p layers are formed by a crystalline oxide semiconductor.
Hitora et al. teach a semiconductor device comprising a p layer is formed by a crystalline oxide semiconductor (specification discloses “The p-type semiconductor layer is a p-type semiconductor layer having a composition different from that of the n-type semiconductor layer, and is not particularly limited as long as it contains an inorganic compound having a hexagonal crystal structure as a main component. The inorganic compound is not particularly limited as long as it has a hexagonal crystal structure, and may be a known one. In the present invention, the “hexagonal crystal” may have a strain. Examples of the inorganic compound include silicon carbide (SiC), gallium nitride (GaN), and a metal compound, and a metal compound is particularly preferable. Examples of the metal compound include metal oxide, metal sulfide, metal nitride, metal halide, metal selenide, and metal telluride. In the present invention, metal oxide or metal sulfide is used”).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Takeuchi et al. according to the teachings of Hitora et al. with the motivation to “improving pressure resistance and suppressing leakage current”.
Regarding claim 15, Takeuchi et al. teach the semiconductor device according to claim 1 that is a normally-off-type semiconductor device (paragraph 0010, it would be within the grasp of one of ordinary skill in the art to use the MOSFET device as claimed).
Claims 2, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi et al. (US 2019/0035882) in view of Hitora et al. (JP 2016025256 A) and further in view of Oda et al. (US 2018/0097073).
Regarding claim 2, Takeuchi et al. modified by Hitora et al. teach all of the limitations as discussed above.
Takeuchi et al. modified by Hitora et al. do not explicitly disclose wherein a breakdown field strength of the crystalline oxide semiconductor is 5 MV/cm or more.
Oda et al. teach a semiconductor device comprising a p-type layer with a breakdown field that is 6 MV/cm or more (paragraph 0050-0051).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Takeuchi et al. and Hitora et al. according to the teachings of Oda et al. with the motivation to improve current density-voltage (paragraph 0235).
Regarding claim 8, Takeuchi et al. modified by Hitora et al. teach all of the limitations as discussed above.
Takeuchi et al. modified by Hitora et al. do not explicitly disclose wherein a breakdown field strength of the semiconductor layer is 5 MV/cm or more.
Oda et al. teach a semiconductor device comprising a n-type layer with a breakdown field that is 6 MV/cm or more (paragraph 0050-0051).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Takeuchi et al. and Hitora et al. according to the teachings of Oda et al. with the motivation to improve current density-voltage (paragraph 0235).
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/Primary Examiner, Art Unit 2813
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