Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figures 1, 2, and 3 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g).
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
“20” (paragraph [0034], line 6) must be changed to --520--as per FIG. 5.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 4 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
The first row is different from the second row considering that the first row is of “transmit physical layers (TX PHYs)” [lines 3-4] while the second row is of “receive physical layers (RX PHYs)” [lines 4-5]. Thus, the claim does not further limit because a first row of TX PHYs is different than a second row of RX PHYs.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9, 11-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Kolor et al. [US 2022/0284163 A1].
1.A device [0002 SOC IC to form a given device, 0004 a range of applications], comprising:
an interposer [0075 interposer device 530, 0077 interposer device 530a-c];
and a first IC disposed on the interposer [FIG. 1 element 101a, FIG. 5A element 501a], the first IC comprising a first row of transmit physical layers (TX PHYs) parallel to a periphery of the first IC [FIGS . 1 and 5A elements 120a, 0046 circuits may be physically located is interpreted as physical layers PHYs] and a second row of receive physical layers (RX PHYs) parallel to the periphery of the first IC [FIGS . 1 and 5A elements 125a]; and
a second IC disposed on the interposer [FIG. 1 element 101b, FIG. 5A element 501b], the second IC comprising a third row of TX PHYs parallel to a periphery of the second IC [FIGS . 1 and 5A elements 120b] and a fourth row of RX PHYs parallel to the periphery of the second IC [FIGS . 1 and 5A elements 125b],
chip-to-chip connections [0023 complementary inter-IC interfaces, 0024 transmit and receive, 0027 pairs], in the interposer [0037 an interposer device may be used], coupling respective ones of the RX PHYs in the first IC to the TX PHYs in the second IC and respective ones of the RX PHYs in the second IC to the TX PHYs in the first IC [0030, 0031 collectively external interfaces 110].
2. The device of claim 1, wherein the chip-to-chip connections are non-crossing [0036 do not cross wires, do not cross a wire, 0074 coupled without crossing any wires].
3. The device of claim 2, wherein each of the TX PHYs in the first IC is aligned in a same column as one of the RX PHYs in the second IC [FIGS. 1 and 5A transmit pin 120a and receive pin 125b] and each of the TX PHYs in the first IC is aligned in a same column as one of the RX PHYs in the first IC [0027 pairs of bi-directional pins].
4. The device of claim 1, wherein the first row is different from the second row and the third row is different from the fourth row [0046-0047 sets are co-located; see, also, 112(d) above].
5. The device of claim 1, wherein the first IC has a circuit layout that mirrors a circuit layout of the second IC [0037 face-to-face is interpreted as mirrors, 0076 face-to-face].
6. The device of claim 5, wherein bit re-ordering is not performed by the first IC and second IC on bits received by the chip-to-chip connections [0023 complementary, 0024 transmit and receive a particular bit, 0034 in a same order].
7. The device of claim 1, wherein the first IC has a circuit layout that is the same as a circuit layout of the second IC [0029 two or more ICs of a same design], wherein the circuit layout of the first IC is rotated 180 degrees relative to the circuit layout of the second IC [0036 by rotating 180 degrees].
8. The device of claim 7, wherein the first IC and second IC are configured to perform bit re-ordering on bits received by the chip-to-chip connections [0055 an order of bits may not align directly, misalignment, 0059 reroute pins, 0090 reroute, adjust individual bits, 0091 reroute, desired order, 0092 proper bit position].
9. The device of claim 1, further comprising: a third IC disposed on the interposer [0029 two or more ICs provides for a third, 0075 interposer device 530, 0077 interposer device 530a-c], the third IC comprising a fifth row of TX PHYs parallel to a periphery of the third IC [FIGS . 1 and 5A elements 120a, 0046 circuits may be physically located is interpreted as physical layers PHYs] and a sixth row of RX PHYs parallel to the periphery of the third IC [FIGS . 1 and 5A elements 125a], wherein the chip-to-chip connections couple respective ones of the RX PHYs in the third IC to the TX PHYs in the first IC [0023 complementary inter-IC interfaces, 0024 transmit and receive, 0030, 0031 collectively external interfaces 110] and respective ones of the RX PHYs in the first IC to the TX PHYs in the third IC [0029 two or more ICs provides for a third, enable various combinations of instances of two or more of the ICs, such a variety of combinations may provide highly scalable system solution across a wide range of applications, which is interpreted to provide for the specified arrangement as cited above accordingly for a scalable solution, 0101].
11. A method, comprising:
transmitting data [0024] from a first IC [FIG. 1 element 101a, FIG. 5A element 501a] to a second IC [FIG. 1 element 101b, FIG5A. element 501b] using chip-to-chip connections in an interposer [0030, 0031 collectively external interfaces 110], wherein the first and second ICs are disposed on the interposer [0023 complementary inter-IC interfaces, 0024 transmit and receive, 0027 pairs, 0037 an interposer device may be used , 0075 interposer device 530, 0077 interposer device 530a-c]; and
receiving the data at the second IC [0024],
wherein the first IC comprises a first row of transmit physical layers (TX PHYs) parallel to a periphery of the first IC [FIGS . 1 and 5A elements 120a, 0046 circuits may be physically located is interpreted as physical layers PHYs] and a second row of receive physical layers (RX PHYs) parallel to the periphery of the first IC [FIGS . 1 and 5A elements 125a], and
wherein the second IC comprises a third row of TX PHYs parallel to a periphery of the second IC [FIGS . 1 and 5A elements 120b] and a fourth row of RX PHYs parallel to the periphery of the second IC [FIGS . 1 and 5A elements 125b], and
wherein the chip-to-chip connections couple respective ones of the RX PHYs in the first IC to the TX PHYs in the second IC and respective ones of the RX PHYs in the second IC to the TX PHYs in the first IC [0023 complementary inter-IC interfaces, 0024 transmit and receive, 0027 pairs].
12. The method of claim 11, wherein the chip-to-chip connections are non-crossing [0036 do not cross wires, do not cross a wire, 0074 coupled without crossing any wires].
13. The method of claim 11, wherein each of the TX PHYs in the first IC is aligned in a same column as one of the RX PHYs in the second IC [FIGS. 1 and 5A transmit pin 120a and receive pin 125b] and each of the TX PHYs in the first IC is aligned in a same column as one of the RX PHYs in the first IC [0027 pairs of bi-directional pins].
14. The method of claim 11, wherein the first IC has a circuit layout that mirrors a circuit layout of the second IC [0037 face-to-face is interpreted as mirrors, 0076 face-to-face].
15. The method of claim 14, wherein bit re-ordering is not performed by the first IC and second IC on bits received by the chip-to-chip connections [0023 complementary, 0024 transmit and receive a particular bit, 0034 in a same order].
16. The method of claim 11, wherein the first IC has a circuit layout that is the same as a circuit layout of the second IC [0029 two or more ICs of a same design], wherein the circuit layout of the first IC is rotated 180 degrees relative to the circuit layout of the second IC [0036 by rotating 180 degrees].
17. The method of claim 16, further comprising: performing bit re-ordering on the data received by second IC [0055 an order of bits may not align directly, misalignment, 0059 reroute pins, 0090 reroute, adjust individual bits, 0091 reroute, desired order, 0092 proper bit position].
18. The method of claim 11, further comprising: transmitting data from the first IC to a third IC disposed on the interposer [0029 two or more ICs provides for a third, 0075 interposer device 530, 0077 interposer device 530a-c], wherein the third IC comprises a fifth row of TX PHYs parallel to a periphery of the third IC [FIGS . 1 and 5A elements 120a, 0046 circuits may be physically located is interpreted as physical layers PHYs] and a sixth row of RX PHYs parallel to the periphery of the third IC [FIGS . 1 and 5A elements 125a], wherein the chip-to-chip connections couple respective ones of the RX PHYs in the third IC to the TX PHYs in the first IC [0023 complementary inter-IC interfaces, 0024 transmit and receive, 0030, 0031 collectively external interfaces 110] and respective ones of the RX PHYs in the first IC to the TX PHYs in the third IC [0029 two or more ICs provides for a third, enable various combinations of instances of two or more of the ICs, such a variety of combinations may provide highly scalable system solution across a wide range of applications, which is interpreted to provide for the specified arrangement as cited above accordingly for a scalable solution, 0101].
19. A device [0002 SOC IC to form a given device, 0004 a range of applications], comprising:
an interposer [0075 interposer device 530, 0077 interposer device 530a-c]; and
a first FPGA disposed on the interposer, the first FPGA comprising a first circuit design [FIG. 1 element 101a, FIG. 5A element 501a, the generic term IC is interpreted as an FPGA which is a form of SoC the generic term IC is interpreted as an FPGA which is a form of SoC]; and
a second FPGA disposed on the interposer [FIG. 1 element 101b, FIG. 5A element 501b], the second FPGA comprising a second circuit design[0029] that is a mirror of the first circuit design [0037 face-to-face is interpreted as mirrors, 0076 face-to-face], wherein the interposer provides connections between the first and second FPGAs [0023 complementary inter-IC interfaces, 0037 an interposer device may be used].
20. A device [0002 SOC IC to form a given device, 0004 a range of applications], comprising:
an interposer [0075 interposer device 530, 0077 interposer device 530a-c]; and
a first FPGA disposed on the interposer, the first FPGA comprising a first circuit design [FIG. 1 element 101a, FIG. 5A element 501a, 0029, the generic term IC is interpreted as an FPGA which is a form of SoC]; and
a second FPGA disposed on the interposer [FIG. 1 element 101b, FIG. 5A element 501b], the second FPGA comprising the first circuit design [0029], wherein the second FPGA is rotated relative to the first FPGA [0036 rotating], wherein the interposer provides connections between the first and second FPGAs [0023 complementary inter-IC interfaces, 0037 an interposer device may be used].
Claims 1-5, 7, 11-14, 16 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Chen et al. [US 10,515,939 B2].
1.A device, comprising:
an interposer [column 4, lines 31-37 CoWoS package];
and a first IC disposed on the interposer [FIG. 5 element 502_1, FIG. 6 element 602_1, FIG. 11 element 1102_1, see also FIG. 12], the first IC comprising a first row of transmit physical layers (TX PHYs) parallel to a periphery of the first IC [column 5, lines 39-column 6, line 63, P1 and P4 in FIG. 5, P1’-P4’ in FIG. 6, element 1106_1, column 11, lines 26 and 66 Tx/Rx multi-row I/O design] and a second row of receive physical layers (RX PHYs) parallel to the periphery of the first IC [column 5, lines 39-column 6, line 63, P2 and P4 in FIG. 5, P1’-P4’ in FIG. 6, element 1104_1 , column 11, lines 26 and 66 Tx/Rx multi-row I/O design]; and
a second IC disposed on the interposer [FIG. 5 element 502_2, FIG. 6 element 602_2, FIG. 11 element 1102_2, see also FIG. 12], the second IC comprising a third row of TX PHYs parallel to a periphery of the second IC [column 5, lines 39-column 6, line 63, P1 and P4 in FIG. 5, P1’-P4’ in FIG. 6, element 1106_2, column 11, lines 26 and 66 Tx/Rx multi-row I/O design] and a fourth row of RX PHYs parallel to the periphery of the second IC [column 5, lines 39-column 6, line 63, P2 and P4 in FIG. 5, P1’-P4’ in FIG. 6, element 1104_2, column 11, lines 26 and 66 Tx/Rx multi-row I/O design],
chip-to-chip connections, in the interposer, coupling respective ones of the RX PHYs in the first IC to the TX PHYs in the second IC and respective ones of the RX PHYs in the second IC to the TX PHYs in the first IC [column 5, lines 39-column 6, line 63, L1-L4 in FIG. 5, L1’-L4’ in FIG. 6, column 11, line 12-column 12, line 48 L11-L24 in FIG. 11, see also FIGS. 8 and 12].
2. The device of claim 1, wherein the chip-to-chip connections are non-crossing [column 12, lines 43-48, as depicted in FIGS. 6, 8, 11, 12].
3. The device of claim 2, wherein each of the TX PHYs in the first IC is aligned in a same column as one of the RX PHYs in the second IC and each of the TX PHYs in the first IC is aligned in a same column as one of the RX PHYs in the first IC [as depicted in FIGS. 6, 8, 11, 12].
4. The device of claim 1, wherein the first row is different from the second row and the third row is different from the fourth row [as depicted in FIGS. 6, 8, 11, 12; see, also, 112(d) above].
5. The device of claim 1, wherein the first IC has a circuit layout that mirrors a circuit layout of the second IC [column 8, lines 1-22 mirrors is interpreted as rotationally symmetric meaning an exact match, FIG. 8(A)].
7. The device of claim 1, wherein the first IC has a circuit layout that is the same as a circuit layout of the second IC [column 5, lines 50-51, column 6, lines 18-19, column 8, lines 23-24], wherein the circuit layout of the first IC is rotated 180 degrees relative to the circuit layout of the second IC [column 5, lines 57-58, column 6, lines 31-33, column 8, lines 1-22, 36-37].
11. A method, comprising:
transmitting data from a first IC [FIG. 5 element 502_1, FIG. 6 element 602_1, FIG. 11 element 1102_1, see also FIG. 12] to a second IC [FIG. 5 element 502_2, FIG. 6 element 602_2, FIG. 11 element 1102_2, see also FIG. 12] using chip-to-chip connections in an interposer [column 5, lines 39-column 6, line 63, L1-L4 in FIG. 5, L1’-L4’ in FIG. 6, column 11, line 12-column 12, line 48 L11-L24 in FIG. 11, see also FIGS. 8 and 12], wherein the first and second ICs are disposed on the interposer [column 4, lines 31-37 CoWoS package]; and
receiving the data at the second IC [FIG. 5 P2 and P3 on element 502_2, column 6, lines 13-15 for element 602_2, column 11, lines 12-13, 26-27 for element 1102_2],
wherein the first IC comprises a first row of transmit physical layers (TX PHYs) parallel to a periphery of the first IC [column 5, lines 39-column 6, line 63, P1 and P4 in FIG. 5, P1’-P4’ in FIG. 6, element 1106_1, column 11, lines 26 and 66 Tx/Rx multi-row I/O design] and a second row of receive physical layers (RX PHYs) parallel to the periphery of the first IC [column 5, lines 39-column 6, line 63, P2 and P4 in FIG. 5, P1’-P4’ in FIG. 6, element 1104_1 , column 11, lines 26 and 66 Tx/Rx multi-row I/O design], and
wherein the second IC comprises a third row of TX PHYs parallel to a periphery of the second IC [column 5, lines 39-column 6, line 63, P1 and P4 in FIG. 5, P1’-P4’ in FIG. 6, element 1106_2, column 11, lines 26 and 66 Tx/Rx multi-row I/O design and a fourth row of RX PHYs parallel to the periphery of the second IC [column 5, lines 39-column 6, line 63, P2 and P4 in FIG. 5, P1’-P4’ in FIG. 6, element 1104_2, column 11, lines 26 and 66 Tx/Rx multi-row I/O design], and
wherein the chip-to-chip connections couple respective ones of the RX PHYs in the first IC to the TX PHYs in the second IC and respective ones of the RX PHYs in the second IC to the TX PHYs in the first IC [column 5, lines 39-column 6, line 63, L1-L4 in FIG. 5, L1’-L4’ in FIG. 6, column 11, line 12-column 12, line 48 L11-L24 in FIG. 11, see also FIGS. 8 and 12].
12. The method of claim 11, wherein the chip-to-chip connections are non-crossing [column 12, lines 43-48, as depicted in FIGS. 6, 8, 11, 12].
13. The method of claim 11, wherein each of the TX PHYs in the first IC is aligned in a same column as one of the RX PHYs in the second IC and each of the TX PHYs in the first IC is aligned in a same column as one of the RX PHYs in the first IC [as depicted in FIGS. 6, 8, 11, 12].
14. The method of claim 11, wherein the first IC has a circuit layout that mirrors a circuit layout of the second IC [column 8, lines 1-22 mirrors is interpreted as rotationally symmetric meaning an exact match, FIG. 8(A)].
16. The method of claim 11, wherein the first IC has a circuit layout that is the same as a circuit layout of the second IC [column 5, lines 50-51, column 6, lines 18-19, column 8, lines 23-24], wherein the circuit layout of the first IC is rotated 180 degrees relative to the circuit layout of the second IC [column 5, lines 57-58, column 6, lines 31-33, column 8, lines 1-22, 36-37].
Claims 19-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Gibson et al. [US 2005/0194672 A1].
19. A device [FIG. 4, 0053], comprising:
an interposer [60 or 62, paragraph 0031, also FIG. 6]; and
a first FPGA disposed on the interposer, the first FPGA comprising a first circuit design [paragraph 0025 an FPGA is element 41, paragraph 0028 a unit or one of the 16 FPGAs, indeed all of the units are identical to one another]; and
a second FPGA disposed on the interposer [paragraph 0025 element 41, paragraph 0028 another unit of the 16 FPGAs, indeed all of the units are identical to one another], the second FPGA comprising a second circuit design that is a mirror of the first circuit design [0052 “mirrored”], wherein the interposer provides connections between the first and second FPGAs [0036, 0041, 0047 inputs and outputs of FPGAs in units of different stacks must be connected to one another, rotated].
20. A device [FIG. 4, 0053], comprising:
an interposer [60 or 62, paragraph 0031, also FIG.]; and
a first FPGA disposed on the interposer, the first FPGA comprising a first circuit design [paragraph 0025 an FPGA is element 41, paragraph 0028 a unit or one of the 16 FPGAs, indeed all of the units are identical to one another]; and
a second FPGA disposed on the interposer, the second FPGA comprising the first circuit design [paragraph 0025 element 41, paragraph 0028 another unit of the 16 FPGAs, indeed all of the units are identical to one another], wherein the second FPGA is rotated relative to the first FPGA, wherein the interposer provides connections between the first and second FPGAs [0036, 0041, 0047 inputs and outputs of FPGAs in units of different stacks must be connected to one another, rotated].
Claims 19- 20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Sankman et al. [US 2020/0402937 A1].
19. A device [0002, FIG. 1], comprising:
an interposer [element 110]; and
a first FPGA disposed on the interposer, the first FPGA comprising a first circuit design [element 1201, 0036 FPGAs]; and
a second FPGA disposed on the interposer [element 1204], the second FPGA comprising a second circuit design that is a mirror of the first circuit design [0036 identical circuit die, mirror is interpreted as die 1201 to 1204, i.e., by rotating the devices (see FIG. 2) 1201 appears to be a mirror of 1204, 1202 or 1205, etc.], wherein the interposer provides connections between the first and second FPGAs [0043 device-to-device conductive route 162].
20. A device [0002, FIG. 1], comprising:
an interposer [element 110]; and
a first FPGA disposed on the interposer [element 1201, 0036 FPGAs], the first FPGA comprising a first circuit design [identical circuit dice]; and
a second FPGA disposed on the interposer [element 1202], the second FPGA comprising the first circuit design [0035 identical circuit dice], wherein the second FPGA is rotated relative to the first FPGA [as depicted in FIGS. 1 and 2, 0039 and FIG. 5], wherein the interposer provides connections between the first and second FPGAs [0043 device-to-device conductive route 162].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kolor et al. [US 2022/0284163 A1] in view of Delacruz et al. [US 2020/0402913 A1].
Kolor et al. teach the features from which the claim depends, further comprising:
a fourth IC disposed on the interposer [0029 two or more ICs provides for a fourth, 0075 interposer device 530, 0077 interposer device 530a-c], the fourth IC comprising a seventh row of TX PHYs parallel to a periphery of the fourth IC [FIGS . 1 and 5A elements 120a, 0046 circuits may be physically located is interpreted as physical layers PHYs] and an eight row of RX PHYs parallel to the periphery of the fourth IC [FIGS . 1 and 5A elements 125a],
wherein the chip-to-chip connections couple respective ones of the RX PHYs in the fourth IC to the TX PHYs in the second IC and respective ones of the RX PHYs in the second IC to the TX PHYs in the fourth IC [0023 complementary inter-IC interfaces, 0024 transmit and receive, 0030, 0031 collectively external interfaces 110], and
wherein the chip-to-chip connections couple respective ones of the RX PHYs in the fourth IC to the TX PHYs in the third IC and respective ones of the RX PHYs in the third IC to the TX PHYs in the fourth IC [0023 complementary inter-IC interfaces, 0024 transmit and receive, 0030, 0031 collectively external interfaces 110, 0029 two or more ICs provides for a third, enable various combinations of instances of two or more of the ICs, such a variety of combinations may provide highly scalable system solution across a wide range of applications, which is interpreted to provide for the specified arrangement as cited above accordingly for a scalable solution, 0101].
However, Kolor et al. do not explicitly teach wherein the first, second, third, and fourth ICs are disposed in a 2x2 configuration.
Delacruz et al. teach a device comprising four ICs disposed on an interposer [FIG. 2, 0025 chips A, B, C, D, FIG. 3, 0031 chip 302A, 302B, 302C, 302D, 0042 devices can be integrated in a lower cost interposer], wherein the ICs are disposed in a 2x2 configuration [as depicted in FIGS. 2 and 3]. Thus, considering that Kolor et al. teach a scalable solution enabling use of one or more ICs and Delacruz et al. teach lower cost, the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because the density of ICs can be increased [0002].
Claims 9-10, 18 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Chen et al. [US 10,515,939 B2] over Martorell et al. [US 2021/0111113 A1].
Taking claim 9 as exemplary of claims 9 and 18, Chen et al. teach the features from which the claim depends, further comprising: a third IC disposed on the interposer [FIG. 7 element 702_3, FIG. 9 element 902_3, FIG. 10 element 1002_3, column 8, lines 54-67], the third IC comprising a fifth row of TX PHYs parallel to a periphery of the third IC [column 7, lines 2-8 transmitting, column 9, lines 6-11 transmitting, column 10, lines 35-47 transmitting] and a sixth row of RX PHYs parallel to the periphery of the third IC [column 7, lines 2-8 receiving, column 9, lines 6-11 receiving, column 10, lines 35-47 receiving]. It is also noted that Martorell et al. teach a third IC including arrays of input/output (receiving/transmitting) contacts [0030-0031, 0049-0050, 0055].
However, Chen et al. do not teach wherein the chip-to-chip connections couple respective ones of the RX PHYs in the third IC to the TX PHYs in the first IC and respective ones of the RX PHYs in the first IC to the TX PHYs in the third IC.
Martorell et al. teach a device comprising an interposer [0002, 0029-0031] wherein chip-to-chip connections couple respective ones of receiving in the third IC to the transmitting in the first IC and respective ones of the receiving in the first IC to the transmitting in the third IC [FIG. 4A, 0045 interposer die 170E is used to interconnect the four logic dice to each other, FIG. 4B, 0050 input contacts for receiving, output contact for transmitting, FIG. 4C, 0055pair of contact arrays, arrows in FIG. 7B indicate claimed chip-to-chip connections, 0073 used to route signals to and from each of the dice].
Thus, considering that Chen et al. teach Tx/Rx pairs for a chip on wafer substrate, a person having ordinary skill in the art to which the claimed invention pertains would have been motivated to combine these references such that the invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because a communication medium that enables high speed and high bandwidth transfer of data between the dice is desirable, otherwise the components of the circuit design that are in different dice may not be able to properly communicate with each other [0006], Martorell et al. use die-on-wafer for implementing an interposer to reduce the degradation in signal quality [0029].
As per claim 10, following from above, further comprising: a fourth IC disposed on the interposer [Chen et al. FIGS. 7 and 9 depict a fourth IC; Martorell et al. 0030 four], the fourth IC comprising a seventh row of TX PHYs parallel to a periphery of the fourth IC [column 7, lines 2-8 transmitting, column 9, lines 6-11 transmitting, column 10, lines 35-47 transmitting] and an eight row of RX PHYs parallel to the periphery of the fourth IC [column 7, lines 2-8 receiving, column 9, lines 6-11 receiving, column 10, lines 35-47 receiving], wherein the first, second, third, and fourth ICs are disposed in a 2x2 configuration [Chen et al. FIGS. 7 and 9 depict a 2x2 configuration; Martrell et al. 0031 two-by-two grid pattern], Martorell et al. teach arrays of input/output (receiving/transmitting) contacts [0030-0031, 0049-0050, 0055].
However, Chen et al. do not teach wherein the chip-to-chip connections couple respective ones of the RX PHYs in the fourth IC to the TX PHYs in the second IC and respective ones of the RX PHYs in the second IC to the TX PHYs in the fourth IC, and wherein the chip-to-chip connections couple respective ones of the RX PHYs in the fourth IC to the TX PHYs in the third IC and respective ones of the RX PHYs in the third IC to the TX PHYs in the fourth IC.
Martorell et al. teach a device comprising an interposer [0002, 0029-0031] wherein chip-to-chip connections couple respective ones of receiving in the fourth IC to the transmitting in the second IC and respective ones of the receiving in the second IC to the transmitting in the fourth IC, wherein the chip-to-chip connections couple respective ones of the receiving in the fourth IC to the transmitting in the third IC and respective ones of the receiving in the third IC to the transmitting in the fourth IC [FIG. 4A, 0045 interposer die 170E is used to interconnect the four logic dice to each other, FIG. 4B, 0050 input contacts for receiving, output contact for transmitting, FIG. 4C, 0055pair of contact arrays, arrows in FIG. 7B indicate claimed chip-to-chip connections, 0073 used to route signals to and from each of the dice].
Thus, considering that Chen et al. teach Tx/Rx pairs for a chip on wafer substrate, a person having ordinary skill in the art to which the claimed invention pertains would have been motivated to combine these references such that the invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because a communication medium that enables high speed and high bandwidth transfer of data between the dice is desirable, otherwise the components of the circuit design that are in different dice may not be able to properly communicate with each other [0006], Martorell et al. use die-on-wafer for implementing an interposer to reduce the degradation in signal quality [0029].
Conclusion
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/LEIGH M GARBOWSKI/ Primary Examiner, Art Unit 2851