DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. This office action is in response to the Amendment filed on June 17, 2026.
Claims 1, 7, and 14 are amended. No claims are canceled. No claims are added.
Applicant’s amendments to the specification submitted on June 17, 2026 are acknowledged and objections to the specification are withdrawn.
Response to Arguments
3. Applicant’s arguments, see pages 7-8, filed June 17, 2026, with respect to independent claims 1 and 7, have been fully considered and are persuasive.
Applicant asserts Tran does not disclose the use of multiplexors at all to route signals from digital-to-analog converters to rows of an array, and although Subramanian does disclose multiplexors, it does not disclose multiplexors to route signals from digital-to-analog converters to rows of an array such that "no two consecutive rows share a same multiplexor or wherein no two consecutive sectors of two or four rows each share the same multiplexor" as required by amended claims 1 and 7. Examiner agrees and therefore the rejections of claims 1 and 7 and their respective dependent claims have been withdrawn.
4. Applicant’s arguments, see pages 8-9, filed June 17, 2026, with respect to the rejection of claim 14 under 35 USC § 103, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Tran, et al (US 20180053560 A1).
Applicant asserts although Tran discloses source lines, it does not disclose "a circuit to couple respective ones of the i/2 source lines to a first voltage in response to a first enable signal when one or more rows coupled to the respective source line are selected during a read or verify operation and to a second voltage in response to a second enable signal when two rows coupled to the respective source line are unselected during a read or verify operation" as required by amended claim 14. Applicant further asserts although Do does disclose applying a first voltage on a source line when a cell is selected and a second voltage on the source line when the cell is unselected, it does not specifically disclose "a circuit to couple respective ones of the i/2 source lines to a first voltage in response to a first enable signal when one or more rows coupled to the respective source line are selected during a read or verify operation and to a second voltage in response to a second enable signal when two rows coupled to the respective source line are unselected during a read or verify operation." Examiner agrees on both parts and therefore the rejections of claim 14 and its dependent claims as set forth in the previous office action have been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Tran, et al (US 20180053560 A1).
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 7 each recite the limitation, “wherein no two consecutive rows share a same multiplexor or wherein no two consecutive sectors of two or four rows each share the same multiplexor.” It appears the limitation, “no two consecutive sectors of…four rows each share the same multiplexor,” is not taught anywhere in the specification and may not be taught in the drawings. Therefore, the meaning of the aforementioned limitation is unclear, as further explained in the following paragraphs. Claims 2-6 depend on claim 1; claims 8-13 depend on claim 7.
¶[0120] and FIG. 29 describe a case in which “a sector can comprise a pair of consecutive rows, and the rows of a sector can be accessed concurrently as no consecutive rows share the same multiplexor.”
¶[0122] and FIG. 30 describe a case in which “In one example, a sector comprises consecutive rows. In another example, a sector comprises four consecutive rows. In either case, all rows in a sector can be accessed concurrently as no group of two or four consecutive rows share the same multiplexor 3004.”
¶[0124] and FIG. 31 describe a case in which “the rows in a sector that is formed of two consecutive rows can be accessed concurrently as no two consecutive rows share the same multiplexor.”
Examiner believes Claims 1 and 7 may be intended to reflect the embodiment ¶[0122] and FIG. 30 as it most closely reflects the wording of the claims. Note, however, in FIG. 30, two consecutive sectors of four rows do share the same multiplexor (e.g., Rows 3006-1 and 3006-5 may be in adjacent sectors of four rows each, yet appear to share Multiplexor 3004-1).
Therefore, Examiner believes the aforementioned limitations contain typographical/copyist errors and may be intended to recite, “wherein no two consecutive rows share a same multiplexor or wherein no group of two or four consecutive rows in a sector each share the same multiplexor” (see the last line of ¶[0122]). However, this is substantively different from the aforementioned limitations as recited in the amended claims.
Note it is possible FIG. 29 may teach no two consecutive sectors of four rows each share the same multiplexor, but only provided the sector boundaries are chosen carefully. However, the sector boundaries do not appear to be identified in the specification or drawings.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claims 14-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tran, et al (US 20210280240 A1), hereinafter Tran, in view of Do, et al (US 20140269062 A1), hereinafter Do, and further in view of Tran, et al (US 20180053560 A1), hereinafter Tran ‘560.
Regarding independent claim 14, Tran teaches a system (Abstract; FIG. 10, 32; ¶[0035]) comprising:
a neural network array (Abstract; FIG. 10, VMM Array 33; ¶[0035]) of non-volatile memory cells (Abstract; FIG. 10; ¶[0035]) comprising i rows (e.g., FIG. 12, wherein the rows are coupled to word lines WL0..WL3, making i = 4), where i is a multiple of 2 (FIG. 12, each source line (SL0, SL1) is accompanied by two word lines (e.g., SL0 is “shared” by WL0 and WL1), and therefore the number of word lines must be a multiple of two and the number of rows is a multiple of two);
i/2 source lines, where respective ones of said source lines are shared by a sector comprising two of the i rows (¶[0024] teaches “source lines can be coupled to one row of memory cells or to two adjacent rows of memory cells. That is, source line terminals can be shared by adjacent rows of memory cells.” If source lines terminals are shared by adjacent rows of memory cells, there will be i/2 source lines.); and
a circuit (FIGS. 19A-19C, 1904, 1905, 1906; ¶[0125-0127]) to couple respective ones of the i/2 source lines (FIG. 15, SL0, SL1; ¶[0043]) to a first voltage when one or more rows coupled to the respective source line are selected during a read or verify operation (FIGS. 19A-19C; ¶[0125] teaches “exemplary dummy cells 1905 and 1906, which can serve as source line pull down cells” and “As an example, one end of dummy bit line switch 1904a connects to a low voltage level, such as ground, during a read operation”).
Tran does not teach a second voltage when the respective row of the array of non-volatile memory cells coupled to the source line are unselected during a read or verify operation.
Do teaches a second voltage when the respective row of the array of non-volatile memory cells coupled to the source line are unselected during a read or verify operation (Abstract teaches “placing a small positive voltage on the unselected source lines…during the read operation to suppress sub-threshold leakage and thereby improve read performance”; see also ¶[0066]).
Tran does not teach the first voltage is applied in response to a first enable signal and the second voltage is applied in response to a second enable signal.
Tran ‘560 teaches the first voltage is applied in response to a first enable signal and the second voltage is applied in response to a second enable signal (referencing FIG. 12, ¶[0073] teaches “source line decoder 1231 receives sector enable signal high voltage (SECEN_HV0) from high voltage level shift circuit 1211, its complement (SECEN_HV0_N), a voltage source line supply (VSLSUP), a low voltage source line supply (VSLSUP_LOW), sector enable signal (SECEN), and its complement (SECEN_N). Thus, the output SL0 of source line decoder 1230 can be at one of two different voltage levels: VSLSUP (high or normal voltage), or VSLSUP_LOW (low voltage).”).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Do into the method of Tran to include placing a small positive voltage on the unselected source lines during a read operation. The ordinary artisan would have been motivated to modify Tran in the above manner for the purpose of suppressing sub-threshold leakage, thereby improving read performance (Do, Abstract, ¶ [0066]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Tran ‘560 into the method of Tran to include a source line decoder circuit responsive to a plurality of enable signals. The ordinary artisan would have been motivated to modify Tran in the above manner for the purpose of applying the appropriate source line voltage for a given operating mode (Tran ‘560 ¶[0077]; see also Tables 1-3).
Regarding claim 15, Tran as modified by Do and Tran ‘560 teaches the limitations of claim 14.
Tran further teaches wherein the non-volatile memory cells are stacked-gate flash memory cells (FIG. 7; ¶[0022]).
Regarding claim 16, Tran as modified by Do and Tran ‘560 teaches the limitations of claim 14.
Tran further teaches wherein the non-volatile memory cells are split-gate flash memory cells (FIG. 2; ¶ [0009]).
Regarding claim 20, Tran as modified by Do and Tran ‘560 teaches the limitations of claim 14.
Tran further teaches i/2 erase gate lines, where respective ones of said i/2 erase gate lines are shared by a sector (The present application in ¶[0111] defines a sector as comprising two rows of cells in an array. Tran FIG. 12 shows one erase gate (coupled to erase gate lines EG0, EG1) for each “sector” of two of the “i” rows illustrated (e.g., EG0 is shared by the “sector” coupled to WL0 and WL1). Therefore, Tran teaches i/2 erase gates, where respective ones of said i/2 erase gate lines are shared by a sector.).
9. Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Tran, et al (US 20210280240 A1), hereinafter Tran, in view of Do, et al (US 20140269062 A1), hereinafter Do, further in view of Tran, et al (US 20180053560 A1), hereinafter Tran ‘560, and further in view of Subramanian, et al (US 20220391738 A1), hereinafter Subramanian.
Regarding claim 17, Tran as modified by Do and Tran ‘560 teaches the limitations of claim 14.
Tran further teaches j row registers (FIG. 24, shift registers SR 2401; ¶ [0148]); and
j digital-to-analog converters (FIG. 24, DAC 2402; ¶[0148]) to convert j sets of digital data (FIG. 24, IN[0:q]) received from the j row registers into j analog signals (FIG. 24 shows equal numbers (“j”) of SRs, DACs, sets of data, and analog signals (outputs of the DACs)).
Tran does not teach j multiplexors to route the respective j analog signals to a subset of the i rows in response to control signals, where j < i (note Tran teaches multiplexers, see e.g. FIG. 15, 1505, but these do not appear to be analogous to the multiplexers in view here (see FIG. 29, 2904, of the present application)).
Subramanian teaches multiplexors (FIG. 22C, 334) coupled to the outputs of digital-to-analog converters (FIG. 22C, 332) to route the respective analog signals to various signal paths (FIG. 22C, represented by circuits 322-1..322-K; ¶ [0112]) in response to control signals (¶ [0127]).
Tran as modified by Do, Tran ‘560, and Subramanian would add Subramanian’s multiplexers 334 to the output of each of Tran’s DACs 2402 as shown in Figure A. Because the multiplexer provides multiple outputs for each input, fewer DACs are required to route the respective analog signals to various signal paths (Subramanian ¶ [0032], [0112]). For example, if a 1:2 multiplexer were used at 334-1 (Subramanian FIG. 22C, K=2), the example of Figure A would illustrate j = i/2. Therefore, Tran as modified by Subramanian teaches j < i.
Therefore, Tran as modified by Do, Tran ‘560, and Subramanian teaches route the respective j analog signals to a subset of the i rows in response to control signals, where j < i.
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Subramanian into the method of Tran to include a multiplexer at the output of each digital-to-analog converter. The ordinary artisan would have been motivated to modify Tran in the above manner for the purpose of requiring fewer digital-to-analog converters to route the respective analog signal to various signal paths (Subramanian ¶[0032], [0112]).
Regarding claim 18, Tran as modified by Do, Tran ‘560, and Subramanian teaches the limitations of claim 17.
Tran as modified by Do, Tran ‘560, and Subramanian further teaches j = i/2 (Subramanian FIG. 22C, K=2, would result in a 1:2 multiplexer at 334-1, and the example of Figure A would illustrate j = i/2).
Regarding claim 19, Tran as modified by Do, Tran ‘560, and Subramanian teaches the limitations of claim 17.
Tran as modified by Do, Tran ‘560, and Subramanian further teaches j = i/4 (Subramanian FIG. 22C, K=4, would result in a 1:4 multiplexer at 334-1, and the example of Figure A would illustrate j = i/4, with four outputs instead of the two illustrated).
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Figure A: Tran as modified by Subramanian.
Allowable Subject Matter
10. Claims 1 and 7 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
11. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 1, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein no two consecutive rows share a same multiplexor. Claims 2-6 depend on claim 1.
Regarding claim 7, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein no two consecutive rows share a same multiplexor. Claims 8-13 depend on claim 7.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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