DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statements (IDS) submitted on April 17, 2023; September 27, 2023; March 18, 2025; December 1, 2025; and March 19, 2026, have been fully considered by the examiner.
Specification
3. Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
4. The abstract of the disclosure is objected to because it recites “are disclosed” in line 1, which can be implied.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claims 1-3, 5-10, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Tran, et al (US 20210280240 A1), hereinafter Tran, in view of Subramanian, et al (US 20220391738 A1), hereinafter Subramanian.
Regarding independent claim 1, Tran teaches a system (Abstract; FIG. 10, 32; ¶ [0035]) comprising:
a neural network array (Abstract; FIG. 10, VMM Array 33; ¶ [0035]) of non-volatile memory cells (Abstract; FIG. 10; ¶ [0035]) comprising i rows (e.g., FIG. 12, wherein the rows are coupled to word lines WL0..WL3, making i = 4), where i is a multiple of 2 (FIG. 12, each source line (SL0, SL1) is accompanied by two word lines (e.g., SL0 is “shared” by WL0 and WL1), and therefore the number of word lines must be a multiple of two and the number of rows is a multiple of two);
j row registers (FIG. 24, shift registers SR 2401; ¶ [0148]); and
j digital-to-analog converters (FIG. 24, DAC 2402; ¶[0148]) to convert j sets of digital data (FIG. 24, IN[0:q]) received from the j row registers into respective j analog signals (FIG. 24 shows equal numbers (“j”) of SRs, DACs, sets of data, and analog signals (outputs of the DACs)).
Tran does not teach j multiplexors to route the respective j analog signals to a subset of the i rows in response to control signals, where j < i (note Tran teaches multiplexers, see e.g. FIG. 15, 1504, but these do not appear to be analogous to the multiplexers in view here (believed to be FIG. 29, 2904, of the present application)).
Subramanian teaches multiplexors (FIG. 22C, 334) coupled to the outputs of digital-to-analog converters (FIG. 22C, 332) to route the respective analog signals to various signal paths (FIG. 22C, represented by circuits 322-1..322-K; ¶ [0112]) in response to control signals (¶ [0127]).
Tran as modified by Subramanian would add Subramanian’s multiplexers 334 to the output of each of Tran’s DACs 2402 as shown in Figure A, which follows. Because the multiplexer provides multiple outputs for each input, fewer DACs are required to route the respective analog signals to various signal paths (Subramanian ¶ [0032], [0112]). For example, if a 1:2 multiplexer were used at 334-1 (Subramanian FIG. 22C, K=2), the example of Figure A would illustrate j = i/2. Therefore, Tran as modified by Subramanian teaches j < i.
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Figure A: Tran as modified by Subramanian.
Therefore, Tran as modified by Subramanian teaches j multiplexors to route the respective j analog signals to a subset of the i rows in response to control signals, where j < i.
Regarding independent claim 7, Tran teaches a method (e.g., ¶ [0158-0164]) comprising:
converting, by j digital-to-analog converters (FIG. 24, DAC 2402; ¶[0148]), j sets of digital data (FIG. 24, IN[0:q]) received from j row registers (FIG. 24, shift registers SR 2401; ¶ [0148]) into j analog signals (FIG. 24 shows equal numbers (“j”) of SRs, DACs, sets of data, and analog signals (outputs of the DACs)).
Tran does not teach routing, by j multiplexors, the j analog signals to a subset of rows within i rows in a neural network array of non-volatile memory cells, where i is a multiple of 2 and j < i (note Tran teaches multiplexers, see e.g. FIG. 15, 1504, but these do not appear to be analogous to the multiplexers in view here (believed to be FIG. 29, 2904, of the present application)).
Subramanian teaches multiplexors (FIG. 22C, 334) coupled to the outputs of digital-to-analog converters (FIG. 22C, 332) to route the respective analog signals to various signal paths (FIG. 22C, represented by circuits 322-1..322-K; ¶ [0112]).
Tran as modified by Subramanian would add Subramanian’s multiplexers 334 to the output of each of Tran’s DACs 2402 as shown in Figure A. Because the multiplexer provides multiple outputs for each input, fewer DACs are required to route the respective analog signals to various signal paths (Subramanian ¶ [0032], [0112]). For example, if a 1:2 multiplexer were used at 334-1 (Subramanian FIG. 22C, K=2), the example of Figure A would illustrate j = i/2. Therefore, Tran as modified by Subramanian teaches j < i.
Therefore, Tran as modified by Subramanian teaches routing, by j multiplexors, the j analog signals to a subset of rows within i rows in a neural network array of non-volatile memory cells, where i is a multiple of 2 and j < i.
Regarding claims 1 and 7, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Subramanian into the method of Tran to include a multiplexer at the output of each digital-to-analog converter. The ordinary artisan would have been motivated to modify Tran in the above manner for the purpose of requiring fewer digital-to-analog converters to route the respective analog signal to various signal paths (Subramanian ¶ [0032], [0112]).
Regarding claim 2, Tran as modified by Subramanian teaches the limitations of claim 1.
Tran as modified by Subramanian further teaches j = i/2 (Subramanian FIG. 22C, K=2, would result in a 1:2 multiplexer at 334-1, and the example of Figure A would illustrate j = i/2).
Regarding claim 3, Tran as modified by Subramanian teaches the limitations of claim 1.
Tran as modified by Subramanian further teaches j = i/4 (Subramanian FIG. 22C, K=4, would result in a 1:4 multiplexer at 334-1, and the example of Figure A would illustrate j = i/4, with four outputs instead of the two illustrated).
Regarding claim 5, Tran as modified by Subramanian teaches the limitations of claim 1.
Tran further teaches wherein the non-volatile memory cells are stacked-gate flash memory cells (FIG. 7; ¶ [0022]).
Regarding claim 6, Tran as modified by Subramanian teaches the limitations of claim 1.
Tran further teaches wherein the non-volatile memory cells are split-gate flash memory cells (FIG. 2; ¶ [0009]).
Regarding claim 8, Tran as modified by Subramanian teaches the limitations of claim 7.
Tran as modified by Subramanian further teaches j = i/2 (Subramanian FIG. 22C, K=2, would result in a 1:2 multiplexer at 334-1, and the example of Figure A would illustrate j = i/2).
Regarding claim 9, Tran as modified by Subramanian teaches the limitations of claim 7.
Tran as modified by Subramanian further teaches j = i/4 (Subramanian FIG. 22C, K=4, would result in a 1:4 multiplexer at 334-1, and the example of Figure A would illustrate j = i/4, with four outputs instead of the two illustrated).
Regarding claim 10, Tran as modified by Subramanian teaches the limitations of claim 7.
Tran further teaches pulling a source line to a first voltage when one or more rows coupled to the source line are selected during a read or verify operation (FIGS. 19A-19C; ¶ [0125] teaches “exemplary dummy cells 1905 and 1906, which can serve as source line pull down cells” and “As an example, one end of dummy bit line switch 1904a connects to a low voltage level, such as ground, during a read operation”).
Regarding claim 12, Tran as modified by Subramanian teaches the limitations of claim 7.
Tran further teaches wherein the non-volatile memory cells are stacked-gate flash memory cells (FIG. 7; ¶ [0022]).
Regarding claim 13, Tran as modified by Subramanian teaches the limitations of claim 7.
Tran further teaches wherein the non-volatile memory cells are split-gate flash memory cells (FIG. 2; ¶ [0009]).
9. Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Tran, et al (US 20210280240 A1), hereinafter Tran, in view of Subramanian, et al (US 20220391738 A1), hereinafter Subramanian, and further in view of Do, et al (US 20140269062 A1), hereinafter Do.
Regarding claim 4, Tran as modified by Subramanian teaches the limitations of claim 1.
Tran further teaches a source line pull down circuitry to pull a source line of a respective row of the array of non-volatile memory cells to a first voltage when the respective row of the array of non-volatile memory cells coupled to the source line are selected during a read or verify operation (FIGS. 19A-19C; ¶ [0125] teaches “exemplary dummy cells 1905 and 1906, which can serve as source line pull down cells” and “As an example, one end of dummy bit line switch 1904a connects to a low voltage level, such as ground, during a read operation”).
Tran does not teach a second voltage when the respective row of the array of non-volatile memory cells coupled to the source line are unselected during a read or verify operation.
Do teaches a second voltage when the respective row of the array of non-volatile memory cells coupled to the source line are unselected during a read or verify operation (Abstract teaches “placing a small positive voltage on the unselected source lines…during the read operation to suppress sub-threshold leakage and thereby improve read performance”; see also ¶ [0066]).
Regarding claim 11, Tran as modified by Subramanian teaches the limitations of claim 10.
Tran does not teach pulling the source line to a second voltage when the one or more rows coupled to the source line are unselected during a read or verify operation.
Do teaches pulling the source line to a second voltage when the one or more rows coupled to the source line are unselected during a read or verify operation. (Abstract teaches “placing a small positive voltage on the unselected source lines…during the read operation to suppress sub-threshold leakage and thereby improve read performance”; see also ¶ [0066]).
Regarding claims 4 and 11, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Do into the method of Tran to include placing a small positive voltage on the unselected source lines during a read operation. The ordinary artisan would have been motivated to modify Tran in the above manner for the purpose of suppressing sub-threshold leakage, thereby improving read performance (Do, Abstract, ¶ [0066]).
10. Claims 14-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tran, et al (US 20210280240 A1), hereinafter Tran, in view of Do, et al (US 20140269062 A1), hereinafter Do.
Regarding independent claim 14, Tran teaches a system (Abstract; FIG. 10, 32; ¶ [0035]) comprising:
a neural network array (Abstract; FIG. 10, VMM Array 33; ¶ [0035]) of non-volatile memory cells (Abstract; FIG. 10; ¶ [0035]) comprising i rows (e.g., FIG. 12, wherein the rows are coupled to word lines WL0..WL3, making i = 4), where i is a multiple of 2 (FIG. 12, each source line (SL0, SL1) is accompanied by two word lines (e.g., SL0 is “shared” by WL0 and WL1), and therefore the number of word lines must be a multiple of two and the number of rows is a multiple of two);
i/2 source lines, where respective ones of said source lines are shared by a sector comprising two of the i rows (¶ [0024] teaches “source lines can be coupled to one row of memory cells or to two adjacent rows of memory cells. That is, source line terminals can be shared by adjacent rows of memory cells.” If source lines terminals are shared by adjacent rows of memory cells, there will be i/2 source lines.); and
a circuit (FIGS. 19A-19C, 1904, 1905, 1906; ¶ [0125-0127]) to couple respective ones of the i/2 source lines (FIG. 15, SL0, SL1; ¶ [0043]) to a first voltage when one or more rows coupled to the respective source line are selected during a read or verify operation (FIGS. 19A-19C; ¶ [0125] teaches “exemplary dummy cells 1905 and 1906, which can serve as source line pull down cells” and “As an example, one end of dummy bit line switch 1904a connects to a low voltage level, such as ground, during a read operation”).
Tran does not teach a second voltage when the respective row of the array of non-volatile memory cells coupled to the source line are unselected during a read or verify operation.
Do teaches a second voltage when the respective row of the array of non-volatile memory cells coupled to the source line are unselected during a read or verify operation (Abstract teaches “placing a small positive voltage on the unselected source lines…during the read operation to suppress sub-threshold leakage and thereby improve read performance”; see also ¶ [0066]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Do into the method of Tran to include placing a small positive voltage on the unselected source lines during a read operation. The ordinary artisan would have been motivated to modify Tran in the above manner for the purpose of suppressing sub-threshold leakage, thereby improving read performance (Do, Abstract, ¶ [0066]).
Regarding claim 15, Tran as modified by Do teaches the limitations of claim 14.
Tran further teaches wherein the non-volatile memory cells are stacked-gate flash memory cells (FIG. 7; ¶ [0022]).
Regarding claim 16, Tran as modified by Do teaches the limitations of claim 14.
Tran further teaches wherein the non-volatile memory cells are split-gate flash memory cells (FIG. 2; ¶ [0009]).
Regarding claim 20, Tran as modified by Do teaches the limitations of claim 14.
Tran further teaches i/2 erase gate lines, where respective ones of said i/2 erase gate lines are shared by a sector (The present application in ¶ [0111] defines a sector as comprising two rows of cells in an array. Tran FIG. 12 shows one erase gate (coupled to erase gate lines EG0, EG1) for each “sector” of two of the “i” rows illustrated (e.g., EG0 is shared by the “sector” coupled to WL0 and WL1). Therefore, Tran teaches i/2 erase gates, where respective ones of said i/2 erase gate lines are shared by a sector.).
11. Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Tran, et al (US 20210280240 A1), hereinafter Tran, in view of Do, et al (US 20140269062 A1), hereinafter Do, and further in view of Subramanian, et al (US 20220391738 A1), hereinafter Subramanian.
Regarding claim 17, Tran as modified by Do teaches the limitations of claim 14.
Tran further teaches j row registers (FIG. 24, shift registers SR 2401; ¶ [0148]); and
j digital-to-analog converters (FIG. 24, DAC 2402; ¶[0148]) to convert j sets of digital data (FIG. 24, IN[0:q]) received from the j row registers into j analog signals (FIG. 24 shows equal numbers (“j”) of SRs, DACs, sets of data, and analog signals (outputs of the DACs)).
Tran does not teach j multiplexors to route the respective j analog signals to a subset of the i rows in response to control signals, where j < i (note Tran teaches multiplexers, see e.g. FIG. 15, 1505, but these do not appear to be analogous to the multiplexers in view here (see FIG. 29, 2904, of the present application)).
Subramanian teaches multiplexors (FIG. 22C, 334) coupled to the outputs of digital-to-analog converters (FIG. 22C, 332) to route the respective analog signals to various signal paths (FIG. 22C, represented by circuits 322-1..322-K; ¶ [0112]) in response to control signals (¶ [0127]).
Tran as modified by Do and Subramanian would add Subramanian’s multiplexers 334 to the output of each of Tran’s DACs 2402 as shown in Figure A. Because the multiplexer provides multiple outputs for each input, fewer DACs are required to route the respective analog signals to various signal paths (Subramanian ¶ [0032], [0112]). For example, if a 1:2 multiplexer were used at 334-1 (Subramanian FIG. 22C, K=2), the example of Figure A would illustrate j = i/2. Therefore, Tran as modified by Subramanian teaches j < i.
Therefore, Tran as modified by Do and Subramanian teaches route the respective j analog signals to a subset of the i rows in response to control signals, where j < i.
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Subramanian into the method of Tran to include a multiplexer at the output of each digital-to-analog converter. The ordinary artisan would have been motivated to modify Tran in the above manner for the purpose of requiring fewer digital-to-analog converters to route the respective analog signal to various signal paths (Subramanian ¶ [0032], [0112]).
Regarding claim 18, Tran as modified by Do and Subramanian teaches the limitations of claim 17.
Tran as modified by Do and Subramanian further teaches j = i/2 (Subramanian FIG. 22C, K=2, would result in a 1:2 multiplexer at 334-1, and the example of Figure A would illustrate j = i/2).
Regarding claim 19, Tran as modified by Do and Subramanian teaches the limitations of claim 17.
Tran as modified by Do and Subramanian further teaches j = i/4 (Subramanian FIG. 22C, K=4, would result in a 1:4 multiplexer at 334-1, and the example of Figure A would illustrate j = i/4, with four outputs instead of the two illustrated).
Conclusion
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827