DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-13, and 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu et al. (US 20190287932 A1, hereinafter Hu)
With regards to claim 1, Hu discloses a semiconductor device (FIGS. 4A-4C and 5) comprising:
a substrate (substrate 112) comprising a bonding area (area inside device area 218) and a pad area; (area outside device area 218, see FIGS. 4A-4C) )
a first inter-metal dielectric (IMD) layer (dielectric of layer 226, dielectric 238, and bottom half of bond dielectric 240) on the substrate; (See FIG. 4C)
a metal interconnection (at least bond pad vias 244 and metal lines 227-229) in the first IMD layer; (see FIG. 4b)
a second IMD layer (top half of bond dielectric 240) on the first IMD layer; (See FIG. 4b)
a first bonding pad (at least one of the bond pad pairs 142/242 in the device area 218) on the bonding area and connected to the metal interconnection, and wherein the first bonding pad comprise a first bottom portion (bond pad 142) connecting the metal interconnection and a first top portion (bond pad 242) on the first bottom portion, wherein a width of the first bottom portion is less than a width of the first top portion; (See FIG. 5, wherein the bottom of 142 has less width than the bottom of pad 242) and
wherein a bottom surface of the first top portion directly contacts a top surface of the second IMD layer; (see Annotated FIG. 4b, where a top surface of the dielectric 240 directly contacts the pad 242, see also Response to Arguments) and
a second bonding pad (at least one of the bond pad pairs 142/242 outside the device area 218) on the pad area and connected to the metal interconnection; (see FIGS. 4a and 4b, showing the placements and connections) and
a third bonding pad (via 244) on the bonding area and connected to the first bonding pad, wherein the third bonding pad directly contacts the first bonding pad. (See FIG. 4b, showing the direct contact, see also Response to Arguments)
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With regards to claim 2, Hu discloses the semiconductor device of claim 1, wherein the first bonding pad comprise:
a first bottom portion (portion of pad 242 connected to via 244) connecting the metal interconnection; and
a first top portion (portion of pad 242 opposed to the bottom portion) on the first bottom portion.
With regards to claim 3, Hu discloses the semiconductor device of claim 2, wherein the second bonding pad comprise:
a second bottom portion (bond pad 142) connecting the metal interconnection; and
a second top portion (bond pad 242) on the second bottom portion.
With regards to claim 4, Hu discloses the semiconductor device of claim 3, wherein top surfaces of the first top portion and the second top portion are coplanar. (See FIG. 4b, showing the coplanarity)
With regards to claim 5, Hu discloses the semiconductor device of claim 3, wherein the second IMD layer around the first bottom portion and the second bottom portion, (See FIG. 4b, where the layer 240 is generally near (i.e. around) the first and second bottom portions) and further comprising:
a third IMD layer (dielectric 140) on the second IMD layer and around the first top portion and the second top portion. (see FIG. 5)
With regards to claim 7, Hu discloses the semiconductor device of claim 5, wherein the third bonding pad comprises:
a third bottom portion (bond pad 142) connecting the first top portion of the first bonding pad; and
a third top portion (bond pad 242) on the third bottom portion. (see FIG. 4b)
With regards to claim 9, Hu discloses the semiconductor device of claim 1, wherein the first bonding pad and the second bonding pad comprise same material. (See FIG. 4a, showing the materials being the same)
With regards to claim 10, Hu discloses the semiconductor device of claim 1, wherein the metal interconnection extends from the bonding area to the pad area. (See FIG. 4b, showing the extension)
With regards to claim 11, Hu discloses a semiconductor device, (FIGS. 4A-4C and 5) comprising:
a circuit area (area comprising device area 218) defined on a substrate; (substrate 222)
a bonding area (area outside device area 218 comprising up to ring structure 234) around the circuit area;
a pad area (area comprising ring 232) around the bonding area; and
a first bonding pad (pair of pads 142/242 and left row of pads 230) and a second bonding pad (via 244) on the bonding area, wherein the first bonding pad and the second bonding pad comprise different shapes in a top view, (see FIG. 4c, where the pad 242 is circular and the second bonding pad 244 is conical)
and wherein the second bonding pad directly contacts the first bonding pad, (see FIG. 4b, showing the direct contact, see also Response to Arguments) and disposed above the first bonding pad, and wherein the first bonding pad comprise a first bottom portion (bond pad 142) connecting the metal interconnection and a first top portion (bond pad 242) on the first bottom portion, wherein a width of the first bottom portion is less than a width of the first top portion; (See FIG. 5, wherein the bottom of 142 has less width than the bottom of pad 242) and
wherein a bottom surface of the first top portion directly contacts a top surface of the second IMD layer; (see Annotated FIG. 4b, where a top surface of the dielectric 240 directly contacts the pad 242, see also Response to Arguments)
With regards to claim 12, Hu discloses the semiconductor device of claim 11, further comprising a sub-bonding area (area comprising at least interconnects 244 and 227-229) on the bonding area, wherein the first bonding pad and the second bonding pad are on the sub-bonding area. (see FIG. 4b)
With regards to claim 13, Hu discloses the semiconductor device of claim 12, further comprising a third bonding pad (right half of pads 230) on the pad area.
With regards to claim 17, Hu discloses the semiconductor device of claim 11, wherein the first bonding pad and the second bonding pad are on different levels. (see FIG. 4b, showing the different levels of 242 and 244)
With regards to claim 18, Hu discloses the semiconductor device of claim 11, wherein the first bonding pad comprises a square in a top view. (see FIG. 4C, showing the square shape of at least 230)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8, 14-16, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 20190287932 A1, hereinafter Hu)
With regards to claim 8, Hu discloses the semiconductor device of claim 5.
However, Hu does not explicitly teach wherein the first bonding pad and the third bonding pad comprise different materials.
It should be noted that one of ordinary skill would understand that substituting one metal material for another would yield predictable results, such as conduction from a different metal material.
Therefore, it would have been obvious to one of ordinary skill to modify the device to have multiple different metals for conduction.
With regards to claim 14, Hu discloses the semiconductor device of claim 13.
However, Hu does not explicitly teach wherein a distance between an edge of the sub-bonding area and an edge of the third bonding pad is between 0-8 microns.
It should be noted that the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (See MPEP 2144.04 IV A. Changes in Size/Proportion) In the instant case, the current device would not perform differently with the relative dimensions than the prior art device, and thus is not patentably distinct.
Therefore, it would have been obvious to one of ordinary skill in the art to modify the device of Hu to have the dimensions as recited in the above recited claim.
With regards to claim 15, Hu discloses the semiconductor device of claim 11.
However, Hu does not explicitly teach wherein a distance between an edge of the sub-bonding area and the circuit area is between 0-6 microns.
It should be noted that the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (See MPEP 2144.04 IV A. Changes in Size/Proportion) In the instant case, the current device would not perform differently with the relative dimensions than the prior art device, and thus is not patentably distinct.
Therefore, it would have been obvious to one of ordinary skill in the art to modify the device of Hu to have the dimensions as recited in the above recited claim.
With regards to claim 16, Hu discloses the semiconductor device of claim 11.
However, Hu does not explicitly teach wherein a distance between an edge of the first bonding pad and an edge of the second bonding pad is between 0-6 microns.
It should be noted that the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (See MPEP 2144.04 IV A. Changes in Size/Proportion) In the instant case, the current device would not perform differently with the relative dimensions than the prior art device, and thus is not patentably distinct.
Therefore, it would have been obvious to one of ordinary skill in the art to modify the device of Hu to have the dimensions as recited in the above recited claim.
With regards to claim 19, Hu discloses the semiconductor device of claim 11.
However, Hu does not explicitly teach wherein the second bonding pad comprises a hexagon in a top view.
It should be noted that the court held that the configuration of the claimed [device] was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed [device] was significant.). (See MPEP 2144.04 IV B. Changes in shape) In the instant case, the current device would not perform differently with the relative dimensions than the prior art device, and thus is not patentably distinct.
Therefore, it would have been obvious to one of ordinary skill in the art to modify the device of Wu to have the shape as recited in the above recited claim.
Response to Arguments
Applicant's arguments filed 12/17/2025 have been fully considered but they are not persuasive.
Examiner notes that, as shown in Annotated FIG. 4b, the bottom surface of the bond pad 242 directly contacts a top surface of the top portion of the bond dielectric 240 (i.e. second IMD layer), and thus meets the limitations of claims 1 and 11. Therefore, claims 1 and 11 are rejected, and claims 3-6, 8-10, and 12-19 are rejected for at least their dependencies.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. KIM et al. (US 20210273039 A1) – dislocations in the dielectric layers
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812