Prosecution Insights
Last updated: May 28, 2026
Application No. 18/136,321

COMPILE TIME LOGIC FOR DETECTING AND RESOLVING MEMORY LAYOUT CONFLICTS

Non-Final OA §112
Filed
Apr 18, 2023
Priority
Sep 24, 2020 — continuation of 11/645,057
Examiner
PARIHAR, SUCHIN
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sambanova Systems Inc.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
1015 granted / 1157 resolved
+19.7% vs TC avg
Moderate +9% lift
Without
With
+8.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
19 currently pending
Career history
1179
Total Applications
across all art units

Statute-Specific Performance

§101
3.2%
-36.8% vs TC avg
§103
21.2%
-18.8% vs TC avg
§102
71.1%
+31.1% vs TC avg
§112
1.7%
-38.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1157 resolved cases

Office Action

§112
DETAILED ACTION 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 2. This Non-Final office action is in response to application 18/136,321, application filed on 04/18/2023. Claims 1-20 are currently pending in this application. Information Disclosure Statement 3. The information disclosure statement (IDS) submitted on 02/06/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 112 4. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 5. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural/functional elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: the processor(s)/machine responsible for processing the dataflow graph to carry out the functions/steps of the invention. More specifically, with respect to independent claim 1 lines 5-6, it is Examiner’s position that the recited “compile time logic having access to the memory” requires a relationship to a processor/machine in order to “process the dataflow graph. However, a processor/machine is absent in this limitation. Examiner suggests amending said limitation to read, or example, “compile time logic using a processor having access to the memory and configured to process the dataflow graph to …”. Further, with respect to independent claims 19 and 20 (line 5 and line 6, respectively), it is Examiner’s position that the recited “processing the dataflow graph” requires a relationship to a processor/machine in order to carry out the further recited functions of the invention. However, a processor/machine is absent in this limitation. Examiner suggests amending said limitation to read, or example, “processing the dataflow graph, using a processor, to ….”. Since the dependent claims also recite processing functions, this rejection carries through to the dependent claims, requiring similar correction of the dependent claims. Examiner suggests that Applicant consider amending the claims in order to clarify the language in order to overcome this 112 rejection. Allowable Subject Matter 6. Claims 1-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action, for the following reason(s): 7. With respect to claims 1-20, the prior art made of record fails to teach the combination of steps recited in independent claims 1, 19 and 20, including the following particular combination of steps as recited in claim 1 and similarly recited in claim 19 and 20, as follows: wherein each of the memory layouts includes a vector dimension and at least one of a vector ordering and a data alignment; detect memory layout conflicts when the expected consumer memory layouts are different from corresponding ones of the expected producer memory layouts and/or when the expected consumer memory layouts are different from corresponding ones of the current memory layouts; and resolve the memory layout conflicts by modifying the dataflow graph to cause the expected consumer memory layouts to match the corresponding ones of the expected producer memory layouts and/or to cause the expected consumer memory layouts to match the corresponding ones of the current memory layouts. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUCHIN PARIHAR/ Primary Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

Apr 18, 2023
Application Filed
Feb 03, 2026
Non-Final Rejection mailed — §112
May 04, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
96%
With Interview (+8.8%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1157 resolved cases by this examiner. Grant probability derived from career allowance rate.

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