DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 7, 8, 10, 12, 13, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsurusaki et al. US 2011/0093827 A1 (“Tsurusaki”).
As to claim 1, Tsurusaki discloses a method for logic synthesis, comprising:
receiving a logic design including a representation of a plurality of registers and ports (Figures 2 or 29A or Paragraphs 56-57 – e.g., a tentative layout or other initial design, including flip-flops or registers, and connections or nets);
detecting, by a processing device, one or more registers or ports of the plurality of registers and ports having a constant logic cone, opposite logic cones, or equal logic cones (Figures 17-18 or Paragraphs 92-96 – e.g., merging is performed according to a cost function according to the interconnections between nodes) by analyzing logic across a hierarchy boundary identified for the logic synthesis (Figure 2 or Paragraphs 60-61 – e.g., node selection/merging across node/group boundaries); and
generating a netlist by modifying the logic based on the detection (Figures 2 or 29A – e.g., manipulation of the tentative layout or other initial design, see below).
Tsurusaki discloses many of the elements of claim 1, including the circuit analysis and design details of the claims. Tsurusaki teaches working with a netlist as an initial output and organizing and designing the layout, but does not explicitly teach the generation of an additional netlist. However, Tsurusaki mentions netlist management with a hierarchy block (Paragraph 22), as well as hierarchical layout and optimization according to cost functions which are calculated from hierarchy of the design (Figures 2 or 29A or Paragraphs 56-57 or 65-69). It would have been obvious to one having ordinary skill in the art at the time the invention was made to update the managed netlist and/or consider the intermediate versions of the design created during trace and merge a “generated netlist”, because the netlist of Tsurusaki is managed and/or arranged differently as the design process progresses.
As to claim 7, Tsurusaki discloses the method of claim 1. Tsurusaki further discloses performing a verification process to identify whether the modification of the logic is acceptable based on the detection of the one or more registers or ports (Figures 17-18 or Paragraphs 92-96 – e.g., merging performed according to a cost function).
As to claim 8, Tsurusaki discloses the method of claim 1. Tsurusaki further discloses performing logic reductions in parallel based on boundaries associated with registers or ports (Figures 2 or 29A or Paragraphs 59-61).
As to claim 10, Tsurusaki discloses the method of claim 1. Tsurusaki further discloses wherein detecting the registers or ports having the equal logic cones includes detecting whether logic cones at inputs of registers or ports are equal (Figures 17-18 or Paragraphs 92-96 – e.g., necessary in a cost function used to perform merges according to the interconnections between nodes).
As to claim 12, Tsurusaki discloses the method of claim 1. Tsurusaki further discloses wherein detecting the one or more registers or ports includes detecting constant, equal, or opposite registers or ports for a plurality of circuit design portions in parallel (Figures 2 or 29A or Paragraphs 59-61).
Claims 13, 19, and 20 recite elements similar to claims 1 and 7, and are rejected for the same reasons.
Allowable Subject Matter
Claims 2-6, 9, 11, and 14-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not teach or suggest a method or apparatus having the combination of steps or elements of the claims including, among other elements, the detection criteria of the claims used for register and port analysis, in combination with the design and generation details of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYCE M AISAKA whose telephone number is (571)270-5808. The examiner can normally be reached M-F: 6:30AM-5:00PM PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571)272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYCE M AISAKA/Primary Examiner, Art Unit 2851