DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of Species I (Claims 1-20) in the reply filed on January 15th, 2026 is acknowledged.
Claim Objections
Claims 2, 7, 8, 12, 14, and 16 are objected to because of the following informalities:
Claim 2 recites limitation “the second contacts” in line 1 which refers back to “a plurality of second contacts” in line 10 of claim 1 and should be amended to “the plurality of second contacts” for avoiding confusion. Appropriate correction is required.
Claim 7 recites limitation “the second contacts” in line 4 which refers back to “a plurality of second contacts” in line 10 of claim 1 and should be amended to “the plurality of second contacts” for avoiding confusion. Appropriate correction is required.
Claim 8 recites limitation “the second contacts” in lines 1 and 2 which refers back to “a plurality of second contacts” in line 10 of claim 1 and should be amended to “the plurality of second contacts” for avoiding confusion. Appropriate correction is required.
Claim 12 recites limitation “the second contacts” in line 1 which refers back to “a plurality of second contacts” in line 10 of claim 1 and should be amended to “the plurality of second contacts” for avoiding confusion. Appropriate correction is required.
Claim 14 recites limitation “the second contacts” in line 1 which refers back to “a plurality of second contacts” in line 10 of claim 1 and should be amended to “the plurality of second contacts” for avoiding confusion. Appropriate correction is required.
Claim 16 recites limitation “the third contacts” in line 1 which refers back to “a plurality of third contacts” in line 1 and should be amended to “the plurality of third contacts” for avoiding confusion. Appropriate correction is required.
Claim 16 recites limitation “the second contacts and the third contacts” in line 5 which refers back to “a plurality of second contacts” in line 10 of claim 1 and “a plurality of third contacts” in line 1 of claim 16 and should be amended to “the plurality of second contacts and the plurality of third contacts” for avoiding confusion. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 8-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 8 recites “the second contacts are spaced in the lateral direction from the sidewall of the first trench by a first gap, and the second contacts are spaced in the lateral direction from the sidewall of the second trench by a second gap” which being described as doped regions 26 being spaced from the sidewall of each trench 28 in lateral direction as shown in Fig. 5 of Applicant’s specification. However, claim 7 recites “wherein the second contacts are disposed in a lateral direction between the sidewall of the first trench and the sidewall of the second trench” for reciting the doped regions 26 are also disposed in the same lateral direction which conflict with Applicant’s specification having the doped regions 26 being disposed in the vertical direction. Therefore, the above limitation of claim 8 conflicts applicant’s disclosure.
Claim 9 is rejected for being depended on claim 8 and having the above issue incorporating into the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sampath et al. (Pub. No.: US 2024/0234507 A1), hereinafter as Sampath.
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Regarding claim 1, Sampath discloses a structure for a field-effect transistor in Figs. 8A-8D, the structure comprising: a semiconductor substrate (semiconductor layer 106) including a top surface (top surface of regions 174 and source regions 160) and a first trench (a trench 180 as illustrated in annotated Fig. 8A above), the semiconductor substrate comprising a wide bandgap semiconductor material (silicon carbide) (see Fig. 8A and [0078], [0087], [0090]); a first gate electrode (gate 184) disposed in the first trench (see annotated Fig. 8A above, Fig. 8B and [0079-0080]); a first doped region (bottom shielding structure 140a) disposed beneath the first trench (see Figs. 8B and [0107]); a second doped region (P-wells 170) disposed in a vertical direction between the first doped region and the top surface (between bottom shielding structure 140a and the top surface of semiconductor layer 106) (see Figs. 8A-8B and [0078], [0106]); a first contact (combination of a region 174, a portion of 140c and a shielding structure 240 as illustrated in annotated Fig. 8A above and in Fig. 8B) coupled to the first doped region (bottom shielding structure 140a), the first contact extending in the semiconductor substrate from the top surface to a first depth (first depth being defined at the bottom surface of bottom shielding structure 140a) that adjoins the first doped region (shielding structure 240 adjoins the bottom surface of bottom shielding structure 140a) (see Fig. 8B and [0106-0107]); and a plurality of second contacts (some regions 174 as illustrated in annotated Fig. 8A above that not overlapping with shielding structure 240) coupled to the second doped region, the second contacts extending in the semiconductor substrate from the top surface to a second depth (second depth being defined at the bottom surface of the illustrated regions 174) that adjoins the second doped region (the bottom surface of illustrated regions 174 adjoins the top surface of P-well 170), and the second depth less than the first depth (the bottom surface of the illustrated regions 174 is shallower than the bottom surface of bottom shielding structure 140a) (see Fig. 8C and [0078]).
Regarding claim 2, Sampath discloses the structure of claim 1, wherein the first contact (combination of a region 174, a portion of 140c and a shielding structure 240) and the second contacts (illustrated regions 174) have a first conductivity type (p-type) (see annotated Fig. 8A above, 8B-8C and [0076], [0085-0087]).
Regarding claim 3, Sampath discloses the structure of claim 2 wherein the first doped region (shield region 140a) and the second doped region (P-wells 170) have the first conductivity type (see [0078]).
Regarding claim 4, Sampath discloses the structure of claim 3 further comprising: a third doped region (source region 160) disposed in the vertical direction between the second doped region and the top surface, the third doped region having a second conductivity type (n-type) opposite to the first conductivity type (see Figs. 8B-8D and [0080]).
Regarding claim 5, Sampath discloses the structure of claim 4 wherein the semiconductor substrate has the second conductivity type (n-type conductivity of drift region 120 and substrate 110), the semiconductor substrate includes a drift region (drift region 120)and a drain (substrate 110) with different dopant concentrations (heavily-doped vs moderately-doped), the drift region is disposed in the vertical direction between the drain and the second doped region, and the drift region is disposed in the vertical direction between the drain and the third doped region (between substrate 110 and source 160) (see Fig. 2A, 8A and [0078]).
Regarding claim 6, Sampath discloses the structure of claim 1 wherein the wide bandgap semiconductor material comprises silicon carbide (see [0078]).
Regarding claim 7, Sampath discloses the structure of claim 1 wherein the semiconductor substrate includes a second trench (another trench 180 as illustrated in annotated Fig. 8A above), the first trench has a sidewall (sidewall of the illustrated first trench 180), the second trench has a sidewall (sidewall of the illustrated second trench 180), and further comprising: a second gate electrode (gate electrode 184) in the second trench, wherein the second contacts are disposed in a lateral direction (y-direction) between the sidewall of the first trench and the sidewall of the second trench (see annotated Fig. 8A above, Figs. 8B-8C).
Regarding claim 8, Sampath discloses the structure of claim 7 wherein the second contacts are spaced in the lateral direction from the sidewall of the first trench by a first gap (gap between one region 174 and sidewall of first trench 180 in Fig. 8C), and the second contacts are spaced in the lateral direction from the sidewall of the second trench by a second gap (gap between another region 174 and sidewall of second trench 180) (see annotated Fig. 8A, Fig. 8B-8C).
Regarding claim 9, Sampath discloses the structure of claim 8 wherein the first trench and the second trench each extend through the second doped region (extending through P-wells 170) (see annotated Fig. 8A above, Figs. 8B-8D).
Regarding claim 10, Sampath discloses the structure of claim 9 wherein the first gap includes a first portion of the second doped region (an upper surface of p-wells 170), and the second gap includes a second portion of the second doped region (another upper surface of p-wells 170) (see annotated Fig. 8A above, Figs. 8B-8D).
Regarding claim 11, Sampath discloses the structure of claim 7 further comprising: a third doped region (drift region 120) disposed beneath the second trench, wherein the first contact adjoins the third doped region (see Fig. 8B and [0078]).
Regarding claim 12, Sampath discloses the structure of claim 7 wherein the second contacts are arranged in a row that extends parallel to a length of the first trench and a length of the second trench (see annotated Fig. 8A above).
Regarding claim 13, Sampath discloses the structure of claim 1 further comprising: a third contact (combination of a region 174, a portion of 140c and a shielding structure 240 as illustrated in annotated Fig. 8A above and in Fig. 8B) coupled to the first doped region, the third contact extending in the semiconductor substrate from the top surface to the first depth, wherein the first contact is spaced along a length of the first trench from the third contact by a first spacing (illustrated first spacing) (see annotated Fig. 8A above and Fig. 8B).
Regarding claim 14, Sampath discloses the structure of claim 13 wherein the second contacts are spaced along the length of the first trench by a second spacing (illustrated second spacing), and the first spacing is greater than the second spacing (see annotated Fig. 8A above and Fig. 8B).
Regarding claim 15, Sampath discloses the structure of claim 14 wherein the first spacing is 2 times to 20 times greater than the second spacing (more than 2 times) (see annotated Fig. 8A above).
Regarding claim 16, Sampath discloses the structure of claim 1 further comprising: a plurality of third contacts (plurality of illustrated regions 174) coupled to the second doped region (p-wells 170), the third contacts extending in the semiconductor substrate from the top surface to the second depth (bottom surface of regions 174), wherein the first gate electrode and the first trench are disposed in a lateral direction between the second contacts and the third contacts (illustrated 1st trench 184 in Annotated Fig. 8A below).
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Regarding claim 17, Sampath discloses the structure of claim 1 wherein the first trench extends through the second doped region (see Fig. 8B).
Regarding claim 18, Sampath discloses the structure of claim 1 wherein the first trench includes sidewalls and a bottom between the sidewalls (trench 180 has bottom and sidewalls), the first doped region is disposed adjacent to the bottom of the first trench, and the bottom of the first trench is positioned in the vertical direction between the first depth (bottom surface of shielding region 140a) and the second depth (bottom surface of region 174) (see Fig. 8B).
Regarding claim 19, Sampath discloses the structure of claim 18 wherein the first trench has a first width dimension at the bottom (the width at the bottom of trench 180), and the second doped region has a second width dimension (claim not defining how the second width dimension being measured) that is substantially equal to the first width dimension (a dimension can be chosen from p-well 170 to the same with the width at the bottom of the trench 180) (see Fig. 8B).
Regarding claim 20, Sampath discloses a method of forming a structure for a field-effect transistor in Figs. 8A-8D, the method comprising: forming a trench (a trench 180 as illustrated in annotated Fig. 8A above) in a semiconductor substrate (semiconductor layer 106), wherein the semiconductor substrate including a top surface (top surface of regions 174 and source regions 160), and the semiconductor substrate comprising a wide bandgap semiconductor material (silicon carbide) (see Fig. 8A and [0078], [0087], [0090]); forming a first doped region (bottom shielding structure 140a) disposed beneath the trench (see Figs. 8B and [0107]); forming a first gate electrode (gate 184) disposed in the trench (see annotated Fig. 8A above, Fig. 8B and [0079-0080]); forming a second doped region (P-wells 170) disposed in a vertical direction between the first doped region and the top surface (between bottom shielding structure 140a and the top surface of semiconductor layer 106) (see Figs. 8A-8B and [0078], [0106]); forming a first contact (combination of a region 174, a portion of 140c and a shielding structure 240 as illustrated in annotated Fig. 8A above and in Fig. 8B) coupled to the first doped region (bottom shielding structure 140a), the first contact extending in the semiconductor substrate from the top surface to a first depth (first depth being defined at the bottom surface of bottom shielding structure 140a) that adjoins the first doped region (shielding structure 240 adjoins the bottom surface of bottom shielding structure 140a) (see Fig. 8B and [0106-0107]); and forming a plurality of second contacts (some regions 174 as illustrated in annotated Fig. 8A above that not overlapping with shielding structure 240) coupled to the second doped region, the second contacts extending in the semiconductor substrate from the top surface to a second depth (second depth being defined at the bottom surface of the illustrated regions 174) that adjoins the second doped region (the bottom surface of illustrated regions 174 adjoins the top surface of P-well 170), and the second depth less than the first depth (the bottom surface of the illustrated regions 174 is shallower than the bottom surface of bottom shielding structure 140a) (see Fig. 8C and [0078]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818