Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
RCE, received 12/5/2025, has been entered.
Claims 1, 3 and 5-9 are presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, 5, 7 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato (US Pub. No. 2011/0084379 A1).
As to claim 1, Sato discloses an electronic packaging structure (fig 6, structure 2), comprising:
one or more chips (30, 20), a substrate (10), and a heat sink cover (50);
wherein the one or more chips (30, 20) are mounted on the substrate (10), wherein the one or more chips comprise at least one high-power-density chip (20; [0038]);
wherein the heat sink cover (50) includes a side supporting part (51) and a top cover (50), wherein a bottom of the side supporting part (51) is bonded to the substrate (10) and the side supporting part (51) surrounds the one or more chips (30, 20);
wherein the top cover (50) is disposed above the one or more chips (20, 30) and supported by the side supporting part (51);
wherein a first window (see annotated figs below; opening in 50c-f overlapping 20) is formed in the top cover (50) of the heat sink cover (50/51), the first window exposes an entire upper surface of the high-power-density chip (top surface of 20 is exposed through the opening in 50 which is the window formed in cover 50 and the top surface of chip 20 is exposed to heat transfer through window material 40, thus allowing for the top surface of chip 20 to be exposed to a transfer of thermal energy); and
wherein a second window (see annotated figures below) is formed to replace a piece of the side supporting part (the replacing step is a product by process limitation that does not affect the structure of the device, as the second window is located at the side supporting part), wherein the second window is arranged to be next to the high-power-density chip (20) to expose side surfaces of the high-power-density chip so as to further cool down the high-power-density chip (exposed sides of 20 from the sides of 50), and wherein the second window is not parallel to the top cover of the heat sink cover (second window adjacent to sidewalls of chip 20 are not parallel to the top cover of the heat sink cover 50).
PNG
media_image1.png
611
1315
media_image1.png
Greyscale
The embodiment of figure 6 of Sato does not explicitly disclose wherein the top cover comprises slits, wherein the slits have positions aligned to gaps between the one or more chips.
Nonetheless, the embodiment of figure 4 of Sato discloses wherein a top cover (50c-f) comprises slits (slits located between each quadrant of 50c-f), wherein the slits have positions aligned to gaps between the one or more chips (30, 20).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to include the slits of embodiment shown in figure 4 in the structure of the embodiment shown in figure 6 since this will more effectively prevent heat transfer between chips.
As to claim 3, Sato discloses the electronic packaging structure according to claim 1 (paragraphs above),
wherein an area of the first window is greater than or equal to an area of the upper surface of the high-power-density chip (opening in 50c-f is shown with greater area than chip 20).
As to claim 5, Sato discloses the electronic packaging structure according to claim 1 (paragraphs above),
wherein a total area of the slits is less than or equal to a total area of the gaps between the one or more chips (fig 4, area of slits are less than gaps between chips (30, 20).
As to claim 7, Sato discloses the electronic packaging structure according to claim 1 (paragraphs above),
a first thermal interface material layer (fig 6, 52), wherein the top cover (50) is adhered to upper surfaces of the one or more chips (30) through the first thermal interface material layer (52).
As to claim 9, Sato discloses the electronic packaging structure according to claim 1 (paragraphs above),
wherein the side supporting part (51) is bonded to the substrate (10) by a sealant (54).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Hung et al. (US Pub. No. 2020/0066612 A1), hereafter referred to as Hung.
As to claim 6, Sato discloses the electronic packaging structure according to claim 1 (paragraphs above).
Sato does not disclose wherein each of the slits comprises sub-slits, and wherein each of the sub-slits is arranged in an array.
Nonetheless, Hung discloses a similar electronic package structure including either a continuous slit (fig 2, continuous slit 40H separating chips) or wherein the slit structure comprises sub-slits (fig 4, sub-slits 40H), and wherein each of the sub-slits is arranged in an array (fig 4, 40H).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the continuous slit structure of Sato into a plurality of sub-slits arranged in an array as taught by Hung since Hung teaches that this alternative embodiment would provide improved heat dissipation.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Patel et al. (US Pub. No. 2018/0012878 A1), hereafter referred to as Patel.
As to claim 8, Sato discloses the electronic packaging structure according to claim 1 (paragraphs above).
Sato does not disclose a second thermal interface material layer.
Nonetheless, Patel discloses a second thermal interface material layer (219), wherein the top cover (211) is adhered to an external heat sink (217) through the second thermal interface material layer (219).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the second thermal interface material layer and external heat sink to the top cover of Sato as taught by Patel since this will more effectively disperse heat from the chips.
Response to Arguments
Applicant's arguments filed 12/5/2025 have been fully considered but they are not persuasive.
Applicant argued that Sato does not disclose different openings and thus does not disclose the claimed windows.
Examiner disagrees because windows may be opened or closed. Furthermore, windows may be made of different materials. Applicant has not argued that the material 40 cannot be considered to be a window material. Examiner maintains that the window opening in structure 50 that incudes window material 40 is properly considered to be a first window, especially, because the window material 40 exposes the entire top surface of chip 20 to thermal cooling.
Applicant has made arguments that Sato does not disclose the claimed windows, however, the Applicant has not made it clear what materials qualify as window material and what materials do not qualify as window materials. Examiner maintains that structure 40 in the opening of structure 50 includes window material 40 surrounded by a frame area of the window.
Applicant argued that Sato does not disclose the claimed second window because the only window openings between structure 50 are between chips and do not expose the side surface of the chips.
Examiner disagrees because the structure shown in cross sectional view of Sato’s figure 6 shows that there is no structural material 50 located on the sidewalls of chip 20, as such, the appears to be no structural difference between the window structure of Sato and the second window structure 6 as claimed and shown in figure 6 of the Application.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2022/0301971A1; US 2013/0043581A1; US 2020/0350229A1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 5/27/2026
Prosecution Insights