DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 11 have been considered but are moot because the new ground of rejection does not rely on how any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 15 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention. The added material which is not supported by the original disclosure is as follows:
Claim 15 states: “to reduce signal routing strength”.
The term “to reduce signal routing strength” is not supported in the disclosure nor is defined in the claim language.
Applicant’s Specification states at [047] “FIG. 7 illustrates, in diagram form a top view of a semiconductor substrate core 700 having a cavity having a PTH rectangular region formed therein, in accordance with at least one embodiment. Semiconductor substrate core 700 includes a substrate core 702. Substrate core 702 includes a cavity 704 with embedded devices 706. As discussed earlier, embedded devices may include capacitors, inductors, active semiconductor chips, and the like. PTH rectangular region 708 allows for utilization of this region through the cavity to reduce the IO routing length and improve performance associated with shorter routing distances”.
Applicant’s Specification states at [048] “FIG. 8 illustrates, in diagram form, a top view of a semiconductor substrate core 800 having a cavity having a PTH alley region formed therein, in accordance with at least one embodiment. Semiconductor substrate core 800 includes a substrate core 802. Substrate core 802 includes a cavity 804 with embedded devices 806. As discussed earlier, embedded devices may include capacitors, inductors, active semiconductor chips, and the like. PTH alley region 808 allows for utilization of this region through the cavity to reduce the IO routing length and improve performance associated with shorter routing distances.”
Applicant’s Specification states at [052] “First, PTH's may be provided in gapfill material traditionally used in the cavity of a substrate core and illustrated herein in FIG. 7 and FIG. 8. These structures illustrate the use of PTH's through the cavity region, which may be filled with an insulator, to reduce the signal routing length and provide the concomitant performance improvements. As illustrated, these PTHs may be formed in groups to form islands amidst embedded devices as illustrated in FIG. 7, be formed as alleys under a area with critical timing constraints such as a PHY interface for a surface mounted chip as illustrated in FIG. 8, or be formed into other shapes such as donuts, half moons, and similar geometric shapes. PTYs such as these illustrated in FIG. 7 and FIG. 8 may also be used to remove heat from hotspots of the surface mounted and/or embedded devices”.
Therefore there is not support for the term “to reduce signal routing strength” in the claim language, as this term is not defined in the supporting disclosure. Applicant is required to cancel the new matter in the reply to this Office Action and appropriate correction is required.
The Office shall assume the claim language was possibly meant to read as “to reduce signal routing length”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 15 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2020/0083179 A1).
Regarding Claim 15, Lee (US 2020/0083179 A1) discloses of a semiconductor packaging substrate core (Fig 8) comprising: a substrate (110C) comprising: a first surface (upper surface of 111b); a cavity (111bh) formed into said first surface to a depth less than the thickness (see Fig 8) of said substrate (110C); a device (126) selected from a capacitor ([0063]), an inductor ([0063]), and an active semiconductor chip disposed within said cavity (111bh); and a vertical interconnect module (120; 120 is a separable component or self-contained device that vertically interconnects [0063-0066]) co-located in said cavity (111bh) with said device (126), said vertical interconnect module (120) being physically separate (see Fig 8 [0007-0008]) from the substrate core and electrically coupled to the device (to reduce signal routing strength ([0063] “an electrical connection path may be relatively short”; structure shown would have a shorter connection path and thus be able to provide a reduced signal routing length)).
Claim 15 states “to reduce signal routing strength.”. However it has been held that the recitation that an element is “adapted to” perform a function is not a positive limitation but only requires the ability to so perform. It does not constitute a limitation in any patentable sense. In re Hutchinson, 69 USPQ 138.
The recitation that “semiconductor packaging substrate core” has not been given patentable weight because it has been held that a preamble is denied the effect of a limitation where the claim is drawn to a structure and the portion of the claim following the preamble is a self-contained description of the structure not depending for completeness upon the introductory clause. Kropa v. Robie, 88 USPQ 478 (CCPA 1951).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Igarashi (US 2013/0003314 A1) in view of Lee (US 2020/0083179 A1).
Regarding Claim 11, Igarashi (US 2013/0003314 A1) discloses a semiconductor packaging substrate core (Fig 4) comprising: a substrate (10D) comprising: a first surface (upper surface of 11); a cavity (at 12; [0045-0049,0075]) formed into said first surface (upper surface of 11) to a depth less than the thickness (cavity depth is less than overall thickness of 10D) of said substrate (10D); a device (38) selected from a capacitor ([0077]), an inductor, and an active semiconductor chip disposed within said cavity (12); and a vertical interconnect module (13; 13 is a separable component or self-contained device that vertically interconnects [0050-0052]) disposed within said cavity (12).
Igarashi does not explicitly disclose the vertical interconnect module is disposed along with said device.
Lee (US 2020/0083179 A1) teaches of a semiconductor packaging substrate core (Fig 8) comprising: a substrate (110C) comprising: a first surface (upper surface of 111b); a cavity (111bh) formed into said first surface to a depth less than the thickness (see Fig 8) of said substrate (110C); a device (126) selected from a capacitor ([0063]), an inductor ([0063]), and an active semiconductor chip disposed within said cavity (111bh); and a vertical interconnect module (120; 100 is a separable component or self-contained device that vertically interconnects [0063-0066]) disposed within said cavity (111bh) along with said device (126).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the core as disclosed by Igarashi, comprising a vertical interconnect module disposed within said cavity along with said device as taught by Lee, in order to provide an embedded interconnect structure capable of electrically connecting components, resolve reliability issues, reduce costs, improve power integrity properties, simplify manufacturing, shorten electrical connection paths (Lee, [0003-0006,0063]).
The recitation that “semiconductor packaging substrate core” has not been given patentable weight because it has been held that a preamble is denied the effect of a limitation where the claim is drawn to a structure and the portion of the claim following the preamble is a self-contained description of the structure not depending for completeness upon the introductory clause. Kropa v. Robie, 88 USPQ 478 (CCPA 1951).
Regarding Claim 13, Igarashi further discloses the semiconductor packaging substrate core (Fig 4) of claim 11 further comprising said substrate (10D) further comprising a vertical interconnect (31,33; [0053,0054]) through a cavity fill material (14A,14B; [0048,0076]; see Fig 4 showing portions of 14 filling 12).
The recitation that “semiconductor packaging substrate core” has not been given patentable weight because it has been held that a preamble is denied the effect of a limitation where the claim is drawn to a structure and the portion of the claim following the preamble is a self-contained description of the structure not depending for completeness upon the introductory clause. Kropa v. Robie, 88 USPQ 478 (CCPA 1951).
Regarding Claim 14, Igarashi further discloses the semiconductor packaging substrate core (Fig 4) of claim 13 wherein said vertical interconnect (31,33) through said cavity fill material (14) is not through (see Fig 4 showing 31,33 only partially through 10D) said substrate core.
The recitation that “semiconductor packaging substrate core” has not been given patentable weight because it has been held that a preamble is denied the effect of a limitation where the claim is drawn to a structure and the portion of the claim following the preamble is a self-contained description of the structure not depending for completeness upon the introductory clause. Kropa v. Robie, 88 USPQ 478 (CCPA 1951).
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Igarashi (US 2013/0003314 A1) in view of Lee (US 2020/0083179 A1) as applied to claim 11 above and further in view of Min (US 2016/0143129 A1).
Regarding Claim 12, Igarashi in view of Lee teaches the limitations of the preceding claim.
Igarashi further discloses the semiconductor packaging substrate core (Fig 4) of claim 11 further comprising said substrate (10D) further comprising a first conductive slug module (42; [0079] note that the claim has not structurally defined “conductive slug module” and as 42 includes thermally conductive 42, 42 can be interested as a conductive slug module) disposed within said cavity (12).
Note that the structure of the cavity has not been defined in the claim language however in order to speed prosecution, the Office will assume that Igarashi does not explicitly disclose a first conductive slug module disposed within said cavity.
Min (US 2016/0143129 A1) teaches of a semiconductor packaging substrate core (Fig 1-5) comprising: a substrate (100) comprising: a first surface (upper surface of 10); a cavity (C1) formed into said first surface to a depth less than the thickness (see Fig 1-4; [0074]) of said substrate (100); a device (200) selected from a capacitor ([0055]), an inductor ([0055]), and an active semiconductor chip ([0055]) disposed within said cavity (C1); and a first conductive slug module (110; 110 is a separable component or self-contained device that vertically interconnects heat [0080]) disposed within said cavity (C1) along with said device (200).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the core as taught by Igarashi in view of Lee, comprising a first conductive slug module disposed within said cavity as taught by Min, in order to meet demands for lighter weight, smaller sizes, while transmitting heat away from heat generating components (Min, [0005-0021,0055,0080]) and furthermore since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art, in order to meet demands for lighter weight, smaller sizes, while transmitting heat away from heat generating components, such that the cavity comprises the device, the slug module and the interconnect module. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
The recitation that “semiconductor packaging substrate core” has not been given patentable weight because it has been held that a preamble is denied the effect of a limitation where the claim is drawn to a structure and the portion of the claim following the preamble is a self-contained description of the structure not depending for completeness upon the introductory clause. Kropa v. Robie, 88 USPQ 478 (CCPA 1951).
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2020/0083179 A1) as applied to claim 15 above and further in view of Min (US 2016/0143129 A1) and Campbell (US 2017/0181286 A1).
Regarding Claim 16, Lee discloses the limitations of the preceding claim.
Lee does not disclose the semiconductor packaging substrate core of claim 15 further comprising said substrate further comprising a first conductive slug module co-located in said cavity with said device and said vertical interconnect module.
Min (US 2016/0143129 A1) teaches of a semiconductor packaging substrate core (Fig 1-5) comprising: a substrate (100) comprising: a first surface (upper surface of 10); a cavity (C1) formed into said first surface to a depth less than the thickness (see Fig 1-4; [0074]) of said substrate (100); a device (200) selected from a capacitor ([0055]), an inductor ([0055]), and an active semiconductor chip ([0055]) disposed within said cavity (C1); and a first conductive slug module (110; 110 is a separable component or self-contained device that vertically interconnects heat [0080]) disposed within said cavity (C1) along with said device (200).
Campbell (US 2017/0181286 A1) teaches of a packaging substrate core (Fig 2; [0032] “diverse selection of components”) comprising a substrate (230) comprising a first module (240) co-located in a cavity (250) with a device (240) and a module (240).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the core as disclosed by Lee further comprising said substrate further comprising a first conductive slug module co-located in said cavity as taught by Min, in order to meet demands for lighter weight, smaller sizes, while transmitting heat away from heat generating components (Min, [0005-0021,0055,0080]) such that said substrate further comprising a first conductive slug module co-located in said cavity with said device and said vertical interconnect module as taught by Campbell in order to provide versatility and meet desired needs (Campbell, [0026-0032]). Furthermore since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art, in order to meet demands for lighter weight, smaller sizes, provide versatility and meet desired needs, while transmitting heat away from heat generating components, such that the cavity comprises the device, the slug module and the interconnect module. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
The recitation that “semiconductor packaging substrate core” has not been given patentable weight because it has been held that a preamble is denied the effect of a limitation where the claim is drawn to a structure and the portion of the claim following the preamble is a self-contained description of the structure not depending for completeness upon the introductory clause. Kropa v. Robie, 88 USPQ 478 (CCPA 1951).
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2016/0316565 A1) in view of Schober (US 2020/0128669 A1).
Regarding Claim 17, Chen (US 2016/0316565 A1) discloses a semiconductor packaging substrate core (Fig 5) comprising: a substrate (100) comprising: a first surface (upper surface of 102); a cavity (112) formed into said first surface to a depth less than the thickness of said substrate (100); a device (118) selected from a capacitor, an inductor, and a component (118; [0027]) disposed within said cavity (112); and a conductive slug module (122,124,143) disposed within said cavity (112) adjacent to said device (118), the conductive slug module (122,124,143) comprising a dielectric body (122,124; [0028]) and at least one conductive slug (143; [0055]) extending therethrough, the slug module (122,124,143) configured to conduct heat away from the component (118).
Chen does not explicitly disclose an active semiconductor chip.
Schober (US 2020/0128669 A1) teaches of a semiconductor packaging substrate core (Fig 1) comprising: a substrate (101) comprising: a first surface (upper surface of 101); a cavity (102) formed into said first surface and a conductive slug module (115,116) disposed within said cavity (102) adjacent to said device (118), the conductive slug module (115,116; [0086]) comprising a dielectric body (115) and at least one conductive slug (116; [0086]) extending therethrough, the slug module (115,116) configured to conduct heat away from the active semiconductor device (118; [0013,0044,claim 10]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the core as disclosed by Chen, comprising an active semiconductor chip as taught by Schober, in order to provide a component that can rely on a source of energy, provide a component that can rely on a DC circuit, provide a possible power into a circuit and may source power (Schober, [0003-0015,0044]).
The recitation that “semiconductor packaging substrate core” has not been given patentable weight because it has been held that a preamble is denied the effect of a limitation where the claim is drawn to a structure and the portion of the claim following the preamble is a self-contained description of the structure not depending for completeness upon the introductory clause. Kropa v. Robie, 88 USPQ 478 (CCPA 1951).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2896