DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 11, 15 and 17 have been considered but are moot because the new ground of rejection does not rely on how any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues on page 9 of the Remarks, “Applicants respectfully submit that Chen is directed to heat-recovery and thermoelectric structures. Schober is directed to a component carrier with an interposer in a through-hole. Neither Chen nor Schober discloses or suggests a conductive slug module disposed in a cavity adjacent to a device and configured to conduct heat away through the cavity region”. The Office respectfully disagrees. Chen teaches of the conductive slug module (122,124,143) comprising a dielectric body (122,124; [0028]) and at least one conductive slug (143; [0055]) extending therethrough, the slug module (122,124,143) configured to conduct heat ([0055-0057,0065]; 143 is heat conducting and located within cavity area 112 and thus would conduct heat along the length of 143 to exchange heat with 130 which is away from 118) away from said device (118) through cavity region (112).
As shown below from paragraphs [0055] and [0065] of Chen, Chen discusses how heat is transferred through 143.
[0055] The heat-storing device 120 further includes a housing 122, a phase-change material 124, at least one third via 117, and a third heat-conducting pillar 143. The housing 122 is filled with the phase-change material 124. The third via 117 penetrates the heat-storing device 120. The third heat-conducting pillar 143 is disposed in the third via 117, in which the processor 118 performs heat exchange with the first metal-junction surface 132 of the thermoelectric device 130 through the second heat-conducting pillar 142 and the third heat-conducting pillar 143.
[0065] As previously mentioned, the circuit board of the present invention has the embedded structure and includes the heat-storing device and the thermoelectric device embedded in the substrate. The heat-storing device is used for storing the waste heat generated by the processor. The thermoelectric device is used for converting the thermal energy stored in the heat-storing device into the electrical energy. Therefore, as the processor disposed on the circuit board starts operating, the thermal energy generated by the processor is stored and transmitted to the thermoelectric device, and then the thermal energy is converted into the electrical energy. In addition, since the thermal energy can be stored in the heat-storing device, the thermal energy can be converted into the electrical energy by the thermoelectric device after the operation of the processor is finished. Therefore, the other operating elements can continuously receive the electrical energy, thereby realizing the effect of saving energy.
As Chen in view of Schober teaches the claimed limitations, the rejection stands.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 11 – 16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention. The added material which is not supported by the original disclosure is as follows:
Claim 11 states: “the conductor forming a continuous vertical electrical path within said cavity region between said device and an interconnect of said substrate”.
The language of “forming a continuous vertical electrical path within said cavity region between said device and an interconnect” is not supported in the disclosure. This language implies the embedded device, within the cavity, is electrically coupled to and co-located with the vertical interconnect module, also within the cavity. This is concept is not supporter by the Application. The Specification supports a vertical interconnect module co-located in the cavity with another embedded device (e.g. capacitor) and the interconnect module reducing signal routing length; but does not teach that the embedded device is electrically connected with the interconnect module. The Application seemingly only supports the vertical interconnect module electrically interfacing with vias (PTHs) above the cavity.
The Office shall assume the claim language was possibly meant to read as “the conductor forming a continuous vertical electrical path within said cavity region between another device and an interconnect of said substrate”.
Claim 15 states: “electrically coupled to the device to reduce signal routing length between said device and an interconnect of said substrate”.
The language of “electrically coupled to the device” and “reduce signal routing length between said device and an interconnect of said substrate” is not supported in the disclosure. This language implies the embedded device within the cavity is electrically coupled to and co-located with the vertical interconnect module, also within the cavity. This is concept is not supporter by the Application. The Specification supports a vertical interconnect module co-located in the cavity with another embedded device (e.g. capacitor) and the interconnect module reducing signal routing length, but does not teach that the embedded device is electrically connected with the interconnect module, such that a signal routing length is reduced.
Applicant’s Specification states at [047] “FIG. 7 illustrates, in diagram form a top view of a semiconductor substrate core 700 having a cavity having a PTH rectangular region formed therein, in accordance with at least one embodiment. Semiconductor substrate core 700 includes a substrate core 702. Substrate core 702 includes a cavity 704 with embedded devices 706. As discussed earlier, embedded devices may include capacitors, inductors, active semiconductor chips, and the like. PTH rectangular region 708 allows for utilization of this region through the cavity to reduce the IO routing length and improve performance associated with shorter routing distances”.
Applicant’s Specification states at [048] “FIG. 8 illustrates, in diagram form, a top view of a semiconductor substrate core 800 having a cavity having a PTH alley region formed therein, in accordance with at least one embodiment. Semiconductor substrate core 800 includes a substrate core 802. Substrate core 802 includes a cavity 804 with embedded devices 806. As discussed earlier, embedded devices may include capacitors, inductors, active semiconductor chips, and the like. PTH alley region 808 allows for utilization of this region through the cavity to reduce the IO routing length and improve performance associated with shorter routing distances.”
Applicant’s Specification states at [052] “First, PTH's may be provided in gapfill material traditionally used in the cavity of a substrate core and illustrated herein in FIG. 7 and FIG. 8. These structures illustrate the use of PTH's through the cavity region, which may be filled with an insulator, to reduce the signal routing length and provide the concomitant performance improvements. As illustrated, these PTHs may be formed in groups to form islands amidst embedded devices as illustrated in FIG. 7, be formed as alleys under a area with critical timing constraints such as a PHY interface for a surface mounted chip as illustrated in FIG. 8, or be formed into other shapes such as donuts, half moons, and similar geometric shapes. PTYs such as these illustrated in FIG. 7 and FIG. 8 may also be used to remove heat from hotspots of the surface mounted and/or embedded devices”.
Therefore there is not support for the language of “to reduce signal routing length between said device and an interconnect” in the claim language. Applicant is required to cancel the new matter in the reply to this Office Action and appropriate correction is required.
The Office shall assume the claim language was possibly meant to read as “to reduce signal routing length between another device”.
Claims 12, 13, 14 and 16 are rejected due to dependency from claims 11 and 15.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 - 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 11, 15 and 17 recites the limitation "said" in “said cavity region”. There is insufficient antecedent basis for this limitation in the claim.
Claims 12, 13, 14, and 16 are rejected due to dependency from claims 11 and 15.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 11, 13 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawabe (US 2008/0239685 A1).
Regarding Claim 11, Kawabe (US 2008/0239685 A1) discloses of a semiconductor ([0003,0077]) packaging substrate core (Fig 1-15) comprising: a substrate (10) comprising: a first surface (upper surface of 164); a cavity (90) formed into said first surface to a depth less than the thickness of said substrate (10); a device (101) selected from a capacitor ([0083]), an inductor, and an active semiconductor chip disposed within said cavity (90); and a vertical interconnect module (14) disposed within said cavity (90) along with said device (101), said vertical interconnect module (14) comprising a dielectric body (165,166; [0081]) and at least one conductor (15; [0081]) extending vertically therethrough, the conductor (15) forming a continuous vertical electrical path ([0081,0094]) within said cavity region (90) between (said) device (21) and an interconnect (43,47) of said substrate (10).
The recitation that “semiconductor packaging substrate core” has not been given patentable weight because it has been held that a preamble is denied the effect of a limitation where the claim is drawn to a structure and the portion of the claim following the preamble is a self-contained description of the structure not depending for completeness upon the introductory clause. Kropa v. Robie, 88 USPQ 478 (CCPA 1951).
Regarding Claim 13, Kawabe further discloses the semiconductor packaging substrate core (Fig 1-15) of claim 11 further comprising a vertical interconnect (47) through a cavity fill material (33a; [0084]).
Regarding Claim 15, Kawabe discloses a semiconductor ([0003,0077]) packaging substrate core (Fig 1-15) comprising: a substrate (10) comprising: a first surface (upper surface of 164); a cavity (90) formed into said first surface to a depth less than the thickness of said substrate (10); a device (101) selected from a capacitor ([0083]), an inductor, and an active semiconductor chip located within said cavity (90); and a vertical interconnect module (14) co-located in said cavity (90) with said device (101), said vertical interconnect module (14) being physically separate (see Fig 15) from the substrate core (see Fig 15 showing 14 is separate from 161) and electrically coupled ([0094]) to (the) device (21) to reduce signal routing length (structure shown would perform this function; [0121]) between said device (21) and an interconnect (43,47) of said substrate, said vertical interconnect module (14) comprising a dielectric body (165,166; [0081]) and at least one conductor (15; [0081]) extending vertically therethrough, the conductor (15) forming a continuous vertical electrical path ([0081,0094]) within said cavity region (90) between (said) device (21) and said interconnect (43,47) of said substrate (10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kawabe (US 2008/0239685 A1) as applied to claim 11 above and further in view of Min (US 2016/0143129 A1).
Regarding Claim 12, Kawabe discloses the limitations of the preceding claim.
Kawabe does not disclose the semiconductor packaging substrate core of claim 11 further comprising a first conductive slug module disposed within said cavity.
Min (US 2016/0143129 A1) teaches of a semiconductor packaging substrate core (Fig 1-5) comprising: a substrate (100) comprising: a first surface (upper surface of 10); a cavity (C1) formed into said first surface to a depth less than the thickness (see Fig 1-4; [0074]) of said substrate (100); a device (200) selected from a capacitor ([0055]), an inductor ([0055]), and an active semiconductor chip ([0055]) disposed within said cavity (C1); and a first conductive slug module (110; 110 is a separable component or self-contained device that vertically interconnects heat [0080]) disposed within said cavity (C1) along with said device (200).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the core as disclosed by Kawabe, further comprising a first conductive slug module disposed within said cavity as taught by Min, in order to meet demands for lighter weight, smaller sizes, while transmitting heat away from heat generating components (Min, [0005-0021,0055,0080]) and furthermore since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art, in order to meet demands for lighter weight, smaller sizes, while transmitting heat away from heat generating components, such that the cavity comprises the device, the slug module and the interconnect module. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
The recitation that “semiconductor packaging substrate core” has not been given patentable weight because it has been held that a preamble is denied the effect of a limitation where the claim is drawn to a structure and the portion of the claim following the preamble is a self-contained description of the structure not depending for completeness upon the introductory clause. Kropa v. Robie, 88 USPQ 478 (CCPA 1951).
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kawabe (US 2008/0239685 A1) as applied to claim 13 above and further in view of Kim (US 2016/0172291 A1).
Regarding Claim 14, Kawabe discloses the limitations of the preceding claim.
Kawabe does not explicitly disclose the semiconductor packaging substrate core of claim 13 wherein said vertical interconnect through said cavity fill material extends between opposing surfaces within said cavity fill material to provide vertical electrical connection within said cavity region.
Kim (US 2016/0172291 A1) teaches of a packaging substrate core (Fig 4-6) wherein a vertical interconnect (1380) through a cavity fill material (1550) extends between opposing surfaces (upper and lower surfaces of 1550) within said cavity fill material (1550) to provide vertical electrical connection ([0085-0090]) within a cavity region (1110).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the core as disclosed by Kawabe, wherein said vertical interconnect through said cavity fill material extends between opposing surfaces within said cavity fill material to provide vertical electrical connection within said cavity region as taught by Kim, in order to decrease electrical resistance, improve power property, and potentially increase effective sectional areas (Kim, [0085-0090]). Note that additional vertical connections provide additional paths of conductivity through the package and thus would increase functional capabilities of the assembly.
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kawabe (US 2008/0239685 A1) as applied to claim 15 above and further in view of Min (US 2016/0143129 A1) and Campbell (US 2017/0181286 A1).
Regarding Claim 16, Kawabe discloses the limitations of the preceding claim.
Kawabe does not disclose the semiconductor packaging substrate core of claim 15 further comprising a first conductive slug module co-located in said cavity with said device and said vertical interconnect module.
Min (US 2016/0143129 A1) teaches of a semiconductor packaging substrate core (Fig 1-5) comprising: a substrate (100) comprising: a first surface (upper surface of 10); a cavity (C1) formed into said first surface to a depth less than the thickness (see Fig 1-4; [0074]) of said substrate (100); a device (200) selected from a capacitor ([0055]), an inductor ([0055]), and an active semiconductor chip ([0055]) disposed within said cavity (C1); and a first conductive slug module (110; 110 is a separable component or self-contained device that vertically interconnects heat [0080]) disposed within said cavity (C1) along with said device (200).
Campbell (US 2017/0181286 A1) teaches of a packaging substrate core (Fig 2; [0032] “diverse selection of components”) comprising a substrate (230) comprising a first module (240) co-located in a cavity (250) with a device (240) and a module (240).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the core as disclosed by Kawabe further comprising a first conductive slug module co-located in said cavity as taught by Min, in order to meet demands for lighter weight, smaller sizes, while transmitting heat away from heat generating components (Min, [0005-0021,0055,0080]) such that said substrate further comprising a first conductive slug module co-located in said cavity with said device and said vertical interconnect module as taught by Campbell in order to provide versatility and meet desired needs (Campbell, [0026-0032]). Furthermore since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art, in order to meet demands for lighter weight, smaller sizes, provide versatility and meet desired needs, while transmitting heat away from heat generating components, such that the cavity comprises the device, the slug module and the interconnect module. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
The recitation that “semiconductor packaging substrate core” has not been given patentable weight because it has been held that a preamble is denied the effect of a limitation where the claim is drawn to a structure and the portion of the claim following the preamble is a self-contained description of the structure not depending for completeness upon the introductory clause. Kropa v. Robie, 88 USPQ 478 (CCPA 1951).
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2016/0316565 A1) in view of Schober (US 2020/0128669 A1).
Regarding Claim 17, Chen (US 2016/0316565 A1) discloses a semiconductor packaging substrate core (Fig 5) comprising: a substrate (100) comprising: a first surface (upper surface of 102); a cavity (112) formed into said first surface to a depth less than the thickness of said substrate (100); a device (118) selected from a capacitor, an inductor, and a component (118; [0027]) disposed within said cavity (112); and a conductive slug module (122,124,143) disposed within said cavity (112) adjacent (nearby or next to) to said device (118), the conductive slug module (122,124,143) comprising a dielectric body (122,124; [0028]) and at least one conductive slug (143; [0055]) extending therethrough, the slug module (122,124,143) configured to conduct heat ([0055-0057,0065]; 143 is heat conducting and located within cavity area 112 and thus would conduct heat along the length of 143 to exchange heat with 130 which is away from 118) away from said device (118) through cavity region (112).
Chen does not explicitly disclose an active semiconductor chip.
Schober (US 2020/0128669 A1) teaches of a semiconductor packaging substrate core (Fig 1) comprising: a substrate (101) comprising: a first surface (upper surface of 101); a cavity (102) formed into said first surface and a conductive slug module (115,116) disposed within said cavity (102) adjacent to said device (118), the conductive slug module (115,116; [0086]) comprising a dielectric body (115) and at least one conductive slug (116; [0086]) extending therethrough, the slug module (115,116) configured to conduct heat away from the active semiconductor device (118; [0013,0044,claim 10]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the core as disclosed by Chen, comprising an active semiconductor chip as taught by Schober, in order to provide a component that can rely on a source of energy, provide a component that can rely on a DC circuit, provide a possible power into a circuit and may source power (Schober, [0003-0015,0044]).
The recitation that “semiconductor packaging substrate core” has not been given patentable weight because it has been held that a preamble is denied the effect of a limitation where the claim is drawn to a structure and the portion of the claim following the preamble is a self-contained description of the structure not depending for completeness upon the introductory clause. Kropa v. Robie, 88 USPQ 478 (CCPA 1951).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2847
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