DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 26-30 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/27/2026. Claims 26-30 are mutually exclusive form claims 1-15, because of the limitations “the second sidewall spacers in contact with the third conductive layer forms an angle 01 at a contact point of the upper surface of the third conductive layer and the second sidewall spacers, where 900 < 01 < 1150 measured from the upper surface of the third conductive layer”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,3-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al (US Pub No. 20150214237), in view of Chang et al (US Pub No. 20140197472).
With respect to claim 1, Hsieh et al discloses a plurality of stacked structures (258 is between the two stack structure, Fig.11D) arranged along a first direction disposed over a semiconductor substrate (X ), wherein the plurality of stacked structures are spaced-apart from each other (Fig.11D) and extend in a second direction (z direction) perpendicular to the first direction, and each stacked structure includes: a first conductive layer (236) disposed over the semiconductor substrate (10); a first dielectric layer (238) disposed over the first conductive layer; and a second conductive layer (240) disposed over the first dielectric layer, wherein the first conductive layer, first dielectric layer, and second conductive layer are arranged in order along a third direction (y direction) perpendicular to the first and second directions; first sidewall spacers (244A,244B) disposed on opposing sides of each of the second conductive layers and an upper surface of each of the first conductive layers (Fig.11D); second sidewall spacers (246) disposed on opposing sides of the first sidewall spacers (Fig.11D) and opposing sides of each of the first conductive layers (Fig.11D),; a third conductive layer (262) disposed over the semiconductor substrate between adjacent stacked structures (Fig.11D); a fourth conductive layer (264) disposed over the second sidewall spacers on opposing sides of each of the stacked structures from where the third conductive layer is disposed (Fig.11D); and an insulating layer disposed over the second conductive layer (242A-B). However, Hsieh et al does not explicitly disclose wherein the first sidewall spacers have a three layer structure including an inner layer, a middle layer, and an outer layer, wherein the middle layer is formed of a different material than the inner layer and the outer layer, and the second sidewall material is uniform or have the same material. On the other hand, Cheng et al discloses the first sidewall spacers (124a,126,132,Fig.11) have a three layer structure (Fig.11) including an inner layer (124a), a middle layer (126), and an outer layer (132), wherein the middle layer is formed of a different material than the inner layer and the outer layer (Para 24-26), and the second sidewall spacers have the same material (146). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Hsieh et al according to the teachings of the Cheng et al such that that ONO sidewall is formed on the sidewall of the gate structure, in order to act as both charge trapping layer and isolation structure for a memory device.
With respect to claim 3, Hsieh et al discloses wherein an upper surface of the third conductive layer (upper surface of the 262) is located higher than an upper surface of the second conductive layer with respect to the substrate (240).
With respect to claim 4, Hsieh et al discloses, further comprising a second dielectric layer (234) disposed between the first conductive layer and the substrate (Fig.11D).
With respect to claim 5, Hsieh et al discloses wherein the first dielectric layer is ONO layer (Para 17); however, it does not explicitly disclose comprises a silicon oxide layer, a silicon nitride layer, or multilayers of silicon oxide and silicon nitride. However, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that the first dielectric layer is made from silicon oxide and silicon nitride as ONO layer, because they are commonly used in the industry and do not require additional equipment and training.
With respect to claim 6, Hsieh et al discloses ONO is formed between the first conductive layer and substrate (Para 17). However, it does not explicitly disclose further comprising a silicon oxide layer disposed between the first conductive layer and the substrate. However, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that the dielectric layer between first conductive layer and substrate is made from silicon oxide and silicon nitride as ONO layer, because they are commonly used in the industry and do not require additional equipment and training.
With respect to claim 7, the arts cited above do not explicitly disclose wherein the inner layer and the outer layer of the first sidewall spacers are silicon oxide layers. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that the inner layer and the outer layer of the first sidewall spacers are silicon oxide layers, because they are cheap and commonly used in the industry and do not require additional equipment or training.
With respect to claim 8, the arts cited above disclose that the dielectric layer are ONO (Para 24-26) and not wherein the inner layer and the outer layer of the first sidewall spacers are silicon nitride layers. However, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that instead of ONO layer NON layer is formed so the inner layer and the outer layer of the first sidewall spacers are silicon nitride layers; because they are equivalent.
With respect to claim 9, Hsieh et al discloses a first stacked structure (the stack layer including 240 on the left,Fig.11D) and a second stacked structure (on the right) arranged along a first direction ( x direction) disposed over a semiconductor substrate (10), wherein the first stacked structure and the second stacked structure are spaced-apart from each other and extend in a second direction ( in the Z direction perpendicular to the first direction), and each stacked structure includes: a first conductive layer (236’) disposed over the semiconductor substrate; a first dielectric layer disposed over the first conductive layer (238); and a second conductive layer (240) disposed over the first dielectric layer, wherein the first conductive layer, first dielectric layer, and second conductive layer are arranged in order along a third direction (in the y direction) perpendicular to the first and second directions (Fig.11D), and wherein the first conductive layer has a greater width along the first direction than the second conductive layer (Fig.11D) ;first sidewall spacers disposed on opposing sides of each of the second conductive layers (244A,244B) ; second sidewall spacers (248,254) disposed on opposing sides of the first sidewall spacers and opposing sides of each of the first conductive layers (Fig.11D);a third conductive layer (262) disposed over the semiconductor substrate between the first stacked structure and the second stacked structure (Fig.11D); a fourth conductive layer disposed over the second sidewall spacers (264) on opposing sides of each of the stacked structures from where the third conductive layer is disposed (Fig.11D); and an insulating layer disposed over the second conductive layer ,wherein the insulating layer has a two layer structure (242A-B) including a nitride layer and an oxide layer (Para 17). However, Hsieh et al does not explicitly disclose wherein the first sidewall spacers have a three layer structure including at least one nitride layer and at least one oxide layer; and the second sidewall material is uniform or have the same material. On the other hand, Cheng et al discloses the first sidewall spacers (124a,126,132,Fig.11) have a three layer structure (Fig.11), including at least one nitride layer and at least one oxide layer (Para 24-26), and the second sidewall spacers have the same material (146). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Hsieh et al according to the teachings of the Cheng et al such that that ONO sidewall is formed on the sidewall of the gate structure, in order to act as both charge trapping layer and isolation structure for a memory device.
With respect to claim 10, Hsieh et al discloses wherein an upper surface of the third conductive layer (262) is located higher than an upper surface of the second conductive layer with respect to the substrate (Fig.11D).
With respect to claim 11, Hsieh et al discloses further comprising a second dielectric layer (234) disposed between the first conductive layer and the substrate.
With respect to claim 12, Hsieh et al discloses wherein the first dielectric layer is ONO layer (Para 17); however, it does not explicitly disclose comprises a silicon oxide layer, a silicon nitride layer, or multilayers of silicon oxide and silicon nitride. However, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that the first dielectric layer is made from silicon oxide and silicon nitride as ONO layer, because they are commonly used in the industry and do not require additional equipment and training.
With respect to claim 13, Chang et al discloses wherein the first sidewall spacers have an inner layer (124a), a middle layer (126), and an outer layer (132); and the inner layer and the outer layer are oxide material (Para 18-26). It does not explicitly disclose that they are nitride layers. However, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that instead of ONO layer NON layer is formed so the inner layer and the outer layer of the first sidewall spacers are silicon nitride layers; because they are equivalent.
With respect to claim 14, Chang et al discloses wherein the first sidewall spacers have an inner layer (124a), a middle layer, and an outer layer (132); and the inner layer and the outer layer are oxide layers (Para 24-26). However, the arts cited above do not explicitly disclose that they are silicon oxide layers. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that the inner layer and the outer layer of the first sidewall spacers are silicon oxide layers, because they are cheap and commonly used in the industry and do not require additional equipment or training.
With respect to claim 15, the arts cited above do not explicitly disclose wherein the second sidewall spacers comprise silicon oxide. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that the second sidewall spacer is made from silicon oxide, because of it’s availability in the industry, which does not require additional equipment or training.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al (US Pub No. 20150214237), in view of Chang et al (US Pub No. 20140197472), in view of Pan et al (US Pub No. 20110049603).
With respect to claim 2, the arts cited above do not explicitly disclose wherein the insulating layer has a three layer structure including at least one silicon nitride layer and at least one silicon oxide layer. On the other hand, Pan et al discloses wherein the insulating layer (SIN,TEOS,SIN,Fig.13) has a three layer structure including at least one silicon nitride layer and at least one silicon oxide layer (Fig.13). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Pan et al such that an insulating layer has three layer structure including at least one silicon nitride layer and at least one silicon oxide layer, so a charge trapping layer along with insulating layer for the gate electrode is formed, to optimize the performance of the memory device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Liu et al (US Patent No. 8227850).
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/ALI NARAGHI/Primary Examiner, Art Unit 2817
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