DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, filed 02/05/2026, with respect to claim 20 has been fully considered and are persuasive. The objection of 09/09/2025 has been withdrawn.
Applicant’s arguments, filed 02/05/2026, with respect to the rejection(s) of claim(s) 1, 11, & 18 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as detailed below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, 5, & 7 are rejected under 35 U.S.C. 103 as being unpatentable over Mutyala et al. (US 2021/0159073) [Hereinafter Mutyala] & An et al. (US 2021/0277031A1) [Hereinafter An].
Regarding claim 1, Mutyala teaches A semiconductor processing method comprising:
providing deposition precursors [para 4-5] to a processing region [fig. 1, processing volume 120, para 20] of a semiconductor processing chamber [fig. 1, processing chamber 100, para 20],
wherein the deposition precursors comprise a silicon-carbon-and-hydrogen- containing precursor [para 5, “the silicon-containing precursor may be or include tetraethyl orthosilicate” which contains silicon, carbon, and hydrogen Si(OC2H5)4],
wherein a substrate [fig. 1, substrate 103, para 20] is disposed within the processing region [fig. 1, 102];
forming plasma effluents of the deposition precursors [para 5, wherein oxygen radicalized are plasma effluents, “The semiconductor substrate may be or include silicon, and forming the plasma of the oxygen-containing precursor may produce an oxygen-radicalized surface termination of the silicon of the semiconductor substrate.”] ;
and depositing a layer of silicon-containing material on the substrate [para 4, “The methods may include depositing a silicon-containing material on the semiconductor substrate.”],
wherein the layer of silicon-containing material is characterized by a dielectric constant of less than or about 4.0 [para 17, silicon oxide; wherein silicon oxide dielectric constant is approximately 3.9].
Mutyala fails to explicitly disclose a density of greater than or about 2.65 g/cm3.
However An teaches a density of greater than or about 2.65 g/cm3 [“As shown in FIG. 14, all of the silicon oxide films manufactured at different process temperatures had a density of 2.2 g/cm3 or more, and similar to the density of SiO2 bulk (2.68 g/cm3 ), confirming that a high-quality thin film was formed. That is, since the silicon oxide film of the present invention has a density similar to that of SiO2 bulk, excellent corrosion resistance can be expected.”].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the density to be 2.2 g/cm3 or more for excellent corrosion resistance as taught by An. Furthermore In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. (MPEP 2144.05).
Regarding claim 3, Mutyala/An teaches The semiconductor processing method of claim 1, wherein the silicon- carbon-and-hydrogen-containing precursor further comprises oxygen [Mutyala, para 5, “the silicon-containing precursor may be or include tetraethyl orthosilicate” which contains silicon, carbon, hydrogen, & oxygen Si(OC2H5)4].
Regarding claim 5, Mutyala/An teaches The semiconductor processing method of claim 1,
wherein the deposition precursors further comprise a boron-containing precursor, a nitrogen-containing precursor, or both [Mutyala, para 35, “Any number of oxygen-containing precursors may be utilized including diatomic oxygen, ozone, nitrogen-containing precursors that incorporate oxygen, water, alcohol, or other materials.”].
Regarding claim 7, Mutyala/An teaches The semiconductor processing method of claim 1, wherein the layer of silicon-containing material is characterized by a thickness of less than or about 50 A [Mutyala, para 47, “The portions of the films formed may be to any particular thickness…Sections produced may be characterized by a thickness of less than or about 50nm”]. MPEP 2144.05 states in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.
Claim(s) 2 & 4 are rejected under 35 U.S.C. 103 as being unpatentable over Mutyala & An as applied to claims 1, 3, 5, & 7 and further in view of Seamons et al. (US 2020/0171536) [Hereinafter Seamons].
Regarding claim 2, Mutyala/An teaches The semiconductor processing method of claim 1.
Mutyala/An fails to explicitly disclose wherein the silicon- carbon-and-hydrogen-containing precursor comprises bis(trimethylsilyl)methane or 1,1,3,3- tetramethyl-1,3-disilacyclobutane.
While Mutyala notes the exemplary precursor is a silane [para 17].
Seamons teaches wherein the silicon- carbon-and-hydrogen-containing precursor comprises bis(trimethylsilyl)methane or 1,1,3,3- tetramethyl-1,3-disilacyclobutane [para 19, “The silicon-containing precursor may include one or more of siloxanes…bis(trimethylsilyl)methane (BTMSM)” ].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the silicon containing precursor to comprise bis(trimethylsilyl)methane enabling lower temperature synthesis of high quality silicon-based films.
Regarding claim 4, Mutyala/An teaches The semiconductor processing method of claim 3.
Mutyala/An fails to explicitly disclose wherein the silicon- carbon-and-hydrogen-containing precursor comprises dimethyldimethoxysilane, 1,1,3,3- tetramethyl-1,3-dimethoxydisiloxane, or methoxy(dimethyl)silylmethane.
While Mutyala notes the exemplary precursor is a silane or tetraethyl orthosilicate [para 17].
Seamons teaches wherein the silicon- carbon-and-hydrogen-containing precursor comprises dimethyldimethoxysilane, 1,1,3,3- tetramethyl-1,3-dimethoxydisiloxane, or methoxy(dimethyl)silylmethane [claim 11].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the silicon-carbon-and hydrogen containing precursor to comprise one or more of the silicon precursors as taught by Seamons enabling lower temperature synthesis of high quality silicon-based films.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Mutyala & An as applied to claims 1, 3, 5, & 7 and further in view of Yang et al. (US 2022/0084809) [Hereinafter Yang].
Regarding claim 6, Mutyala/An teaches The semiconductor processing method of claim 5.
Mutyala/An fails to explicitly disclose wherein the boron-containing precursor comprises diborane (B2H6).
However Yang teaches wherein the boron-containing precursor comprises diborane (B2H6) [para 43, “In specific embodiments, the chemical vapor deposition process comprises flowing silane and diborane into the chamber.”].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the method to comprise a boron containing precursor such as diborane to include doping semiconductor materials thereby lowering the deposition temperature needed while enhancing the deposition rate.
Claims 8, are rejected under 35 U.S.C. 103 as being unpatentable over Mutyala & An as applied to claims 1, 3, 5, & 7 and further in view of Uemura et al. (JP2016076712A) [Hereinafter Uemura].
Regarding claim 8, Mutyala/An teaches The semiconductor processing method of claim 1.
Mutyala/An fails to explicitly disclose wherein the layer of silicon-containing material is characterized by a density of greater than or about 2.50 g/cm3.
While Mutyala notes the silicon containing material comprise silicon oxide.
Uemura teaches where silicon oxide comprises a density in the 2.2g/cm3 to 2.6g/cm3 [para 10].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the silicon oxide to comprise a density of greater than or about 2.50 g/cm3. Furthermore MPEP 2144.05 states in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Mutyala & An as applied to claims 1, 3, 5, & 7 and further in view of Hu et al. (US 2020/0190664) [Hereinafter Hu].
Regarding claim 9, Mutyala/An teaches The semiconductor processing method of claim 1.
Mutyala/An fails to explicitly disclose wherein the layer of silicon-containing material is deposited at a rate of greater than or about 200 Å/min.
While Mutyala notes existence of a target flow rate of deposition [para 36].
Hu teaches wherein the layer of silicon-containing material is deposited at a rate of greater than or about 200 Å/min [para 32].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the silicon-containing material to be deposited at a rate of greater than or about 200 Å/min allowing for efficient, high-volume production while maintaining uniformity in high quality dielectric films.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Mutyala & An as applied to claims 1, 3, 5, & 7 and further in view of Guo et al. (US 2020/0332414) [Hereinafter Guo].
Regarding claim 10, Mutyala/An teaches The semiconductor processing method of claim 1.
Mutyala/An fails to explicitly disclose exposing the layer of silicon-containing material to ultraviolet light to provide a cured layer of silicon-containing material,
wherein the cured layer of silicon-containing material is characterized by a stress of less than or about -150 MPa.
Guo teaches exposing the layer of silicon-containing material [fig. 1C/1E, silicon containing second layer 130, para 34] to ultraviolet light to provide a cured layer of silicon-containing material [para 34, “The second layer 130 is converted to a cured composition 131, as depicted in FIG. 1E. The curing process drives out unwanted solvents from the second layer 130, solidifies and stabilizes the second layer, and can also modify chemical and optical properties of the second layer, converting the second later to the cured composition 131. The curing process or treatment can be… an ultraviolet (UV) curing process”].
Guo further notes [para 35] “The curing process is used to modify the second layer 130 film composition and stress as required for a given application.” One of ordinary skill understands the curing process may be used to modify the layer to any reduced stress level desired by design to reduce reliability issues and structural defects in the thin film layer. Simply discovering the optimum or workable ranges absent evidence indication such stress level is critical is not inventive. Furthermore MPEP 2144.05 states it is not inventive to discover the optimum or workable ranges by routine experimentation.
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the discovery of the cured silicon containing layer stress level to be reduced to about -150MPa or less wherein one of ordinary skill understands the curing process may be used to modify the layer to any reduced stress level desired by design to reduce reliability issues and structural defects in the thin film layer. Simply discovering the optimum or workable ranges absent evidence indication such stress level is critical is not inventive. Furthermore MPEP 2144.05 states it is not inventive to discover the optimum or workable ranges by routine experimentation.
Claims 11-12 & 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Mutyala, Uemura, & Shimoda et al. (US 2012/0064302) [Hereinafter Shimoda].
Regarding claim 11, Mutyala teaches A semiconductor processing method comprising:
providing deposition precursors [para 4-5] to a processing region [fig. 1, processing volume 120, para 20] of a semiconductor processing chamber [fig. 1, processing chamber 100, para 20],
wherein the deposition precursors comprise a silicon-containing precursor and [para 5, “the silicon-containing precursor may be or include tetraethyl orthosilicate” which contains silicon, carbon, and hydrogen Si(OC2H5)4],
wherein a substrate [fig. 1, substrate 103, para 20] is disposed within the processing region [fig. 1, 102];
forming plasma effluents of the deposition precursors [para 5, wherein oxygen radicalized are plasma effluents, “The semiconductor substrate may be or include silicon, and forming the plasma of the oxygen-containing precursor may produce an oxygen-radicalized surface termination of the silicon of the semiconductor substrate.”];
and depositing a layer of silicon-containing material on the substrate [para 4, “The methods may include depositing a silicon-containing material on the semiconductor substrate.”],
a dielectric constant of less than or about 4.0 [para 17, silicon oxide; wherein silicon oxide dielectric constant is approximately 3.9].
Mutyala fails to explicitly disclose a dopant-containing precursor;
wherein the layer of silicon-containing material is characterized by a density of greater than or about 2.30 g/cm3.
While Mutyala notes the silicon containing material comprise silicon oxide.
Uemura teaches where silicon oxide comprises a density in the 2.2g/cm3 to 2.6g/cm3 [para 10].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the silicon oxide to comprise a density of greater than or about 2.50 g/cm3. Furthermore MPEP 2144.05 states in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.
Mutyala/Uemura fails to explicitly disclose a breakdown voltage of greater than or about 6.0 MV/cm.
However, Shimoda teaches a breakdown voltage of greater than or about 6.0 MV/cm [para 81, “The pattern of the silicon oxide film formed by the method of the present invention is a very fine film having high homogeneity and shows a high breakdown voltage as compared with a silicon oxide film formed by the known sol-gel process. . . . its breakdown voltage can be set to not less than 6 MV/cm . . .”].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the silicon containing material characterized by a breakdown voltage of greater than or about 6.0 MV/cm to prevent short-circuiting between elements.
Regarding claim 12, Mutyala/Uemura/Shimoda teaches The semiconductor processing method of claim 11,
wherein the silicon- containing precursor comprises a silicon-carbon-and-hydrogen-containing precursor or a silicon- oxygen-carbon-and-hydrogen-containing precursor [Mutyala, para 5, “the silicon-containing precursor may be or include tetraethyl orthosilicate” which contains silicon, carbon, and hydrogen Si(OC2H5)4].
Regarding claim 15, Mutyala/Uemura/Shimoda teaches The semiconductor processing method of claim 11, wherein the layer of silicon-containing material is characterized by a breakdown voltage of greater than or about 6.0 MV/cm [Shimoda, para 81, “The pattern of the silicon oxide film formed by the method of the present invention is a very fine film having high homogeneity and shows a high breakdown voltage as compared with a silicon oxide film formed by the known sol-gel process. . . . its breakdown voltage can be set to not less than 6 MV/cm . . .”].
Regarding claim 16, Mutyala/Uemura/Shimoda teaches The semiconductor processing method of claim 11,
wherein the layer of silicon-containing material is characterized by a dielectric constant of less than or about 3.3 [Mutyala, para 17, silicon oxide; wherein silicon oxide dielectric constant is approximately 3.9 which is about 3.3 absent a showing that the claimed proportions were critical]. Moreover MPEP 2144.05 states, “a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close… the claimed ranges are virtually negligible absent any showing of unexpected results or criticality.”
Regarding claim 17, Mutyala/Uemura/Shimoda teaches The semiconductor processing method of claim 11,
wherein a temperature within the processing region is maintained at less than or about 500 °C [Mutyala, para 32, “Consequently, many conventional operations perform these depositions at relatively high temperatures, such as greater than or about 400° C., or greater than or about 500° C.”].
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Mutyala, Uemura, & Shimoda as applied to claims 11-12 & 15-17 and further in view of Yang.
Regarding claim 13, Mutyala/Uemura/Shimoda teaches The semiconductor processing method of claim 11.
Mutyala/Uemura/Shimoda fails to explicitly teach wherein the dopant precursor comprises a boron-containing precursor.
However Yang teaches wherein the boron-containing precursor comprises diborane (B2H6) [para 43, “In specific embodiments, the chemical vapor deposition process comprises flowing silane and diborane into the chamber.”].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the method to comprise a boron containing precursor such as diborane to include doping semiconductor materials thereby lowering the deposition temperature needed while enhancing the deposition rate.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Mutyala, Uemura, & Shimoda as applied to claims 11-12 & 15-17 and further in view of Gadre et al. (US 2018/0350596) [Hereinafter Gadre].
Regarding claim 14, Mutyala/Uemura/Shimoda teaches The semiconductor processing method of claim 11.
Mutyala/Uemura/Shimoda fails to explicitly disclose wherein a flow rate of the dopant precursor is less than or about 1,000 sccm.
However Gadre teaches wherein a flow rate of the dopant precursor is less than or about 1,000 sccm [para 29, “In general, the following exemplary deposition process parameters may be used to form the boron-doped amorphous silicon layer…The flow rate of the boron-containing gas mixture may be from about 10 sccm to about 1,000 sccm, for example, between about 50 sccm and about 800 sccm”].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the dopant precursor to be less than or about 1,000 sccm as taught by the overlapping range of Gadre. Furthermore MPEP 2144.05 states in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.
Claims 18 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mutyala, An, & Lin (CN 115188709A) [Hereinafter Lin].
Regarding claim 18 Mutyala teaches A semiconductor processing method comprising:
providing deposition precursors [para 4-5] to a processing region [fig. 1, processing volume 120, para 20] of a semiconductor processing chamber [fig. 1, processing chamber 100, para 20],
wherein the deposition precursors comprise a silicon containing precursor [para 5, “the silicon-containing precursor may be or include tetraethyl orthosilicate” which contains silicon, carbon, and hydrogen Si(OC2H5)4],
wherein a substrate [fig. 1, substrate 103, para 20] is disposed within the processing region [fig. 1, 102];
forming plasma effluents of the deposition precursors [para 5, wherein oxygen radicalized are plasma effluents, “The semiconductor substrate may be or include silicon, and forming the plasma of the oxygen-containing precursor may produce an oxygen-radicalized surface termination of the silicon of the semiconductor substrate.”] ;
and depositing a layer of silicon-containing material on the substrate [para 4, “The methods may include depositing a silicon-containing material on the semiconductor substrate.”].
Mutyala fails to explicitly disclose
and wherein the layer of silicon-containing material is characterized by a density of greater than or about 2.50 g/cm3.
However An teaches a density of greater than or about 2.65 g/cm3 [“As shown in FIG. 14, all of the silicon oxide films manufactured at different process temperatures had a density of 2.2 g/cm3 or more, and similar to the density of SiO2 bulk (2.68 g/cm3 ), confirming that a high-quality thin film was formed. That is, since the silicon oxide film of the present invention has a density similar to that of SiO2 bulk, excellent corrosion resistance can be expected.”].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the density to be 2.2 g/cm3 or more for excellent corrosion resistance as taught by An. Furthermore In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. (MPEP 2144.05).
Mutyala/An fails to explicitly disclose wherein the deposition precursor comprises a boron-containing precursor
wherein the layer of silicon-containing material is characterized by a dielectric constant of less than or about 3.5.
However, Lin teaches wherein the deposition precursor comprises a boron-containing precursor [ “The dopant precursor is . . . a boron nitride precursor . . . the boron nitride precursor is the following A mixture of one or more of: ammonia, nitrogen, nitric oxide, nitrogen dioxide, nitrous oxide, carborane, diborane, proporane, butaborane, pentaborane, hexborane, Boron trichloride, boron tribromide, etc.”]
wherein the layer of silicon-containing material is characterized by a dielectric constant of less than or about 3.5 [“The industry has successfully developed the ability to deposit a variety of low-k films, including . . .carbon-doped silicon oxide (eg, Black Diamond) . . . Black Diamond film is a silicon oxide based chemical vapor deposited film with an effective dielectric constant less than 3.0.”].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention wherein the deposition precursor comprises a boron-containing precursor and for the silicon containing material to be characterized by a dielectric constant less than 3.0 to serve as a layer that prevents electronic crosstalk and minimizes signal delays in high-frequency circuits. Furthermore in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists (MPEP 2144.05).
Regarding claim 20, Mutyala/An/Lin teaches The semiconductor processing method of claim 18,
wherein the layer of silicon-containing material is characterized by a boron concentration of less than or about 20.0 at.% [Mutyala teaches wherein the silicon-containing material is silicon oxide in para 17 which comprises 0% of boron concentration].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention wherein the layer of silicon-containing material is characterized by a boron concentration of less than or about 20.0 at.%. Moreover MPEP 2144.05 states in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Mutyala, An, & Lin as applied to claims 18 & 20 and further in view of Guo.
Regarding claim 19, Mutyala/An/Lin teaches The semiconductor processing method of claim 18.
Mutyala/An/Lin fails to explicitly disclose exposing the layer of silicon-containing material to ultraviolet light to provide a cured layer of silicon-containing material.
Guo teaches exposing the layer of silicon-containing material [fig. 1C/1E, silicon containing second layer 130, para 34] to ultraviolet light to provide a cured layer of silicon-containing material [para 34, “The second layer 130 is converted to a cured composition 131, as depicted in FIG. 1E. The curing process drives out unwanted solvents from the second layer 130, solidifies and stabilizes the second layer, and can also modify chemical and optical properties of the second layer, converting the second later to the cured composition 131. The curing process or treatment can be… an ultraviolet (UV) curing process”].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to cure the silicon-containing material to ultraviolet light to reduce the stress and drive out unwanted solvents to reduce defects within the thin film.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FELIX B ANDREWS whose telephone number is (703)756-1074. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm ET.
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/FELIX B ANDREWS/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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