Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 7 is objected to because of the following informalities: the status identifier is improper. Per MPEP 714, “In the claim listing, the status of every claim must be indicated after its claim number by using one of the following identifiers in a parenthetical expression: (Original), (Currently amended), (Canceled), (Withdrawn), (Previously presented), (New), and (Not entered).” For the sake of compact prosecution, claim 7 is interpreted in the instant Office action as follows: the status identifier is found to be a typographical error and is equivalent to “Currently Amended” based on Applicant’s remarks at pg. 9. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20210098380 A1) in view of Fang (US 20170186737 A1).
Regarding claim 1, Chen discloses a package-on-package (POP) structure (Fig. 22), comprising:
a first package unit (350), wherein the first package unit comprises a three-dimensional fan-out memory device ([0077]: “stacked memory dies” inclusive therein); and
a system-in-package (SiP) package unit (200), wherein the SIP package unit comprises a two-dimensional fan-out peripheral circuit ([0047]: “integrated fan-out (InFO) packages”);
wherein the first package unit and the SiP package unit are bonded together (bonded by 252);
wherein the three-dimensional fan-out memory device comprises:
at least two memory chips (310A, 310B) laminated stacked in a stepped configuration having one step surface for each of the at least two memory chips (at least one step is shown, thus encompassing “one step surface”), wherein each of the at least two memory chips is provided with one bonding pad (See annotated figure below, where bonding wires interface with the chips) arranged on said one step surface of the stepped configuration;
[…]
a first encapsulating layer (314), which encapsulates the at least two memory chips (fully encapsulates) […] a first surface of the first encapsulating layer (314-S1);
a first rewiring layer (302) having a first surface (302-S1) and a second surface (302-S2), wherein the second surface of the first rewiring layer is formed on the first surface of the first encapsulating layer (directly on) […]; and
first metal bumps (252), formed on the first surface of the first rewiring layer; wherein the two-dimensional fan-out peripheral circuit comprises:
a second rewiring layer (222) having a first surface (222-S1) and a second surface (222-S2); at least one peripheral circuit chip (50/100), arranged in two dimensions (into/out of the page dimension and lateral dimension) and electrically connected with the first surface of the second rewiring layer (connected at least by 46/130);
second metal connection pillars (216), disposed outside of the at least one peripheral circuit chip (216 is not within 50/100), wherein each of the second metal connection pillars has a first end (216-E1) electrically connected with the first surface of the second rewiring layer (directly connected);
a second encapsulating layer (220), encapsulating the at least one peripheral circuit chip and the second metal connection pillars (fully encapsulating), wherein a second end of the second metal connection pillars (216-TS) are exposed from a top surface of the second encapsulating layer (exposed at 220-TS; exposure shown occurring at the method step of Fig. 12 which is consistent with “grinding” in [0039] of Applicant’s disclosure);
second metal bumps (250), formed on the second surface of the second rewiring layer (directly on);
and a third rewiring layer (206) having a first surface (206-S1) and a second surface (206-S2), wherein the first surface bonds to the first metal bumps (directly bonded), and the second surface is bonded to the at least one peripheral circuit chip (directly bonded) and electrically connected to the exposed second end of the second metal connection pillars (connected through the body of 216);
wherein the first package unit and the SiP package unit are attached by the third rewiring layer (units 350 and 200 are attached to each other by the third rewiring layer 206 because 206 includes bonding/attaching sites for bumps 252) to form the POP structure.
Illustrated below is a marked and annotated figure of Fig. 22 of Chen.
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Chen fails to teach “first metal connection pillars, wherein each of the first metal connection pillars is formed on and electrically connected to said bonding pad in one-to-one correspondence; a first encapsulating layer, which encapsulates the at least two memory chips and the first metal connection pillars, wherein top surfaces of the first metal connection pillars are exposed from a first surface of the first encapsulating layer; a first rewiring layer having a first surface and a second surface, wherein the second surface of the first rewiring layer is formed on the first surface of the first encapsulating layer, wherein the first rewiring layer is electrically connected to the top surfaces of first metal connection pillars”.
Fang discloses first metal connection pillars (Fig. 1: 122/129), wherein each of the first metal connection pillars is formed on and electrically connected to said bonding pad (113) in one-to-one correspondence;
a first encapsulating layer (130), which encapsulates the at least two memory chips (fully encapsulates memory chips 111; [0016]: “memory”) and the first metal connection pillars (fully encapsulates), wherein top surfaces of the first metal connection pillars (Top Surfaces, See annotated figure) are exposed from a first surface of the first encapsulating layer (exposed at 130-S1; exposure occurring at the method step of Fig. 2E which is consistent with “grinding” in [0036] of Applicant’s disclosure);
a first rewiring layer (140) having a first surface (140-S1) and a second surface (140-S2), wherein the second surface of the first rewiring layer is formed on the first surface of the first encapsulating layer (directly on), wherein the first rewiring layer is electrically connected to the top surfaces of first metal connection pillars (directly connected).
Modifying the structure of the first package unit of Chen by incorporating the first metal connection pillars of Fang in the same way would arrive at the claimed first metal connection pillar configuration. Fang provides a teaching to motivate one to incorporate the first metal connection pillars in that it would reduce manufacturing defects induced by the first encapsulating layer (Abstract: “the package has better resistance against mold flow impact to effectively reduce the risk of wire sweeping”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed first metal connection pillar configuration because it would reduce manufacturing defects. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 1 of Fang.
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Regarding claim 2, Chen in view of Fang discloses the POP structure according to claim 1, wherein a material of the first metal connection pillars comprises at least one of gold, silver, aluminum, and copper (Fang: [0017]; “metals with high conductivity such as copper or gold”); and wherein a material of the second metal connection pillars comprises at least one of gold, silver, aluminum, and copper (Chen: [0055]: “a metal, like copper, titanium, tungsten, aluminum, or the like”).
Regarding claim 3, Chen in view of Fang discloses the POP structure according to claim 1, wherein […] a material of the first encapsulating layer comprises one of polyimide, silicone, and epoxy resin (Chen: [0082]: “epoxy”; similarly Fang: [0018]: “epoxy”), and a material of the second encapsulating layer comprises one of polyimide, silicone, and epoxy resin (Chen: [0059]: “epoxy”).
Chen in view of Fang teaches the bonding pad but fails to teach “a material of the bonding pad comprises metallic aluminum”. However, teaches a finite selection of materials useful for other bonding pads, the finite selection comprises metallic aluminum (Chen: [0018]: “aluminum pads”). Modifying the material of the bonding pad by choosing metallic aluminum from the finite selection of materials useful for pads would arrive at the claimed bonding pad configuration.
Since the other bonding pads of Chen are performing the same function as the bonding pads, a person having ordinary skill in the art before the effective filing date would have readily recognized the finite number of predictable solutions for material selection. These predictable solutions include metallic aluminum as this may be chosen from a finite number of identified, predictable solutions (Chen: [0018]). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to try using a different material for the bonding pad. Thus, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1385 (Supreme Court 2007) (KSR). MPEP 2143 (1)(E).
Regarding claim 4, Chen in view of Fang discloses the POP structure according to claim 1, wherein each of the first rewiring layer, the second rewiring layer, and the third rewiring layer comprises a dielectric layer (Fang: Fig. 1: 142; Chen: Fig. 22: 224; Chen: Fig. 22: 208; respectively) and a metal wiring layer (Fang: Fig. 1: 141; Chen: Fig. 22: 226; Chen: Fig. 22: 210; respectively); wherein a material of the dielectric layer comprises one or a combination of two or more of epoxy resin, silicone, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), silicon oxide, phosphorosilicate glass, and fluorine-containing glass (Fang: [0019]: “polyimide”; Chen: [0062]: “polyimide”; Chen: [0051]: “polyimide”), and a material of the metal wiring layer comprises one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium (Fang: [0019]: “titanium/copper/copper/nickel/gold”; Chen: [0063]: “a metal, like copper, titanium, tungsten, aluminum, or the like”; Chen: [0052]: “a metal, like copper, titanium, tungsten, aluminum, or the like”).
Regarding claim 5, Chen in view of Fang discloses the POP structure according to claim 1, wherein one of the first metal bumps or one of the second metal bumps comprises a connecting structure, which includes a solder ball, or a metal pillar, or a solder ball formed on the metal pillar (Chen: [0075]: “a similar material as the conductive connectors 250”; [0070]: “metal pillars…metal cap layer” being “a solder ball formed on the metal pillar”), wherein the solder ball comprises one of a gold-tin solder ball, a silver-tin solder ball, and a copper-tin solder ball (Chen: [0070]: “tin…gold, silver…the like, or a combination thereof”).
Regarding independent claim 6, Chen discloses a method of packaging a package-on-package (POP) structure (Fig. 22), comprising:
forming a first package unit (350) comprising a three-dimensional fan-out memory device ([0077]: “stacked memory dies” inclusive therein); and forming a system-in-package (SiP) package unit (200) comprising a two-dimensional fan-out peripheral circuit ([0047]: “integrated fan-out (InFO) packages”);
wherein forming the first package unit of the three-dimensional fan-out memory device comprises:
providing at least two memory chips (310A, 310B) laminated in a stepped configuration having one step surface for each of the at least two memory chips (at least one step is shown, thus encompassing “one step surface”), wherein each of the at least two memory chips is provided with one of bonding pads (See annotated figure below, where bonding wires interface with the chips) arranged on one of step surfaces of the stepped configuration;
[…]
forming a first encapsulating layer (314), wherein the first encapsulating layer encapsulates the at least two memory chips (fully encapsulates) […] a first surface of the first encapsulating layer (314-S1);
forming a first rewiring layer (302) having a first surface (302-S1) and a second surface (302-S2), wherein the second surface of the first rewiring layer is formed on the first surface of the first encapsulating layer (directly on) […]; and
forming first metal bumps (252) on the first surface of the first rewiring layer;
wherein forming the SiP package unit of the two-dimensional fan-out peripheral circuit comprises:
forming a second rewiring layer (222) having a first surface (222-S1) and a second surface (222-S2);
providing at least one peripheral circuit chip (50/100), wherein the at least one peripheral circuit chip is arranged in two dimensions (into/out of the page dimension and lateral dimension) and electrically connected with the first surface of the second rewiring layer (connected at least by 46/130);
forming second metal connection pillars (216), wherein the second metal connection pillars are disposed outside of the at least one peripheral circuit chip (216 is not within 50/100), wherein each of the second metal connection pillars has a first end (216-E1) electrically connected with the first surface of the second rewiring layer (directly connected);
forming a second encapsulating layer (220), wherein the second encapsulating layer encapsulates the at least one peripheral circuit chip and the second metal connection pillars (fully encapsulating), wherein top surfaces of the second metal connection pillars (216-TS) are exposed from the second encapsulating layer (exposed at 220-TS; exposure shown occurring at the method step of Fig. 12 which is consistent with “grinding” in [0039] of Applicant’s disclosure);
forming second metal bumps (250), wherein the second metal bumps are disposed on the second surface of the second rewiring layer (directly on);
forming a third rewiring layer (206) having a first surface (206-S1) and a second surface (206-S2), bonding the first surface to the first metal bumps (directly bonded), and bonding the second surface to the at least one peripheral circuit chip (directly bonded) and electrically connecting to the exposed second end of the second metal connection pillars (connected through the body of 216); and
attaching the first package unit and the SiP package unit by the third rewiring layer (units 350 and 200 are attached to each other by the third rewiring layer 206 because 206 includes bonding/attaching sites for bumps 252) to form the POP structure.
Chen fails to teach the method “forming first metal connection pillars, wherein each of the first metal connection pillars is disposed on and electrically connected to said bonding pad in one-to-one correspondence; forming a first encapsulating layer, wherein the first encapsulating layer encapsulates the at least two memory chips and the first metal connection pillars, wherein top surfaces of the first metal connection pillars are exposed from a first surface of the first encapsulating layer; forming a first rewiring layer having a first surface and a second surface, wherein the second surface of the first rewiring layer is formed on the first surface of the first encapsulating layer, and wherein the first rewiring layer is electrically connected to the first metal connection pillars”.
Fang discloses a method forming first metal connection pillars (Fig. 1: 122/129), wherein each of the first metal connection pillars is disposed on and electrically connected to said bonding pad (113) in one-to-one correspondence;
forming a first encapsulating layer (130), wherein the first encapsulating layer encapsulates the at least two memory chips (fully encapsulates memory chips 111; [0016]: “memory”) and the first metal connection pillars (fully encapsulates), wherein top surfaces of the first metal connection pillars (Top Surfaces, See annotated figure below) are exposed from a first surface of the first encapsulating layer (exposed at 130-S1; exposure occurring at the method step of Fig. 2E which is consistent with “grinding” in [0036] of Applicant’s disclosure);
forming a first rewiring layer (140) having a first surface (140-S1) and a second surface (140-S2), wherein the second surface of the first rewiring layer is formed on the first surface of the first encapsulating layer (directly on), and wherein the first rewiring layer is electrically connected to the first metal connection pillars (directly connected).
Modifying the method of forming the first package unit of Chen, by incorporating the method of forming the first metal connection pillars of Fang in the same way, would arrive at the claimed method. Fang provides a teaching to motivate one to incorporate the method configuration “forming first metal connection pillars” in that it would reduce manufacturing defects induced by the first encapsulating layer (Abstract: “the package has better resistance against mold flow impact to effectively reduce the risk of wire sweeping”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed method because it would reduce manufacturing defects. MPEP 2143 (I)(G).
Regarding claim 7, Chen in view of Fang discloses the method of packaging the POP structure according to claim 6, wherein forming the first package unit of the three-dimensional fan-out memory device comprises:
providing at least two memory chips (Chen: [0077]: “one or more stacked dies” fully encompassing the claimed range) each having one of the bonding pads (Fang: Fig. 1: 113), and laminating the at least two memory chips in the stepped configuration (Fang: [0016]: “stair-like stacking”);
forming the first metal connection pillars on the bonding pads, respectively (Fang: Fig. 2B);
encapsulating the at least two memory chips and the first metal connection pillars by the first encapsulating layer (Fang: Fig. 2D), exposing top surfaces of the first metal connection pillars from the first surface of the first encapsulating layer (Fang: exposure occurring at the method step of Fig. 2E which is consistent with “grinding” in [0036] of Applicant’s disclosure);
forming the first rewiring layer on the first surface of the first encapsulating layer (Fang: Fig. 2G), wherein the first metal connection pillars are electrically connected to the first rewiring layer (Fang: directly connected); and
forming the first metal bumps on the first surface of the first rewiring layer (Fang: [0029]: “After the disposition of the redistribution wiring mechanism 140, a plurality of external terminals 160 are bonded onto the redistribution layer 140”).
Regarding claim 8, Chen in view of Fang discloses the method of packaging the POP structure according to claim 7, wherein the laminating of the at least two memory chips is realized by a surface mount process (surfaces of each 111 are directly mutually mounted, thus a surface mounting process consistent with Fig. 1 of Applicant’s disclosure).
Regarding claim 9, Chen in view of Fang discloses the method of packaging the POP structure according to claim 6, wherein forming the SiP package unit of the two-dimensional fan-out peripheral circuit comprises:
forming the second rewiring layer having the first surface and the second surface (Chen: Fig. 13);
electrically connecting the at least one peripheral circuit chip to the first surface of the second rewiring layer (at least by 46/130);
electrically connecting the second metal connection pillars to the first surface of the second rewiring layer (directly connecting), wherein the second metal connection pillars are formed outside of the at least one peripheral circuit chip (Chen: Fig. 10: 216 is not within 50/100);
encapsulating the at least one peripheral circuit chip and the second metal connection pillars using the second encapsulating layer (Chen: Fig. 11);
forming the third rewiring layer on the at least one peripheral circuit chip and the second metal connection pillars (Chen: Fig. 20: at least some method steps are required to complete 206 after providing 50/100 and 216, as shown by positioning of 252 and the openings formed therefore, thus “forming”), wherein the third rewiring layer is bonded to the at least one peripheral circuit chip (at least by 218), and the second metal connection pillars are electrically connected with the second surface of the third rewiring layer (directly connected); and
forming the second metal bumps on the second surface of the second rewiring layer (Fang: [0029]: “After the disposition of the redistribution wiring mechanism 140, a plurality of external terminals 160 are bonded onto the redistribution layer 140”).
Regarding claim 10: Chen in view of Fang discloses the method of packaging the POP structure according to claim 6, further comprising polishing the top surfaces of the first encapsulating layer and the second encapsulating layer after forming the first encapsulating layer and the second encapsulating layer (Fang: Fig. 2E: [0028]: “a grinding process”).
Response to Arguments
Applicant's arguments filed 12/1/2025 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to claim 1 that “Fang does not teach how to bond the three dimensional fan-out memory package unit and the two-dimensional fan-out peripheral circuit chip SiP package unit together by the third rewiring layer”. Remarks at pg. 13.
Examiner’s reply:
The examiner does not find the argument persuasive. Fang is relied upon to teach a configuration within the first package. Chen already teaches the means of bonding the memory package unit to the SiP package unit (Fig. 22: bumps 252). The configuration disclosed by Fang would not require any changes to Chen’s bonding means because in each case the first package is bonded by similar means (Chen: Fig. 22: bumps 252; Fang: Fig. 1: bumps 160). Thus, the bonding means of Chen would be used in the same way as before, regardless of the configuration within the first package. Accordingly, the rejection is maintained in substantially the same way as before.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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