DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous rejection: claims 1 through 12 rejected, claims 13 through 20 withdrawn.
Present rejection: claims 1 through 12 rejected, claims 13 through 20 withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/12/2026 was filed after the mailing date of the non-final rejection on 1/8/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Applicant is advised that should claim 1 be found allowable, claim 5 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim 5 recites “a center of each circuit probing pad is disposed on and aligned with the boundary between the die region and the scribe line region” and is therefore substantially the same as claim 1 lines 17 and 18.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 through 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 through 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
Claim 1 recites “equal to a distance the second edge of the second portion of each of the circuit probing pads and the boundary” in line 16.
The limitation omits the relationship term, the examiner suggests “equal to a distance between the second edge of the second portion of each of the circuit probing pads and the boundary”
Claim 1 recites the limitation "the circuit probing pads" in line 11. There is insufficient antecedent basis for this limitation in the claim. The claim previously referred to “one or more circuit probing pads”, which has a different scope.
Claim 1 recites the limitation "the circuit probing pads" in line 15. There is insufficient antecedent basis for this limitation in the claim. The claim previously referred to “one or more circuit probing pads”, which has a different scope.
Claim 1 recites the limitation "the second edges" in line 20. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites the limitation "the second portions" in line 21. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites “the first top surface of the scribe line region” in line 12. There is insufficient antecedent basis for this limitation because previously the claim has stated “a first top surface of the die region” in line 6. It is therefore unclear whether the limitation is referring to the first top surface of the die region, the second top surface of the scribe line region, or a previously unmentioned top surface.
Claim 1 recites the limitation "the second edge" in line 12. There is insufficient antecedent basis for this limitation in the claim. The antecedent recite “an opposed second edge” in line 10.
Claim 5 recites “a center of each circuit probing pad” in lines 1 and 2. It is unclear if this refers to the same “center of each circuit probing pad” recited in claim 1 line 17.
Claim 6 recites “a center of each circuit probing pad” in lines 1 and 2. It is unclear if this refers to the same “a center of each circuit probing pad” recited in claim 1 line 17. Further, it is unclear how the center can be disposed away from the die region (claim 6) and disposed on the boundary (claim 1 line 18) simultaneously. The center will be understood to be disposed on the boundary.
Claim 7 recites “a center of each circuit probing pad” in lines 1 and 2. It is unclear if this refers to the same “a center of each circuit probing pad” recited in claim 1 line 17.
Claims 2 through 12 depend from and incorporate claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 6, 7, and 12 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Nakamura (US 5982042)
Regarding claim 1.
Nakamura teaches a scribe line structure, comprising: a die region (fig 1:1a; [column 4 lines 45-50]), disposed on a semiconductor wafer (fig 1:1; [column 4 lines 40-45]); a scribe line region (fig 2; [column 4 lines 45-50]), surrounding the die region (fig 1:1a; [column 4 lines 45-50]) to define a boundary between an edge of the die region (fig 1:1a; [column 4 lines 45-50]) and the scribe line region (fig 1; [column 4 lines 45-50]), and a safe margin between a center line of the scribe line region (fig 1,2; [column 4 lines 45-50]) and the edge of the die region (fig 1:1a; [column 4 lines 45-50]); and one or more circuit probing pads (fig 1:2,3; [column 4 lines 50-55]), disposed on a first top surface of the die region (fig 1,2:1a; [column 4 lines 45-50]) and a second top surface of the scribe line region (fig 1,2:6; [column 4 lines 50-60]) and disposed on the boundary to define a first portion (fig 1:2; [column 4 lines 45-50]) of each circuit probing pad on the first top surface of the die region (fig 2:1a; [column 4 lines 45-50]) and a second portion (fig 1:3; [column 4 lines 45-50]) of each circuit probing pad on the second top surface of the scribe line region (fig 2; [column 4 lines 45-50]), wherein each of the circuit probing pads (fig 1:2,3; [column 4 lines 50-55]) further has a first edge defined at the first portion (fig 1:2; [column 4 lines 50-55]) and an opposed second edge defined at the second portion (fig 1:3; [column 4 lines 50-55]), wherein the first edge of the first portion (fig 1:2; [column 4 lines 50-55]) of each of the circuit probing pads (fig 1:2,3; [column 4 lines 50-55]) is disposed within the first top surface of the scribe line region (fig 2; [column 4 lines 50-55]), wherein the second edge of the second portion (fig 1:3; [column 4 lines 50-55]) of each circuit probing pad (fig 1:2,3; [column 4 lines 50-55]) is disposed within the safe margin and is spaced apart from the center line of the scribe line region (fig 1,2; [column 4 lines 50-55]); wherein a distance between the first edge of the first portion (fig 1:2; [column 4 lines 50-55]) of each of the circuit probing pads and the boundary is equal to a distance the second edge of the second portion (fig 1:3; [column 4 lines 50-55]) of each of the circuit probing pads and the boundary (annotated figure 1,2), such that a center of each of the circuit probing pads (fig 1:2,3; [column 4 lines 50-55]) is disposed on the boundary; wherein the scribe line region (fig 1,2; [column 4 lines 50-55]) further has a dicing path (fig 1,2:6; [column 4 lines 50-55]) aligned with the center line of the scribe line region, wherein the dicing path (fig 1,2:6; [column 4 lines 50-55]) is spaced apart from the second edges of the second portions of the one or more circuit probing pads (fig 1,2:2,3; [column 4 lines 50-55]).
PNG
media_image1.png
569
607
media_image1.png
Greyscale
PNG
media_image2.png
467
755
media_image2.png
Greyscale
Regarding claim 2.
Nakamura teaches the scribe line structure of Claim 1, wherein the die region (fig 1:1a; [column 4 lines 45-50]) comprises functional circuitry ([column 4 line 45]), and the scribe line region is a non-functional region ([column 4 line 47]).
Regarding claim 5
Nakumura teaches the scribe line structure of Claim 1, wherein a center of each circuit probing pad (fig 1:2,3; [column 4 lines 50-55]) is disposed on and aligned with the boundary between the die region (fig 1:1a; [column 4 lines 50-55]) and the scribe line region (annotated figure 1 above).
Regarding claim 6.
Nakamura teaches the scribe line structure of Claim 1, wherein a center of each circuit probing pad (fig 1:2,3; [column 4 lines 50-55]) is disposed away from the die region (fig 1:1a; [column 4 lines 50-55]) with reference to the center line of the scribe line region (annotated figure 1,2).
Note: the center is on the boundary
Regarding claim 7.
Nakamura teaches the scribe line structure of Claim 1, wherein a center of each circuit probing pad (fig 1:2,3; [column 4 lines 50-55]) is disposed closer to the die region (fig 1:1a; [column 4 lines 50-55]) with reference to the center line of the scribe line region (annotated figure 1,2).
Note: the center is on the boundary
Regarding claim 12.
Nakamura teaches the scribe line structure of Claim 1, wherein the first top surface of the die region (fig 1,2:1a; [column 4 lines 50-55]) and the second top surface of the scribe line region are coplanar (annotated fig 2).
PNG
media_image3.png
239
765
media_image3.png
Greyscale
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 4, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 5982042) as applied to claim 2 and further in view of Kim (US 6159826).
Regarding claim 3.
Nakamura teaches the scribe line structure of Claim 2 above
Nakamura does not state that the pad is connected to functional circuitry.
Kim teaches the first portion (fig 5:56a; [column 3 lines 40-45]) of each circuit probing pad (fig 5:56; [column 3 lines 35-40]) is electrically connected (fig 5:52a; [column 3 lines 35-40]) to the functional circuitry (fig 5:52; [column 3 lines 30-35]) of the die region (fig 5:32; [column 3 lines 25-30]).
It would have been obvious to one of ordinary skill in the before the effective filing date of the claimed invention to connect the pad to circuitry so that voltage can be conducted from the pad to the circuitry for the purposes of testing the die (Kim column 3 lines 50-60).
Regarding claim 4.
Nakamura in view of Kim teaches the scribe line structure of Claim 3, further:
Kim teaches the functional circuitry (fig 5:52; [column 3 lines 30-35]) of the die region (fig 5:32; [column 3 lines 25-30]) is tested via one or more circuit probing needles (fig 5:60; [column 5 lines 50-55]) electrically connected to external test equipment and placed on the one or more circuit probing pads (fig 5:56; [column 3 lines 50-55]).
Regarding claim 8.
Nakamura in view of Kim teaches the scribe line structure of Claim 4, further:
Nakamura teaches the semiconductor wafer (fig 1:1; [column 4 lines 40-45]) is arranged to be diced (fig 21,22; [column 1 line 44]) along the dicing path (fig 1,2:6; [column 4 lines 45-50]) to dice the scribe line region from the die region (fig 1,22:1a; [column 1 lines40-50]) and to form a diced portion (fig 21,22:6; [column 1 lines 40-50]) of the scribe line region and a remaining portion of the scribe line region attached to the die region (fig 22:1a; [column 1 lines 40-50]), wherein after the semiconductor wafer (fig 21,22:1; [column 1 lines 40-50]) is diced, the first portion of each circuit probing pad (fig 22:2; [column 1 lines 40-50]) is not damaged (fig 22), while the second portion (fig 21,22:3; [column 1 lines 40-50]) of each circuit probing pad is diced to form a remaining circuit probing pad (fig 22:2,3a; [column 1 lines 40-50]) remaining on the remaining portion of the scribe line region and the die region (fig 22:1a; [column 1 lines 40-50]), wherein the remaining circuit probing pad (fig 22:2,3a; [column 1 lines 40-50]) includes the first portion (fig 22:2; [column 1 lines 40-50]) disposed on the first top surface of the die region (fig 22:1a; [column 1 lines 40-50]) and a remaining second portion (fig 22:3a; [column 1 lines 40-50]) disposed on the second top surface of a kerf section of the scribe line region.
PNG
media_image4.png
359
531
media_image4.png
Greyscale
Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 5982042) in view of Kim (US 6159826) as applied to claim 8 and further in view of Uehling (US 2013/0299947).
Regarding claim 9.
Nakamura in view of Kim teaches the scribe line structure of Claim 8, further:
Nakamura teaches the die region (fig 22:1a; [column 1 lines 40-50]) and the remaining portion of the scribe line region with each remaining circuit probing pad (fig 22:2,3a; [column 1 lines 40-50])
Nakamura in view of Kim does not teach a package.
Uehling teaches the die region (fig 3:260; [para 0019]) and the remaining portion of the scribe line region (fig 3:122; [para 0008]) are packaged into a semiconductor chip package (fig 3:264; [para 0019]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to package the die in order to protect the die and prepare the structure for subsequent assembly.
Regarding claim 10.
Nakamura in view of Kim in view of Uehling teaches the scribe line structure of Claim 9, further:
Kim teaches a size of each remaining circuit probing pad (fig 22:2,3a; [column 1 lines 40-50]) is smaller than a size of each circuit probing pad (fig 21:2,3; [column 1 lines 40-50]), wherein a width of the remaining second portion (fig 22:3a; [column 1 lines 40-50]) is smaller than the width of the first portion (fig 22:2; [column 1 lines 40-50]) of each circuit probing pad (fig 22:2,3a; [column 1 lines 40-50]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 5982042) in view of Kim (US 6159826) as applied to claim 1 and further in view of Uehling (US 2013/0299947).
Regarding claim 11.
Nakamura in view of Kim teaches the scribe line structure of claim 1.
Nakamura in view of Kim does not teach wire bonding the die to a substrate.
Uehling teaches the die region (110,112) is electrically connected to a substrate via wire bonding (fig 3) (paragraph 19).
PNG
media_image5.png
166
341
media_image5.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to wire bond the die to a substrate in order to conduct voltage from external connector to the die and thereby enable packaging of the device for protection and further assembly.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 through 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Previous rejections over rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite are withdrawn. New rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite are above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 19, 2026