DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10, 12-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Schmidt et al. (US 2011/0133304 A1; hereafter Schmidt) in view of Wang et al. (US 2005/0114824 A1; hereafter Wang) and Shih et al. (US 2019/0371749 A1; hereafter Shih).
Regarding claim 1, Schmidt teaches a method for dummy die placement on a bonding wafer (see e.g., Figures 1-3), comprising:
receiving bonding wafer parameters for the bonding wafer (see e.g., layer 101, which is formed on or as part of the substrate 100, a semiconductor wafer. The substrate 100 has functional areas 110, 105 and 115, the physical location of functional areas 105, 110 and 115 on layer 101 is merely illustrative. These areas maybe active elements such as MEM dies. In order to maintain removal rate consistency during polishing example, CMP, dummy structures are added into layer 101. The placement of these dummy structures, requiring calculation of shape, size and positioning, necessitates accurate measurement of wafer parameters, including its size, prior to their bonding, Paras [0003], [0022], [0023], Figures 1-3);
receiving component die size parameters for at least one component die and component die positioning parameters of the at least one component die for the bonding wafer (see e.g., placement of the dummy structure to the layer 101 is determined as a function of the density (location and shape) and width of the functional area, Paras [0026], [0027], [0030], Figures 1-3);
determining dummy die size parameters, dummy die material composition, or dummy die positioning parameters on the bonding wafer…. selecting at least one dummy die according to the dummy die size parameters, dummy die material composition, or dummy die positioning parameters; and (see e.g., the placement, size and shape of the dummy structure to be added to the layer 101 is determined based on the density and width of functional areas of the substrate. The size of the dummy structure is a function of the placement and the shape of the dummy structure is a function of the size. Dummy structures are added to the layer 101 to achieve better planarization through CMP, Para [0036], [0037], [0039], Figures 1-3);
Schmidt does not explicitly teach
“receiving bonding wafer processing information for at least one subsequent post-bonding process for the bonding wafer;
determining dummy size….based on the at least one subsequent post-bonding process or thermal behavior of a dummy die material or a wafer material of the bonding wafer”.
Note that Schmidt teaches placing the dummy structures to the layer 101 in order to maintain removal rate consistency during post-bonding process for example, CMP. (see e.g., Para [0024]). The dummy dies are being placed on the wafer in order to reduce post-CMP topography.
In a similar field of endeavor Wang teaches a system to compute dummy feature density for a (Chemical Mechanical Polishing) CMP process in order to reduce the post-CMP topography.
Wang shows oxide CMP process for aluminum interconnect fabrication flow but can easily be applied to any other types of CMP processes. Wang’s smart dummy filling technique uses more accurate CMP models to add dummy features at appropriate locations on the wafer. Figure 4 presents a flowchart that illustrates various high-level steps in the smart dummy filling process. The process starts by performing layout density acquisition (step 402), which involves discretizing the integrated circuit into a set of panels and computing the metal density and slack density for each panel. Next, the system assigns dummy feature density (step 404). In this step, the system uses a CMP process model to compute the dummy feature density to be added to the slack region 514 in panel 506 in order to reduce the post-CMP topography variation. The system then performs dummy feature placement (step 406) based on the computed dummy feature density and design rules. For example, the system may place dummy features 516 based on the computed dummy feature density. Once the new layout with dummy features is sent to the foundry for fabrication, the dummy features are produced and CMP is used to planarize the wafer that contains dummy features (see e.g., Paras [0049], [0052], Figures 3 and 4).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to place dummy features based on the CMP process onto a wafer to improve post-CMP topography. Knowing the CMP parameters allows for accurate material removal and creates a surface suitable for bonding.
Schmidt does not explicitly teach
“bonding the at least one dummy die on the bonding wafer according to the dummy die positioning parameters”.
In a similar field of endeavor Shih teaches
bonding the at least one dummy die on the bonding wafer according to the dummy die positioning parameters (see e.g., plurality of bumps 416b, such as micropumps, are formed on the RDL and the dummy die 420b is bonded to these bumps, Para [0028], Figures 3-4).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Shih’s teachings of bonding the at least one dummy die on the bonding wafer according to the dummy die positioning parameters in the method of Schmidt in order to reduce stress of the functional bumps.
Regarding claim 12, Schmidt teaches a method for dummy die placement on a bonding wafer (see e.g., Figures 1-3), comprising:
receiving bonding wafer parameters for the bonding wafer, wherein the bonding wafer parameters include a size of the bonding wafer or a material composition of the bonding wafer (see e.g., layer 101, which is formed on or as part of the substrate 100, a semiconductor wafer. The substrate 100 has functional areas 110, 105 and 115, the physical location of functional areas 105, 110 and 115 on layer 101 is merely illustrative. These areas maybe active elements such as MEM dies. In order to maintain removal rate consistency during polishing example, CMP, dummy structures are added into layer 101. The placement of these dummy structures, requiring calculation of shape, size and positioning, necessitates accurate measurement of wafer parameters, including its size, prior to their bonding, Paras [0003], [0022], [0023], Figures 1-3);
receiving component die size parameters for at least one component die and component die positioning parameters of the at least one component die for the bonding wafer, wherein the component die size parameters include a width, a length, and a height of the component die (see e.g., placement of the dummy structure to the layer 101 is determined as a function of the density (location and shape) and width of the functional area. The functional feature’s shape and width are determined which in 3D context includes length, width and height, Paras [0026], [0027], [0030], Figures 1-3);
inferring dummy die size parameters, dummy die material composition, or dummy die positioning parameters on the bonding wafer …..that incorporates the bonding wafer parameters, the component die size parameters, the component die positioning parameters, and to select at least one dummy die; and (see e.g., the placement, size and shape of the dummy structure to be added to the layer 101 is determined based on the density and width of functional areas of the substrate. The size of the dummy structure is a function of the placement and the shape of the dummy structure is a function of the size. Dummy structures are added to the layer 101 to achieve better planarization through CMP, Para [0036], [0037], [0039], Figures 1-3).
Schmidt does not explicitly teach
“receiving bonding wafer processing information for at least one subsequent post-bonding process for the bonding wafer;
using a machine learning model that incorporates… the bonding wafer processing information”
Note that Schmidt teaches placing the dummy structures to the layer 101 in order to maintain removal rate consistency during post-bonding process for example, CMP. (see e.g., Para [0024]). The dummy dies are being placed on the wafer in order to reduce post-CMP topography.
In a similar field of endeavor Wang teaches
In a similar field of endeavor Wang teaches a system to compute dummy feature density for a (Chemical Mechanical Polishing) CMP process in order to reduce the post-CMP topography.
Wang shows oxide CMP process for aluminum interconnect fabrication flow but can easily be applied to any other types of CMP processes. Wang’s smart dummy filling technique uses more accurate CMP models to add dummy features at appropriate locations on the wafer. Figure 4 presents a flowchart that illustrates various high-level steps in the smart dummy filling process. The process starts by performing layout density acquisition (step 402), which involves discretizing the integrated circuit into a set of panels and computing the metal density and slack density for each panel. Next, the system assigns dummy feature density (step 404). In this step, the system uses a CMP process model to compute the dummy feature density to be added to the slack region 514 in panel 506 in order to reduce the post-CMP topography variation. The system then performs dummy feature placement (step 406) based on the computed dummy feature density and design rules. For example, the system may place dummy features 516 based on the computed dummy feature density. Once the new layout with dummy features is sent to the foundry for fabrication, the dummy features are produced and CMP is used to planarize the wafer that contains dummy features (see e.g., Paras [0049], [0052], Figures 3 and 4).
Wang’s process is a machine learning model since flowchart 6 shows a process including an iterative process to update the dummy feature density which starts by computing the effective feature density, next calculates the gapfill amount, updates the feature density, slack density and the dummy feature density using the filling amount. If the filling amount has a positive value, the system adds the filling amount to the dummy feature density and subtracts the filling amount from the slack density. Furthermore, the system adds the updated dummy feature density to the feature density to obtain the updated feature density that will be used for the next iteration. The system determines whether to terminate the iterative loop or not, Paras [0060] – [0074]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to place dummy features based on the CMP process onto a wafer to improve post-CMP topography. Knowing the CMP parameters allows for accurate material removal and creates a surface suitable for bonding. Machine learning models are becoming increasingly valuable in optimizing dummy die placement for CMP uniformity and reduced stress and warpage
Schmidt does not explicitly teach
“bonding the at least one dummy die on the bonding wafer according to the dummy die positioning parameters”.
In a similar field of endeavor Shih teaches
bonding the at least one dummy die on the bonding wafer according to the dummy die positioning parameters (see e.g., plurality of bumps 416b, such as micropumps, are formed on the RDL and the dummy die 420b is bonded to these bumps, Para [0028], Figures 3-4).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Shih’s teachings of bonding the at least one dummy die on the bonding wafer according to the dummy die positioning parameters in the method of Schmidt in order to reduce stress of the functional bumps.
Regarding claim 2, Schmidt, as modified by Wang and Shih, teaches the limitations claim 1 as mentioned above. Schmidt further teaches
wherein the bonding wafer parameters include a size of the bonding wafer or a material composition of the bonding wafer (see e.g., The placement of these dummy structures, requiring calculation of shape, size and positioning, necessitates accurate measurement of wafer parameters, including its size, prior to their bonding, Paras [0003], [0022], [0023], Figures 1-3).
Regarding claim 3, Schmidt, as modified by Wang and Shih, teaches the limitations claim 1 as mentioned above. Schmidt further teaches
wherein the component die size parameters include a width, a length, and a height of a component die (see e.g., the functional feature’s shape and width are determined which in 3D context includes length, width and height, Para [0027], Figures 1-3).
Regarding claims 4 and 13, Schmidt, as modified by Wang and Shih, teaches the limitations claim 1 and 12 as mentioned above. Schmidt further teaches
wherein the dummy die size parameters include a width, a length, and a height for a dummy die (see e.g., dummy structure size and shape are determined which in 3D context includes length, width and height, Para [0026], Figures 1-3).
Regarding claims 5 and 14, Schmidt, as modified by Wang and Shih, teaches the limitations claim 1 and 12 as mentioned above. Schmidt does not explicitly teach
“wherein the dummy die material composition includes dielectric material and metallic material”.
In a similar field of endeavor Shih teaches
wherein the dummy die material composition includes dielectric material and metallic material (see e.g., the dummy chips 420b may be dummy silicon chips, dies or pieces having dimensions or sizes similar to that of the chip 420a, but not limited thereto. It is to be understood that other materials such as metal, glass or ceramic may be used, Para [0029], Figure 4).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Shih’s teachings of wherein the dummy die material composition includes dielectric material and metallic material in the method of Schmidt in order to provide material mimicking the behavior of functional die.
Regarding claim 6, Schmidt, as modified by Wang and Shih, teaches the limitations claim 1 as mentioned above. Schmidt further teaches
receives the bonding wafer parameters (see e.g., layer 101, which is formed on or as part of the substrate 100, a semiconductor wafer. The substrate 100 has functional areas 110, 105 and 115, the physical location of functional areas 105, 110 and 115 on layer 101 is merely illustrative. These areas maybe active elements such as MEM dies. In order to maintain removal rate consistency during polishing example, CMP, dummy structures are added into layer 101. The placement of these dummy structures, requiring calculation of shape, size and positioning, necessitates accurate measurement of wafer parameters, including its size, prior to their bonding, Paras [0003], [0022], [0023], Figures 1-3), the component die size parameters, the component die positioning parameters (see e.g., placement of the dummy structure to the layer 101 is determined as a function of the density (location and shape) and width of the functional area, Paras [0026], [0027], [0030], Figures 1-3), and infers the dummy die size parameters, the dummy die material composition, or the dummy die positioning parameters for the bonding wafer (see e.g., the placement, size and shape of the dummy structure to be added to the layer 101 is determined based on the density and width of functional areas of the substrate. The size of the dummy structure is a function of the placement and the shape of the dummy structure is a function of the size. Dummy structures are added to the layer 101 to achieve better planarization through CMP, Para [0036], [0037], [0039], Figures 1-3).
Schmidt does not explicitly teach
“using a machine learning model that receives….. the bonding wafer processing information”
In a similar field of endeavor Wang teaches
using a machine learning model that receives … the bonding wafer processing information (see e.g., flowchart 6 shows a process including an iterative process to update the dummy feature density which starts by computing the effective feature density, next calculates the gapfill amount, updates the feature density, slack density and the dummy feature density using the filling amount. If the filling amount has a positive value, the system adds the filling amount to the dummy feature density and subtracts the filling amount from the slack density. Furthermore, the system adds the updated dummy feature density to the feature density to obtain the updated feature density that will be used for the next iteration. The system determines whether to terminate the iterative loop or not, Paras [0060] – [0074]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wang’s teachings of using a machine learning model that receives … the bonding wafer processing information in the method of Schmidt since machine learning models are becoming increasingly valuable in optimizing dummy die placement for CMP uniformity and reduced stress and warpage.
Regarding claims 7 and 15, Schmidt, as modified by Wang and Shih, teaches the limitations claim 6 and 12 as mentioned above. Schmidt further teaches
infer dummy die size parameters and dummy die positioning parameters that maintain edge uniformity of the bonding wafer during the at least one subsequent post-bonding process (see e.g., the placement, size and shape of the dummy structure to be added to the layer 101 is determined based on the density and width of functional areas of the substrate. The size of the dummy structure is a function of the placement and the shape of the dummy structure is a function of the size. Dummy structures are added to the layer 101 to achieve better planarization through CMP, Para [0036], [0037], [0039], Figures 1-3).
Schmidt does not explicitly teach
“using the machine learning model….”
In a similar field of endeavor Wang teaches
using the machine learning model….( see e.g., flowchart 6 shows a process including an iterative process to update the dummy feature density which starts by computing the effective feature density, next calculates the gapfill amount, updates the feature density, slack density and the dummy feature density using the filling amount. If the filling amount has a positive value, the system adds the filling amount to the dummy feature density and subtracts the filling amount from the slack density. Furthermore, the system adds the updated dummy feature density to the feature density to obtain the updated feature density that will be used for the next iteration. The system determines whether to terminate the iterative loop or not, Paras [0060] – [0074]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wang’s teachings of using a machine learning model in the method of Schmidt since machine learning models are becoming increasingly valuable in optimizing dummy die placement for CMP uniformity and reduced stress and warpage.
Regarding claims 8 and 16, Schmidt, as modified by Wang and Shih, teaches the limitations claims 6 and 12 as mentioned above. Schmidt further teaches
infer dummy die size parameters and dummy die positioning parameters that reduce step height differences between the at least one component die bonded on the bonding wafer and a surrounding area of the at least one component die bonded on the bonding wafer (see e.g., the placement, size and shape of the dummy structure to be added to the layer 101 is determined based on the density and width of functional areas of the substrate. The size of the dummy structure is a function of the placement and the shape of the dummy structure is a function of the size. Dummy structures are added to the layer 101 to achieve better planarization through CMP, Para [0036], [0037], [0039], Figures 1-3).
Schmidt does not explicitly teach
“using the machine learning model ....”
In a similar field of endeavor Wang teaches
using the machine learning model….( see e.g., flowchart 6 shows a process including an iterative process to update the dummy feature density which starts by computing the effective feature density, next calculates the gapfill amount, updates the feature density, slack density and the dummy feature density using the filling amount. If the filling amount has a positive value, the system adds the filling amount to the dummy feature density and subtracts the filling amount from the slack density. Furthermore, the system adds the updated dummy feature density to the feature density to obtain the updated feature density that will be used for the next iteration. The system determines whether to terminate the iterative loop or not, Paras [0060] – [0074]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wang’s teachings of using a machine learning model in the method of Schmidt since machine learning models are becoming increasingly valuable in optimizing dummy die placement for CMP uniformity and reduced stress and warpage.
Regarding claim 10, Schmidt, as modified by Wang and Shih, teaches the limitations claim 1 as mentioned above. Schmidt further teaches
wherein the at least one subsequent post-bonding process includes a chemical mechanical planarization (CMP) process, a chemical vapor deposition (CVD) gapfill process, or a plating gapfill process (see e.g., the dummy structures are placed to help achieve better planarization through a CMP process therefore, it is understood that the post bonding process includes a gapfill process and a CMP process, Para [0040]).
Schmidt does not explicitly teach
“…subsequent post-bonding process includes an annealing process..”
In a similar field of endeavor Shih teaches
… subsequent post-bonding process includes an annealing process…(see e.g., after mounting the active chip 420a and dummy chip 420b through bumps 416a and 416b respectively a thermal process is performed to reflow the bumps, Paras [0029] – [0030], Figures 3-6).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Shih’s teachings of … subsequent post-bonding process includes an annealing process…in the method of Schmidt in order to strengthen the bond between the die and the bump, improve reliability and enhance electrical performance.
Regarding claim 18, Schmidt teaches a non-transitory, computer readable medium having instructions stored thereon that, when executed, cause a method for dummy die placement on a bonding wafer to be performed (see e.g., the process steps are being performed by an algorithm. It is understood that the algorithm would be running on a processor, Figures 1-3), the method comprising:
receiving bonding wafer parameters for the bonding wafer (see e.g., layer 101, which is formed on or as part of the substrate 100, a semiconductor wafer. The substrate 100 has functional areas 110, 105 and 115, the physical location of functional areas 105, 110 and 115 on layer 101 is merely illustrative. These areas maybe active elements such as MEM dies. In order to maintain removal rate consistency during polishing example, CMP, dummy structures are added into layer 101. The placement of these dummy structures, requiring calculation of shape, size and positioning, necessitates accurate measurement of wafer parameters, including its size, prior to their bonding, Paras [0003], [0022], [0023], Figures 1-3);
receiving component die size parameters for at least one component die and component die positioning parameters of the at least one component die for the bonding wafer (see e.g., placement of the dummy structure to the layer 101 is determined as a function of the density (location and shape) and width of the functional area, Paras [0026], [0027], [0030], Figures 1-3);
determining dummy die size parameters, dummy die material composition, or dummy die positioning parameters on the bonding wafer;selecting at least one dummy die according to the dummy die size parameters, dummy die material composition, or dummy die positioning parameters; and (see e.g., the placement, size and shape of the dummy structure to be added to the layer 101 is determined based on the density and width of functional areas of the substrate. The size of the dummy structure is a function of the placement and the shape of the dummy structure is a function of the size. Dummy structures are added to the layer 101 to achieve better planarization through CMP, Para [0036], [0037], [0039], Figures 1-3).
Schmidt does not explicitly teach
“receiving bonding wafer processing information for at least one subsequent post-bonding process for the bonding wafer;
determining dummy die…. based on the at least one subsequent post-bonding process or thermal behavior of a dummy die material or a wafer material of the bonding wafer”.
Note that Schmidt teaches placing the dummy structures to the layer 101 in order to maintain removal rate consistency during post-bonding process for example, CMP. (see e.g., Para [0024]). The dummy dies are being placed on the wafer in order to reduce post-CMP topography.
In a similar field of endeavor Wang teaches a system to compute dummy feature density for a (Chemical Mechanical Polishing) CMP process in order to reduce the post-CMP topography.
Wang shows oxide CMP process for aluminum interconnect fabrication flow but can easily be applied to any other types of CMP processes. Wang’s smart dummy filling technique uses more accurate CMP models to add dummy features at appropriate locations on the wafer. Figure 4 presents a flowchart that illustrates various high-level steps in the smart dummy filling process. The process starts by performing layout density acquisition (step 402), which involves discretizing the integrated circuit into a set of panels and computing the metal density and slack density for each panel. Next, the system assigns dummy feature density (step 404). In this step, the system uses a CMP process model to compute the dummy feature density to be added to the slack region 514 in panel 506 in order to reduce the post-CMP topography variation. The system then performs dummy feature placement (step 406) based on the computed dummy feature density and design rules. For example, the system may place dummy features 516 based on the computed dummy feature density. Once the new layout with dummy features is sent to the foundry for fabrication, the dummy features are produced and CMP is used to planarize the wafer that contains dummy features (see e.g., Paras [0049], [0052], Figures 3 and 4).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to place dummy features based on the CMP process onto a wafer to improve post-CMP topography. Knowing the CMP parameters allows for accurate material removal and creates a surface suitable for bonding.
Schmidt does not explicitly teach
“bonding the at least one dummy die on the bonding wafer according to the dummy die positioning parameters”.
In a similar field of endeavor Shih teaches
bonding the at least one dummy die on the bonding wafer according to the dummy die positioning parameters (see e.g., plurality of bumps 416b, such as micropumps, are formed on the RDL and the dummy die 420b is bonded to these bumps, Para [0028], Figures 3-4).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Shih’s teachings of bonding the at least one dummy die on the bonding wafer according to the dummy die positioning parameters in the method of Schmidt in order to reduce stress of the functional bumps.
Regarding claim 19, Schmidt, as modified by Wang and Shih, teaches the limitations of claim 18 as mentioned above. Schmidt further teaches
receives the bonding wafer parameters (see e.g., layer 101, which is formed on or as part of the substrate 100, a semiconductor wafer. The substrate 100 has functional areas 110, 105 and 115, the physical location of functional areas 105, 110 and 115 on layer 101 is merely illustrative. These areas maybe active elements such as MEM dies. In order to maintain removal rate consistency during polishing example, CMP, dummy structures are added into layer 101. The placement of these dummy structures, requiring calculation of shape, size and positioning, necessitates accurate measurement of wafer parameters, including its size, prior to their bonding, Paras [0003], [0022], [0023], Figures 1-3), the component die size parameters, the component die positioning parameters (see e.g., placement of the dummy structure to the layer 101 is determined as a function of the density (location and shape) and width of the functional area, Paras [0026], [0027], [0030], Figures 1-3), and infers the dummy die size parameters, the dummy die material composition, or the dummy die positioning parameters for the bonding wafer (see e.g., the placement, size and shape of the dummy structure to be added to the layer 101 is determined based on the density and width of functional areas of the substrate. The size of the dummy structure is a function of the placement and the shape of the dummy structure is a function of the size. Dummy structures are added to the layer 101 to achieve better planarization through CMP, Para [0036], [0037], [0039], Figures 1-3).
Schmidt does not explicitly teach
“using a machine learning model that receives….. the bonding wafer processing information”
In a similar field of endeavor Wang teaches
using a machine learning model that receives … the bonding wafer processing information (see e.g., flowchart 6 shows a process including an iterative process to update the dummy feature density which starts by computing the effective feature density, next calculates the gapfill amount, updates the feature density, slack density and the dummy feature density using the filling amount. If the filling amount has a positive value, the system adds the filling amount to the dummy feature density and subtracts the filling amount from the slack density. Furthermore, the system adds the updated dummy feature density to the feature density to obtain the updated feature density that will be used for the next iteration. The system determines whether to terminate the iterative loop or not, Paras [0060] – [0074]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wang’s teachings of using a machine learning model that receives … the bonding wafer processing information in the method of Schmidt since machine learning models are becoming increasingly valuable in optimizing dummy die placement for CMP uniformity and reduced stress and warpage.
Regarding claim 20, Schmidt, as modified by Wang and Shih, teaches the limitations of claim 18 as mentioned above. Schmidt does not explicitly teach
“determining dummy die size parameters, dummy die material composition, or dummy die positioning parameters on the bonding wafer based on metrology information of the bonding wafer”.
However, the dummy structure placement, shape and size on the wafer is a controlled process, not a random one. These dummy structures are strategically inserted into areas lacking active circuitry with the specific objective of improving the CMP uniformity. It is understood that this strategic positioning and dimensioning of dummy structures is informed by the wafer’s existing metrology data.
Claims 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Schmidt et al. (US 2011/0133304 A1; hereafter Schmidt) in view of Wang et al. (US 2005/0114824 A1; hereafter Wang) and Shih et al. (US 2019/0371749 A1; hereafter Shih) and further in view of Chen et al. (US 2020/0365570 A1; hereafter Chen).
Regarding claims 9 and 17, Schmidt, as modified by Wang and Shih, teaches the limitations claim 1 and 12 as mentioned above. Schmidt does not explicitly teach
“determining the dummy die material composition based on thermal expansion or conduction properties of the at least one component die”.
In a similar field of endeavor Chen teaches
determining the dummy die material composition based on thermal expansion or conduction properties of the at least one component die (see e.g., The first dummy die 160 is used to reduce the asymmetric warpage (in X- and Y-direction) or bending stress on the substrate 102. The coefficient of thermal expansion (CTE) of the first dummy die 160 is substantially identical to or similar to the coefficient of thermal expansion (CTE) of the first device die 140, Para [0023]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chen’s teachings of determining the dummy die material composition based on thermal expansion or conduction properties of the at least one component die in the method of Schmidt in order to reduce warpage or bending stress on the substrate.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Schmidt et al. (US 2011/0133304 A1; hereafter Schmidt) in view of Wang et al. (US 2005/0114824 A1; hereafter Wang) and Shih et al. (US 2019/0371749 A1; hereafter Shih) and further in view of Cheng et al. (US 2024/0030222 A1; hereafter Cheng).
Regarding claim 11, Schmidt, as modified by Wang and Shih, teaches the limitations claim 1 as mentioned above. Schmidt does not explicitly teach
“performing the method of claim 1 integrated into an integrated hybrid bonding tool; or performing the method of claim 1 external to the integrated hybrid bonding tool”.
Schmidt teaches the processing steps for dummy placement, steps 305 and 310, and subsequent dummy bonding to the layer 101, step 315, as illustrated in Figure 3.
However, Schmidt is silent regarding the physical location of the dummy placement processing system, neither specifying nor precluding its integration within the bonding tool or its implementation as an external system.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement the dummy placement processing system either as an integrated or external component given that its positioning lacks criticality.
Schmidt does not explicitly teach
the bonding tool is an integrated hybrid bonding tool.
In a similar field of endeavor Cheng teaches
the bonding tool is a hybrid bonding tool (see e.g., the bonding tool 116 is a semiconductor processing tool capable of bonding two or more wafers. The bonding tool maybe a hybrid bonding tool, Para [0039]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Cheng’s teachings of a hybrid bonding tool in the method of Schmidt as hybrid bonding enables higher performance such as reduced electrical resistance and capacitance for faster signals and lower power consumption.
Conclusion
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893