DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The present amendment, filed on or after 02/20/2026, has been entered. The Applicant has amended claims 1, 6-7, and 9, and canceled claims 2 and 10. Claims 15-20 were withdrawn previously due to restriction requirement. Accordingly, claims 1, 3-9, and 11-14 remain pending in the application.
Applicant’s amendments to the claims 1 and 6-7 have overcome each and every objection previously set forth in the Non-Final Office Action mailed on 10/27/ 2025.
Claim Objections
Claims 12-13 are objected to because of the following informalities:
Both claim 12 and claim 13 are indicated to depend on claim 10, which has been canceled by the Applicant. Because the Applicant incorporated claim 10 into amended independent claim 9, the Examiner considers the improper dependency of claim 12-13 on claim 10 as a typo, where the dependencies of claims 12 and 13 should be changed to claim 9 instead of claim 10. Accordingly, for examining purpose, claims 12-13 are considered to be dependent on claim 9.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 4, and 6-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 of U.S. Patent No. US 9,349,648 B2 (will be referred as Lei) in view of Bischoff (Bischoff, C., Hellmann, R. and Rung, S. (2012), Efficient Micromachining of Thin Films with Nanosecond Lasers. LTJ, 9: 15-20. https://doi.org/10.1002/latj.201290062).
Instant Application- 18/141,177
US Pat. No. US 9,349,648 B2 (Lei)
1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the plurality of integrated circuits;
patterning the mask with a rectangular laser spot-based laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the plurality of integrated circuits, wherein the rectangular laser spot-based laser scribing process comprises using laser spots that are square in plan view and having a top-hat profile in cross-sectional view, and wherein the laser spots are edge-aligned and do not overlap with one another; and
plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the plurality of integrated circuits.
4. The method of claim 1, wherein the rectangular laser spot-based laser scribing process comprises using a Gaussian source laser beam.
6. The method of claim 1, wherein scribing with the rectangular laser spot-based laser scribing process comprises scribing with a femto-second rectangular laser spot-based laser beam.
7. The method of claim 1, wherein patterning the mask with the laser scribing process comprises forming trenches in the regions of the semiconductor wafer between the plurality of integrated circuits, and wherein plasma etching the semiconductor wafer comprises extending the trenches to form corresponding trench extensions.
1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the integrated circuits;
patterning the mask with a top hat laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits, wherein the top hat laser beam profile laser scribing process comprises scribing with a laser beam having a rectangular shaped two-dimensional top hat beam, wherein scribing with the laser beam having the rectangular shaped two-dimensional top hat beam comprises shaping a Gaussian-shaped beam into the rectangular shaped two-dimensional top hat beam;
subsequent to patterning the mask with the top hat laser beam profile laser scribing process, cleaning the exposed regions of the semiconductor wafer with a plasma process; and
subsequent to cleaning the exposed regions of the semiconductor wafer with the plasma process, plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.
2. The method of claim 1, wherein scribing with the laser beam having the rectangular shaped two-dimensional top hat beam comprises using a femto-second based rectangular shaped two-dimensional top hat beam.
3. The method of claim 1, wherein patterning the mask with the laser scribing process comprises forming trenches in the regions of the semiconductor wafer between the integrated circuits, and wherein plasma etching the semiconductor wafer comprises extending the trenches to form corresponding trench extensions.
Regarding claim 1, Lei claim 1 recites the limitations of claim 1 which are shown in bold in the table above.
Lei, however, does not teach that the laser spots are edge-aligned and do not overlap with one another.
Bischoff, on the other hand, teaches methods for efficient micromachining of thin films with laser spots (Abstact) of square-shaped plan view and top-hat cross-section (Fig. 1). Bischoff discloses that square-shaped laser spots with top-hat profiles can achieve effective and smooth scribing even with minimal to no overlap (Fig. 9, page 5, para. 4; see also Fig. 1 top-hat spot profile, where the laser spots are edge-aligned as defined by the ablation threshold, and the overlap between laser spots is zero when the regions of the spots indicated by heating energy is excluded, which is in agreement with the current application). Bischoff further discloses that square-shaped laser spots with top-hat profile provide the benefit of increasing the processing speed of the laser micromachining when the overlap between spots are minimized (page 2, para. 1). Furthermore, as evidenced by Abelo (US 2007/0272668 A1), using square-shaped pulses with overlap leads to a non-uniform scribing depth at the ends of the etched trenches (Fig. 8, [0056]), which will be undesirable in applications requiring uniform ablation depth.
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the method of Lei to use the square-shaped laser spots in a way taught by Bischoff so that the laser spots are edge-aligned (minimal overlap with complete coverage at or above the ablation threshold) and do not overlap with one another, which would provide the benefit of increasing the scribing speed and improving the scribing uniformity.
Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of Lei in view of Bischoff as applied to claim 1 above and further in views of Kumar (US 2015/0162243 A1) and Gu (US 2008/0067155 A1).
Instant Application- 18/141,177
Lei (US Pat. No. US 9,349,648 B2)
1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the plurality of integrated circuits;
patterning the mask with a rectangular laser spot-based laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the plurality of integrated circuits, wherein the rectangular laser spot-based laser scribing process comprises using laser spots that are square in plan view and having a top-hat profile in cross-sectional view, and wherein the laser spots are edge-aligned and do not overlap with one another; and
plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the plurality of integrated circuits.
3. The method of claim 1, wherein the rectangular laser spot-based laser scribing process comprises scribing with a laser beam having a wavelength in a range of 510-530 nanometers, an input beam diameter in a range of 8-10 millimeters, a working distance in a range of 40-55 millimeters, and an output square spot width in a range of 6-8 microns.
1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the integrated circuits;
patterning the mask with a top hat laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits, wherein the top hat laser beam profile laser scribing process comprises scribing with a laser beam having a rectangular shaped two-dimensional top hat beam, wherein scribing with the laser beam having the rectangular shaped two-dimensional top hat beam comprises shaping a Gaussian-shaped beam into the rectangular shaped two-dimensional top hat beam;
subsequent to patterning the mask with the top hat laser beam profile laser scribing process, cleaning the exposed regions of the semiconductor wafer with a plasma process; and
subsequent to cleaning the exposed regions of the semiconductor wafer with the plasma process, plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.
Lei claim 1 in view of Bischoff recites the limitations of claims 1.
Lei and Bischoff do not explicitly disclose that the rectangular laser spot-based laser scribing process comprises scribing with a laser beam having a wavelength in a range of 510-530 nanometers, an input beam diameter in a range of 8-10 millimeters, a working distance in a range of 40-55 millimeters, and an output square spot width in a range of 6-8 microns.
Kumar, on the other hand, teaches a method of dicing a semiconductor wafer (Fig. 9A-D, Abstract) comprising a plurality of integrated circuits ([0070]) with a laser spot-based laser scribing process (Abstract)), wherein the laser spot-based laser scribing process comprises scribing with a laser beam having a wavelength in a range of 510-530 nanometers ([0063]: 250nm to 540 nm), and an output square spot width in a range of 6-8 microns ([0063]: 5-10 microns).
Therefore, the range of wavelengths and the range of the output laser spot sizes provided by Kumar overlap with the ranges disclosed in the current application, and a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the range of wavelengths and range of spot sizes can be optimized by routine experimentation to achieve a desired scribing smoothness and minimize the damage caused by scribing (see MPEP 2144.05(II)), as also disclosed by Kumar (see the detailed description in paragraph [0066]). Thus, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use a laser beam having a wavelength in a range of 510-530 nanometers, and an output square spot width in a range of 6-8 microns in the method of Lei, as disclosed by Kumar to achieve a desired scribing smoothness and minimize the damage caused by scribing.
Lei, Bischoff, and Kumar, however, do not teach an input beam diameter in a range of 8-10 millimeters, and a working distance in a range of 40-55 millimeters.
Gu, on the other hand, teaches a method of laser processing semiconductor substrates (Fig. 2, [0005]-[0006]: including cutting and trimming), wherein the working distance is at least in a range of 40-55 millimeters ([0099]: at least 40 millimeters).
The range of working distances provided by Gu overlaps with the range disclosed the current application, and a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the range of working distances can be optimized by routine experimentation to achieve desired operating conditions for the method (see MPEP 2144.05(II)), as also disclosed by Gu, that having the working distance to be at least 40 millimeters allows access to the devices on the surface of the wafer if required (claim 50: such as contact probes). Furthermore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be also motivated to adjust the working distance according to the heights of the integrated circuits on the semiconductor wafer. Therefore, the combination of Lei, Bischoff, Kumar, and Gu meets the limitation that the working distance is at least in a range of 40-55 millimeters.
Lei, Bischoff, Kumar, and Gu do not explicitly disclose that an input beam diameter is in a range of 8-10 millimeters.
However, a person of ordinary skill in the art before the effective filing date of the claimed invention would be familiar with that the diameter of the femto-second Gaussian input beam would be set to achieve a stable beam-shaping profile for a given working distance, output beam spot size, and laser wavelength, as evidenced by Schlutow (page 2, section 2.1; Schlutow et al., Applications in Laser Material Processing. Materials 2021, 14, 4981, doi.org/10.3390/ma14174981). For example, for typical beam sizes of femtosecond lasers (~5 mm) and a beta factor of 10, the input beam diameter would be at least 6.9 millimeters (see equation 2 of Schlutow) for the ranges provided for the working distance, output spot size and a laser wavelength. Thus, the range provided by combination of Lei, Kumar, and Gu covers the range provided by the current application, and a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the range of input beam diameter can be optimized by routine experimentation to achieve desired quality for the rectangular laser spot (see MPEP 2144.05(II)).
Therefore, the combination of Lei, Kumar, and Gu meets all the limitations of claim 3.
Claim 5 is rejected on the ground of nonstatutory double patenting as being unpatentable over Lei claim 1 in view of Bischoff as applied to claim 1 above and further in view of Lei claim 4.
Instant Application- 18/141,177
Lei (US Pat. No. US 9,349,648 B2)
1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the plurality of integrated circuits;
patterning the mask with a rectangular laser spot-based laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the plurality of integrated circuits, wherein the rectangular laser spot-based laser scribing process comprises using laser spots that are square in plan view and having a top-hat profile in cross-sectional view, and wherein the laser spots are edge-aligned and do not overlap with one another; and
plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the plurality of integrated circuits.
4. The method of claim 1, wherein the rectangular laser spot-based laser scribing process comprises using a Gaussian source laser beam.
5. The method of claim 4, wherein the rectangular laser spot-based laser scribing process comprises using a femto-second source laser beam.
1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the integrated circuits;
patterning the mask with a top hat laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits, wherein the top hat laser beam profile laser scribing process comprises scribing with a laser beam having a rectangular shaped two-dimensional top hat beam, wherein scribing with the laser beam having the rectangular shaped two-dimensional top hat beam comprises shaping a Gaussian-shaped beam into the rectangular shaped two-dimensional top hat beam;
subsequent to patterning the mask with the top hat laser beam profile laser scribing process, cleaning the exposed regions of the semiconductor wafer with a plasma process; and
subsequent to cleaning the exposed regions of the semiconductor wafer with the plasma process, plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.
Lei claim 1 in view of Bischoff recites the limitations of claims 1 and 4.
Lei and Bischoff do not explicitly disclose that the rectangular laser spot-based laser scribing process comprises using a femto-second source laser beam.
However, it is well-known in the field of optics that a femto-second, square-shaped laser beam is generated most effectively by converting the Gaussian beam output of a femtosecond source laser to a square shape, as also evidenced by Long (Fig. 2, Long et al, Centimeter-scale low-damage micromachining on single-crystal 4H–SiC substrates using a femtosecond laser with square-shaped Flat-Top focus spots, Ceramics International, Volume 47, Issue 16, 2021, Pages 23134-23143, ISSN 0272-8842, doi.org/10.1016/j.ceramint.2021.05.027). Applying a known technique to yield predictable results does not provide further inventive concept (see MPEP (I)(D)), and therefore, the combination of Lei and Bischoff meets the limitations of claim 5.
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over Lei claim 1 in view of Bischoff as applied to claim 1 above and further in view of Balakrishnan (US 2021/0050262 A1).
1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the plurality of integrated circuits;
patterning the mask with a rectangular laser spot-based laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the plurality of integrated circuits, wherein the rectangular laser spot-based laser scribing process comprises using laser spots that are square in plan view and having a top-hat profile in cross-sectional view, and wherein the laser spots are edge-aligned and do not overlap with one another; and
plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the plurality of integrated circuits.
8. The method of claim 1, wherein the rectangular laser spot-based laser scribing process is an actively-focused laser beam laser scribing process comprising pre-mapping a topography of the semiconductor wafer or a topography of a chuck for supporting the semiconductor wafer, or both.
1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the integrated circuits;
patterning the mask with a top hat laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits, wherein the top hat laser beam profile laser scribing process comprises scribing with a laser beam having a rectangular shaped two-dimensional top hat beam, wherein scribing with the laser beam having the rectangular shaped two-dimensional top hat beam comprises shaping a Gaussian-shaped beam into the rectangular shaped two-dimensional top hat beam;
subsequent to patterning the mask with the top hat laser beam profile laser scribing process, cleaning the exposed regions of the semiconductor wafer with a plasma process; and
subsequent to cleaning the exposed regions of the semiconductor wafer with the plasma process, plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.
Lei claim 1 in view of Bischoff teaches the limitations of claim 1.
Lei and Bischoff, however, do not explicitly disclose that the rectangular laser spot-based laser scribing process is an actively-focused laser beam laser scribing process comprising pre-mapping a topography of the semiconductor wafer or a topography of a chuck for supporting the semiconductor wafer, or both.
Balakrishnan, on the other hand, teaches a method for dicing a semiconductor wafer by an actively-focused laser beam (Fig. 1, Abstract) including scribing the regions between the integrated circuits (integrated circuits 206, Fig. 2A-B, [0029]) on the semiconductor wafer (substrate 204, Figs. 2A-B, [0029]) with a laser beam (Figs. 2A-B, [0036]). Balakrishnan further teaches that the laser scribing process is an actively-focused laser beam laser scribing process ([0036]) comprising pre-mapping a topography of the semiconductor wafer or a topography of a chuck for supporting the semiconductor wafer, or both ([0044] and claim 12).
Balakrishnan discloses that an actively-focused laser beam laser scribing process including pre-mapping the topography of the semiconductor wafer or the topography of the chuck for supporting the semiconductor wafer, or both would provide the benefit of compensating for chuck or substrate thickness variations in a laser dicing process ([0023]) by actively adjusting the laser focus according to the topography ([0026]), and thereby increasing the uniformity of the scribe profile. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to incorporate an actively-focused laser beam laser scribing process comprising pre-mapping a topography of the semiconductor wafer or a topography of a chuck for supporting the semiconductor wafer, or both, as disclosed by Balakrishnan, into the method of Lei to increase the uniformity of the scribing process.
Claims 9-10, and 12-13 is rejected under 35 U.S.C. 103 as being unpatentable over Kumar (US 2015/0162243 A1) in views of Raciukaitis (Raciukaitis et al, Laser processing by using diffractive optical laser beam shaping technique, J. Laser Micro Nanoeng. 6 (2011) 37–43, doi.org/10.2961/jlmn.2011.01.0009) and Bischoff (Bischoff, C., Hellmann, R. and Rung, S. (2012), Efficient Micromachining of Thin Films with Nanosecond Lasers. LTJ, 9: 15-20. https://doi.org/10.1002/latj.201290062).
Regarding claim 9, Kumar teaches a method of dicing a semiconductor wafer (Fig. 9A-D, Abstract) comprising a plurality of integrated circuits ([0070]: “The device layer 904 also includes streets arranged between integrated circuits, the streets including the same or similar layers to the integrated circuits.”), the method comprising:
laser scribing (Figs. 9A-D, [0073]) the semiconductor wafer (Figs. 9A-D) with a laser scribing process to singulate ([0072]: femtosecond-based laser scribing process) the plurality of integrated circuits ([0073]: “… in the case that substrate 906 is thinner than approximately 50 microns, the laser ablation process 912 is used to completely singulate substrate 906 without the use of an additional plasma process.”).
Kumar, however, does not teach that the laser scribing process is a rectangular laser spot-based laser scribing process, wherein the rectangular laser spot-based laser scribing process comprises using laser spots that are square in plan view and having a top-hat profile in cross-sectional view, and
wherein the laser spots are edge-aligned and do not overlap with one another.
Raciukaitis, on the other hand, teaches a method for scribing and drilling thin films (Abstract), wherein Raciukaitis further teaches laser scribing process is a rectangular laser spot-based laser scribing process (Figs. 1 and 6), which leads to significant improvements in edge smoothness and reduces damage compared to Gaussian beams (page 6, conclusion).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to singulate the plurality of integrated circuits with a rectangular spot-based laser scribing process, as taught by Raciukaitis, in the method of Kumar, which would provide the benefit of improving the smoothness of the edges.
Kumar and Raciukaitis, however, do not teach that
the laser spots are edge-aligned and do not overlap with one another.
Bischoff, on the other hand, teaches methods for efficient micromachining of thin films with laser spots (Abstact) of square-shaped plan view and top-hat cross-section (Fig. 1). Bischoff discloses that square-shaped laser spots with top-hat profiles can achieve effective and smooth scribing even with minimal to no overlap (Fig. 9, page 5, para. 4; see also Fig. 1 top-hat spot profile, where the laser spots are edge-aligned as defined by the ablation threshold, and the overlap between laser spots is zero when the regions of the spots indicated by heating energy is excluded, which is in agreement with the current application). Bischoff further discloses that square-shaped laser spots with top-hat profile provide the benefit of increasing the processing speed of the laser micromachining when the overlap between spots are minimized (page 2, para. 1). Furthermore, as evidenced by Abelo (US 2007/0272668 A1), using square-shaped pulses with overlap leads to a non-uniform scribing depth at the ends of the etched trenches (Fig. 8, [0056]), which will be undesirable in applications requiring uniform ablation depth.
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the method of Kumar in view of Raciukaitis to use the square-shaped laser spots in a way taught by Bischoff, so that the laser spots are edge-aligned (minimal overlap with complete coverage at or above the ablation threshold) and do not overlap with one another, which would provide the benefit of increasing the scribing speed and improving the scribing uniformity.
Regarding claim 12, while Kumar in views of Raciukaitis and Bischoff teaches the method of claim
Kumar does not teach that the rectangular laser spot-based laser scribing process comprises using a Gaussian source laser beam.
Raciukaitis, on the other hand, teaches a method for scribing and drilling thin films (Abstract) using a rectangular laser spot-based laser scribing process (Figs. 1 and 6), wherein the rectangular laser spot-based laser scribing process comprises using a Gaussian source laser beam (page 2, col. 1, para. 2). Raciukaitis further discloses that using square-shaped beams improves the smoothness of the edges of the scribed regions.
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use a rectangular laser spot-based laser scribing process comprising using laser spots that are square in plan view and form the square-shaped beam from a Gaussian source laser beam, as taught by Raciukaitis, in the method of Kumar in views of Raciukaitis and Bischoff, which would provide the benefit of improving the smoothness of the edges.
Regarding claim 13, Kumar in views of Raciukaitis and Bischoff teaches the method of claim
Kumar further teaches that the rectangular laser spot-based laser scribing process comprises using a femto-second source laser beam ([0035]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kumar (US 2015/0162243 A1) in view of Raciukaitis (Raciukaitis et al, Laser processing by using diffractive optical laser beam shaping technique, J. Laser Micro Nanoeng. 6 (2011) 37–43, doi.org/10.2961/jlmn.2011.01.0009) and Bischoff (Bischoff, C., Hellmann, R. and Rung, S. (2012), Efficient Micromachining of Thin Films with Nanosecond Lasers. LTJ, 9: 15-20. https://doi.org/10.1002/latj.201290062) as applied to claims 9 and 12-13 above, and further in view of Gu (US 2008/0067155 A1).
Regarding claim 11, Kumar in views of Raciukaitis of Bischoff teaches the method of claim 9, wherein
Kumar further teaches that the laser spot-based laser scribing process comprises scribing with a laser beam having a wavelength in a range of 510-530 nanometers ([0063]: 250nm to 540 nm), and an output square spot width in a range of 6-8 microns ([0063]: 5-10 microns).
Therefore, the range of wavelengths and the range of the output laser spot sizes provided by Kumar in view of Raciukaitis and Bischoff overlap with the ranges disclosed in the current application, and a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the range of wavelengths and range of spot sizes can be optimized by routine experimentation to achieve a desired scribing smoothness and minimize the damage caused by scribing (see MPEP 2144.05(II)), as also disclosed by Kumar (see the detailed description in paragraph [0066]). Thus, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use a laser beam having a wavelength in a range of 510-530 nanometers, and an output square spot width in a range of 6-8 microns in the method of Kumar in view of Raciukaitis and Bischoff, as disclosed by Kumar to achieve a desired scribing smoothness and minimize the damage caused by scribing.
Kumar, Raciukaitis, and Bischoff, however, do not teach an input beam diameter in a range of 8-10 millimeters, and a working distance in a range of 40-55 millimeters.
Gu, on the other hand, teaches a method of laser processing semiconductor substrates (Fig. 2, [0005]-[0006]: including cutting and trimming), wherein the working distance is at least in a range of 40-55 millimeters ([0099]: at least 40 millimeters).
The range of working distances provided by Gu overlaps with the range disclosed the current application, and a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the range of working distances can be optimized by routine experimentation to achieve desired operating conditions for the method (see MPEP 2144.05(II)), as also disclosed by Gu, that having the working distance to be at least 40 millimeters allows access to the devices on the surface of the wafer if required (claim 50: such as contact probes). Furthermore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be also motivated to adjust the working distance according to the heights of the integrated circuits on the semiconductor wafer. Therefore, the combination of Kumar, Raciukaitis, Bischoff, and Gu meets the limitation that the working distance is at least in a range of 40-55 millimeters.
Kumar, Raciukaitis, Bischoff, and Gu do not explicitly disclose that an input beam diameter is in a range of 8-10 millimeters.
However, a person of ordinary skill in the art before the effective filing date of the claimed invention would be familiar with that the diameter of the femto-second Gaussian input beam would be set to achieve a stable beam-shaping profile for a given working distance, output beam spot size and laser wavelength, as evidenced by Schlutow (page 2, section 2.1; Schlutow et al., Applications in Laser Material Processing. Materials 2021, 14, 4981, doi.org/10.3390/ma14174981). For example, for typical beam sizes of femtosecond lasers (~5 mm) and a beta factor of 10, the input beam diameter would be at least 6.9 millimeters (see equation 2 of Schlutow) for the ranges provided for the working distance, output spot size and a laser wavelength. Thus, the range provided by combination of Kumar, Raciukaitis, Bischoff, and Gu covers the range provided by the current application, and a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the range of input beam diameter can be optimized by routine experimentation to achieve desired quality for the rectangular laser spot (see MPEP 2144.05(II)).
Therefore, the combination of Kumar, Raciukaitis, Bischoff, and Gu meets all the limitations of claim 11.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kumar (US 2015/0162243 A1) in views of Raciukaitis (Raciukaitis et al, Laser processing by using diffractive optical laser beam shaping technique, J. Laser Micro Nanoeng. 6 (2011) 37–43, doi.org/10.2961/jlmn.2011.01.0009) and Bischoff (Bischoff, C., Hellmann, R. and Rung, S. (2012), Efficient Micromachining of Thin Films with Nanosecond Lasers. LTJ, 9: 15-20. https://doi.org/10.1002/latj.201290062) as applied to claims 9 and 12-13 above, and further in view of Balakrishnan (US 2021/0050262 A1).
Regarding claim 14, while Kumar in views of Raciukaitis and Bischoff teaches the method of claim 9,
Kumar, Raciukaitis, and Bischoff fail to disclose that the rectangular laser spot-based laser scribing process is an actively-focused laser beam laser scribing process comprising pre-mapping a topography of the semiconductor wafer or a topography of a chuck for supporting the semiconductor wafer, or both.
Balakrishnan, on the other hand, teaches a method for dicing a semiconductor wafer by an actively-focused laser beam (Fig. 1, Abstract) including scribing the regions between the integrated circuits (integrated circuits 206, Fig. 2A-B, [0029]) on the semiconductor wafer (substrate 204, Figs. 2A-B, [0029]) with a laser beam (Figs. 2A-B, [0036]). Balakrishnan further teaches that the laser scribing process is an actively-focused laser beam laser scribing process ([0036]) comprising pre-mapping a topography of the semiconductor wafer or a topography of a chuck for supporting the semiconductor wafer, or both ([0044] and claim 12).
Balakrishnan discloses that an actively-focused laser beam laser scribing process, including pre-mapping the topography of the semiconductor wafer or the topography of the chuck for supporting the semiconductor wafer, or both, would provide the benefit of compensating for chuck or substrate thickness variations in a laser dicing process ([0023]), by actively adjusting the laser focus according to the topography ([0026]), and thereby increasing the uniformity of the scribe profile. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to incorporate an actively-focused laser beam laser scribing process comprising pre-mapping a topography of the semiconductor wafer or a topography of a chuck for supporting the semiconductor wafer, or both, as disclosed by Balakrishnan, into the method of Kumar in views of Raciukaitis and Bischoff, to increase the uniformity of the scribing process.
Response to Arguments
It has been acknowledged that the applicant amended claims 1, 6-7, and 9, and canceled claims 2 and 10 per response dated on 2/20/2026.
Applicant's arguments with respect to claims have been fully considered. The Examiner agrees with the Applicant on that the amendments to independent claims 1 and 9 overcame their corresponding rejections made previously in the non-final office action.
However, amended independent claims 1 and 9 are now rejected under new grounds based on a new prior-art, Bischoff (Bischoff, C., Hellmann, R. and Rung, S. (2012), Efficient Micromachining of Thin Films with Nanosecond Lasers. LTJ, 9: 15-20. https://doi.org/10.1002/latj.201290062), combined with the prior art of the non-final office action. Rejections are also made on all remaining claims based on Bischoff and prior art of the non-final office action.
For the purpose of compact prosecution, the Examiner notes, however, that incorporating more detailed limitations about the method might make independent claim 1 and 9 inventive and non-obvious.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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