Attorney’s Docket Number: SILG2022P24US
Filing Date: 05/01/2023
Claimed Priority Date: 05/20/2022 (CN202210556968.7)
Applicants: Chen
Examiner: Aneesa Baig
DETAILED ACTION
This Office action responds to the Amendment filed on 06/03/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114.
The Amendment filed on 06/03/2026, responding to the Office action mailed on 03/17/2026, has been entered. The present Office action is made with all the suggested amendments being fully considered. Applicant amended claims 1, 8 and pending in this application are claims 1-20.
Response to Amendment
Applicant amendments to the Claims have overcome the respective claim rejections under 35 U.S.C. 103, as previously formulated in the Final Office action mailed on 03/17/2026. However, some of the previously presented prior art remains relevant, and new grounds for rejection are presented below, as necessitated by Applicant’s amendments.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 14-16,18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Vinn (US 20060216855 A1, Hereinafter Vinn) in view of Chen (US 20200328092 A1, Hereinafter Chen) further in view of Daubenspeck (US 20140319522 A1, Hereinafter Daubenspeck) further in view of Yilmaz et al (US 20140054758 A1, Hereinafter Yilmaz).
Regarding claim 1, Vinn (Fig 2-5,[0010]-[0042]) shows most aspects of a stacked packaging structure, comprising:
b) a die located on a first surface of the package material (e.g., converter chip 108 on material 110);
c) an electrical interconnection structure located above the die and configured to be electrically connected with corresponding electrodes of the die (e.g., metal pad 106) ;
d) a diode located on the electrical interconnection structure (e.g., diode 102); and
e) wherein a lower surface of the diode is electrically connected to the electrical interconnection structure (e.g., bottom of diode (cathode) is connected to 106), and an electrode on an upper surface of the diode is connected to a corresponding pin of the package material (e.g., anode of diode is connected to SW 122).
While Vinn shows a stacked packaging structure with three pins on a package material (e.g., Fig 3, 110 [0024]), it fails to show a lead frame as part of the structure.
Chen, (e.g., Figs 1,2, 4D, 4EPar [0020]-[0027]), on the other hand and in a related field, teaches a die (e.g., 307) mounted using three conductive pillars (e.g., 308) and a lead from (e.g., 300) with three pins (e.g., Fig 4D 3022, 306, 305). The
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the packaging structure of Vinn applied to the lead frame and three pin structure of Chen, along with leads from the diode to the pins, to enable mechanical support for a die carrier of integrated circuits, as a basic component (e.g., [0003]) and to efficiently lay out the pins of the lead frame (e.g., [0010]).
While Vinn shows an electrical interconnection structure on the die and insulating layers ([0025]), it does not show a patterned insulating layer on the die.
Daubenspeck (Fig 6-8 [0054]-[0057]), on the other hand and in a related field of die formation, teaches patterning dielectric and passivating layers to form openings and allow for electrical connections. The openings are patterned through a passivation layer and dielectric layers to aligned above and expose the top surfaces of specific metal electrodes.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a patterned passivation layer with openings to allow for electrical connections with the die and external interconnects.
While Vinn shows an electrical interconnection structure above the die, it does not show an electrical interconnection structure that is a cross-toothed structure.
Yilmaz (Figs 17E [0043]-[0046]), on the other hand and in a related field and similar arrangement of lead frame packages, teaches having a conductive segment (340) in the shape of a cross toothed structure placed on a die.
Initially, and with respect to claim 1, note that a limitation in a claim with respect to the manner in which a claimed device is intended to be used does not differentiate the claimed device from a prior-art device if the prior-art device teaches all structural limitations in the claims and the functional limitations are found to be inherent in the prior-art device. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See Hewlett-Packard Co. v. Bausch & Lomb Inc. and the related case law cited therein which makes it clear that it is the final product per se which must be determined in a device claim, and not the patentability of its functions (909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990)).
As stated in Best, Where the claimed and prior art products are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Note that the applicant has burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990).
In the instant case, Vinn /Chen/Daubenspeck/Yilmaz teach all structural aspects of the lead frame package according to the claimed invention (see, paragraphs above). Furthermore, the structure of Vinn/Chen/Daubenspeck in view of Yilmaz is capable of performing the claimed function.
For instance, Yilmaz teaches a die placed on a lead frame and has a conductive clip with two segments in the shape of a cross tooth. Yilmaz teaches this as zig-zag shape has elasticity and reduced fixed contact area to provide stress release from stresses developed at the die/clip interface. The zig-zag structure also allows for outgassing from the conductive adhesive which can reduce void formation and improve electrical performance and reliability ([0043]). Similar to the instant invention, Yilmaz is solving the problem of poor bonding and reducing void formation to improve the device performance. Accordingly, Yilmaz would be capable of performing the function of improving bonding performance and anti-layering ability as in the instant application.
Regarding Claim 2, Vinn (e.g., Fig 2) shows an adhesive layer (e.g., 104) between the electrical connection structure (e.g., 106) and the diode (e.g., 102).
Regarding Claim 3, Vinn shows a conductive adhesive layer (e.g., 104 [0026]).
Regarding Claim 4, While Vinn shows an interconnection structure on the die and insulating layers ([0025]), it does not show a patterned insulating layer on top of an electrical interconnection structure,
Daubenspeck (Fig 6-8 [0054]-[0057]), on the other hand and in a related field of die formation, teaches patterning dielectric and passivating layers to form openings and allow for electrical connections. The openings are patterned through a passivation layer and dielectric layers to aligned above and expose the top surfaces of specific metal electrodes. This is a well-known method to selectively connect metal portions of one surface to another.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a patterned insulation layer on the electrical interconnection structure with openings to allow for electrical connections with the die and external interconnects.
Regarding Claim 5, See comments from Claim 4, as they would be considered repeated here.
Regarding Claim 6, While Vinn /Chen/Daubenspeck/Yilmaz show insulating layers in packaging structures with discrete diodes, they do not show wherein at least one side of the diode exceeds the corresponding side of the opening of the second insulating layer by a distance from 20-50um.
However, it is noted that the specific claimed distance, absent any criticality, is only considered to be the “optimum” thickness disclosed by Vinn that a person having ordinary skill in the art would have been able to determine using routine experimentation based, among other things, on the desired insulating properties for being a good barrier for contaminants. (see Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained as long as an insulation structure is used with a specified distance according to a design, as already suggested by Vinn.
Since the applicant has not established the criticality (see next paragraph below) of the claimed distance, it would have been obvious to one of ordinary skill in the art to use these values in the structure of Vinn, and to have a diode sized bigger than the openings of the insulating layer.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed dimensions or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 7, Vinn shows an insulating layer (e.g., [0025] “silicon nitride or silicon nitride on silicon oxide, that forms a good barrier”) on a surface of die 108, however it is silent about the thickness of the insulating layer being less than 10um.
However, it is noted that the specific claimed proportion between the thickness of the insulation layer being less than 10um, absent any criticality, is only considered to be the “optimum” thickness disclosed by Vin that a person having ordinary skill in the art would have been able to determine using routine experimentation based, among other things, on the desired insulating properties for being a good barrier for contaminants. (see Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained as long as an insulation structure is used with a minimal thickness, as already suggested by Vinn.
Since the applicant has not established the criticality (see next paragraph below) of the claimed proportion, it would have been obvious to one of ordinary skill in the art to use these values in the structure of Vinn.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed dimensions or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 14, Daubenspeck teaches the insulating layer comprises polyimide (e.g., passivation 205).
Regarding Claim 15, Chen ([0010]) teaches the lead frame is a QFN lead frame.
Regarding Claim 16, See comments from claim 1, as they would be considered repeated here.
Regarding Claim 18, Vinn shows a conductive adhesive layer (e.g., 104 [0026]) however it is silent in regards to the specific thickness being less than 10um.
However, it is noted that the specific claimed thickness, absent any criticality, is only considered to be the “optimum” thickness disclosed by Vinn that a person having ordinary skill in the art would have been able to determine using routine experimentation based, among other things, on the desired insulating properties for being a good barrier for contaminants. (see Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a conductive adhesive is used with a specified thickness to a design, as already suggested by Vinn.
Since the applicant has not established the criticality (see next paragraph below) of the claimed distance, it would have been obvious to one of ordinary skill in the art to use these values in the structure of Vinn, and to have a diode sized bigger than the openings of the insulating layer.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed dimensions or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 19, See comments from Par. 23-25 from claim 1, as they would be considered repeated here.
Regarding Claim 20, See comments from Par. 34 from claim 6, as they would be considered repeated here.
Claims 17 is rejected under 35 U.S.C. 103 as being unpatentable over Vinn /Chen/Daubenspeck/Yilmaz further in view of Wu (US 11133797 B1, Hereinafter Wu).
Regarding Claim 17, Vinn/Chen/Daubenspeck/Yilmaz discloses a first, second and third pin with an anode of the diode is connected to the first pin, and a cathode of the diode is connected to a second pin (Vinn, Figs 2-4). Vinn, in (Fig 1 [0010] )shows a capacitor connected between one pin and ground as a common arrangement for a boost converter. Vinn also shows two transistors (e.g., claim 12), however Vinn is silent in regards to both transistors sharing a common node. Vin is also silent in regards to the specific arrangement of capacitors and transistors as listed in the claim.
Wu, (e.g., Fig 1,2 , col 1-5), on the other hand and in a related field of power converters, teaches an arrangement to solve the technical problem of energy storage and power converter structures. Matsui teaches
a first pin (supply voltage (VDD), second pin (bootstrap voltage terminal VB) and a third pin (switch node VS),
a capacitor connected between second and third pin (bootstrap capacitor 140)
a bootstrap diode with the anode connected to the first pin, and the cathode connected to the second pin (e.g., anode 131 for coupling to a power supply voltage terminal VDD and a cathode 132 for coupling to a bootstrap voltage terminal VB).
A third pin connected to a common node of two transistors ( high-side transistor 191 (Q1) and a low-side transistor 192 (Q2) connected in series at a midpoint 195 between a power terminal 197 providing a voltage VPOWER and a ground terminal labeled PGND, both connected to VS)
Although Wu does not explicitly illustrate a decoupling capacitor connected between VDD and ground, It is well known that in typical gate-driver circuits, a decoupling capacitor is required and is connected between the supply (VDD) and ground to stabilize the driver supply. A person skilled in the art would select a position of the capacitor based on the storage needs of a typical gate driver circuit with a half bridge circuit including a high-side and low side transistor switches. Since the operation of decoupling capacitors is well known, it would have been obvious to combine a well-known element to yield the predictable result of stabilizing power supply in the gate driver circuit (MPEP 2143).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Vinn /Chen/Daubenspeck/Yilmaz further in view of Okamoto et al(JP 2015166110 A-PDF provided, Hereinafter Okamoto).
Regarding Claim 12, While Vinn shows a conductive adhesive layer (104), it does not show a welding layer that is lead-free solder with a thickness of 10-15um.
Okamoto (Fig 11), on the other hand and in a related field of packaging, teaches a lead free solder (Fig 11, Sn-based lead-free solder 3) that may be less than 50um.
However, it is noted that the specific claimed thickness of solder layer may be between 10-15um absent any criticality, is only considered to be the “optimum” thickness disclosed by Okamoto that a person having ordinary skill in the art would have been able to determine using routine experimentation based, among other things, on the desired insulating properties for being a good barrier for contaminants. (see Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained as long as an insulation structure is used with a minimal thickness, as already suggested by Okamoto.
Since the applicant has not established the criticality (see next paragraph below) of the claimed proportion, it would have been obvious to one of ordinary skill in the art to use these values in the structure of Vinn/Chen/Daubenspeck.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed dimensions or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 13, See comments from Claim 12, as they would be considered repeated here.
Allowable Subject Matter
Claims 8-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to the claims filed on 06/03/2026 have been considered but are moot in view of the new grounds of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEESA RIAZ BAIG whose telephone number is (571)272-0249. The examiner can normally be reached Monday-Friday 8am-5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANEESA RIAZ BAIG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
