Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to the claim to priority to United States Provisional Application Serial No. 63/343,476, filed May 18, 2022.
Election/Restrictions
Claims 1-20 are pending in this application.
Claims 8-14 remain withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected intention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on October 7, 2025.
The Examiner notes that claims 1-7 and 15-20 are examined and claims 8-14 are withdrawn.
Drawings
The drawings were received on February 2, 2026. These drawings are acceptable. Objections to the drawings are withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 15-16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim-766 (US 2022/0208766 A1) in view of Kim-424 (US 2023/0048424 A1).
With respect to claim 1, Kim-766 teaches in Fig. 2A:
A semiconductor structure, comprising:
a plurality of memory levels (Fig. 2A shows two memory cells MC stacked) stacked in a first direction (D1), each of the plurality of memory levels comprising:
a semiconductor layer (active layer ACT, para 36 “the active layer ACT may include a semiconductor material. The active layer ACT may include a silicon-containing layer or a silicon germanium-containing layer”);
a word line metal layer (word line WL, para. 38 “The word line WL may include a low-resistance metal material.”) above the semiconductor layer in the first direction and buried in a spacer (cell isolation layers LIL and VIL);
and an interface (bit line contact node BLC) on a cross section of the semiconductor layer (in contact with source region SR of active layer ACT);
and a bit line (bit line BL) in contact with the interface (BLC) of each of the plurality of memory levels (MC), the bit line extending in the first direction (D1),
wherein the bit line comprises metal material (para. 33 “The bit line BL may include a silicon-based material, a metal-based material…”), and the interface comprises silicide (para. 34 “the bit line contact node BLC may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof”).
Kim-766 fails to teach:
and an interface on a cross section of the semiconductor layer and not on a cross section of a spacer;
and a bit line (bit line BL) in contact with the interface (BLC) and the cross section of the spacer of each of the plurality of memory levels (MC)
Kim-424 teaches in Fig. 9I:
and an interface (bit line contact node BLC) on a cross section of the semiconductor layer (source/drain region SR) and not on a cross section of a spacer (interlayer dielectric layers 11 and 15);
and a bit line (bitline BL) in contact with the interface (BLC) and the cross section of the spacer (11 and 15) of each of the plurality of memory levels (Fig. 7 shows multiple memory levels in the device)
Kim-766 discloses the claimed invention except for the bitline contacts are in contact with a cross section of the spacer. Kim-424 discloses that it is known in the art to provide a bitline contact that only contacts the semiconductor layer, not the spacer. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the device of Kim-766 with the interface of Kim-424 that does not contact the spacer for the purpose of reducing the amount of interface material needed for the device, See MPEP 2144.
With respect to claim 2, Kim-766 further teaches:
wherein the semiconductor layer comprises silicon (active layer ACT, para 36 “the active layer ACT may include a semiconductor material. The active layer ACT may include a silicon-containing layer or a silicon germanium-containing layer”)
With respect to claim 5, Kim-766 further teaches:
wherein the spacer comprises (LIL) silicon nitride (para. 52 “The cell isolation layers LIL and VIL may include silicon oxide (SiO.sub.2)”).
With respect to claim 15, Kim-766 teaches in Fig. 2A:
A three dimensional (3D) dynamic random-access memory (DRAM) device (para. 26 “The memory cells MC may include memory cells of the three-dimensional (3D) DRAM having a 1T-1C (1 transistor-1 capacitor) structure”), comprising:
a plurality of memory levels (Fig. 2A shows two memory cells MC stacked) stacked in a first direction (D1), each of the plurality of memory levels comprising:
a semiconductor layer (active layer ACT, para 36 “the active layer ACT may include a semiconductor material. The active layer ACT may include a silicon-containing layer or a silicon germanium-containing layer”) having a first end (left) and a second end (right) in a second direction (D2) that is orthogonal to the first direction (D1);
a word line metal layer (word line WL, para. 38 “The word line WL may include a low-resistance metal material.”) buried in a spacer (interlayer dielectrics VIL and LIL);
and an interface (bit line contact node BLC) on a cross section at the first end (left) of the semiconductor layer (in contact with source region SR of active layer ACT);
and a bit line (bit line BL) in contact with the interface (BLC) of each of the plurality of memory levels (MC), the bit line extending in the first direction (D1),
wherein the bit line comprises metal material (para. 33 “The bit line BL may include a silicon-based material, a metal-based material…”), and the interface comprises silicide (para. 34 “the bit line contact node BLC may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof”).
Kim-766 fails to teach:
and an interface on a cross section of the semiconductor layer and not on a cross section of a spacer;
Kim-424 teaches in Fig. 9I:
and an interface (bit line contact node BLC) on a cross section of the semiconductor layer (source/drain region SR) and not on a cross section of a spacer (interlayer dielectric layers 11 and 15);
Kim-766 discloses the claimed invention except for the bitline contacts are in contact with a cross section of the spacer. Kim-424 discloses that it is known in the art to provide a bitline contact that only contacts the semiconductor layer, not the spacer. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the device of Kim-766 with the interface of Kim-424 that does not contact the spacer for the purpose of reducing the amount of interface material needed for the device, See MPEP 2144.
With respect to claim 16, Kim-766 further teaches:
wherein the semiconductor layer comprises silicon (active layer ACT, para 36 “the active layer ACT may include a semiconductor material. The active layer ACT may include a silicon-containing layer or a silicon germanium-containing layer”)
With respect to claim 19, Kim-766 further teaches:
wherein the spacer comprises (LIL) silicon nitride (para. 52 “The cell isolation layers LIL and VIL may include silicon oxide (SiO.sub.2)”).
Claims 3-4 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim-766 (US 2022/0208766 A1) and Kim-424 (US 2023/0048424 A1) as applied to independent claims 1 and 15 above and in view of Wilkerson (US 2019/0165046 A1).
With respect to claim 3, Kim-766/Kim-424 teaches all limitations of claim 1 upon which claim 3 depends. Kim-766/Kim-424 does not specify the metal and metal silicide used in the bitline and therefore does not teach:
wherein the metal material comprises molybdenum (Mo) and the interface comprises molybdenum silicide.
Wilkerson teaches:
wherein the metal material comprises molybdenum (Mo) (para. 146 “In some examples, the metal bit line comprises tungsten, tantalum, niobium, molybdenum, titanium, or a combination thereof”) and the interface comprises molybdenum silicide (para. 130 “in some examples, the metal silicon nitride layer comprises tungsten silicon nitride, tantalum silicon nitride, niobium silicon nitride, molybdenum silicon nitride, titanium silicon nitride, or a combination thereof.”)
The Examiner notes that in para. 41 teaches that the “metal silicon nitride” is not limiting to specific stoichiometric proportions and that the concentration of nitrogen can be as low as 1%. The Examiner therefore determines that the metal silicon nitride can be considered to be a metal silicide doped with nitrogen which therefore teaches the limitation of the instant application under broadest reasonable interpretation.
Kim-766/Kim-424 differs from the claimed invention in that Kim-766/Kim-424 does not teach the same specific metal and metal silicide as the claimed invention. Wilkerson teaches that a bit line metal layer can be made of Molybdenum and that the bit line may be covered with a silicide layer that includes molybdenum silicide. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to look to analogous art teachings of alternative suitable or useful material such as molybdenum and molybdenum silicide, as the selection of a known material based on its suitability for intended purpose deemed obvious. See MPEP 2144.07.
With respect to claim 4, Kim-766/Kim-424 teaches all limitations of claim 1 upon which claim 4 depends. Kim-766/Kim-424 does not specify the metal and metal silicide used in the bitline and therefore does not teach:
wherein the metal material comprises titanium (Ti) and the interface comprises titanium silicide.
Wilkerson teaches:
wherein the metal material comprises titanium (Ti) (para. 146 “In some examples, the metal bit line comprises tungsten, tantalum, niobium, molybdenum, titanium, or a combination thereof”) and the interface comprises titanium silicide (para. 130 “in some examples, the metal silicon nitride layer comprises tungsten silicon nitride, tantalum silicon nitride, niobium silicon nitride, molybdenum silicon nitride, titanium silicon nitride, or a combination thereof.”)
The Examiner notes that in para. 41 teaches that the “metal silicon nitride” is not limiting to specific stoichiometric proportions and that the concentration of nitrogen can be as low as 1%. The Examiner therefore determines that the metal silicon nitride can be considered to be a metal silicide doped with nitrogen which therefore teaches the limitation of the instant application under broadest reasonable interpretation.
Kim-766/Kim-424 differs from the claimed invention in that Kim-766/Kim-424 does not teach the same specific metal and metal silicide as the claimed invention. Wilkerson teaches that a bit line metal layer can be made of titanium and that the bit line may be covered with a silicide layer that includes titanium silicide. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to look to analogous art teachings of alternative suitable or useful material such as titanium and titanium silicide, as the selection of a known material based on its suitability for intended purpose deemed obvious. See MPEP 2144.07.
With respect to claim 17, Kim-766/Kim-424 teaches all limitations of claim 15 upon which claim 17 depends. Kim-766/Kim-424 does not specify the metal and metal silicide used in the bitline and therefore does not teach:
wherein the metal material comprises molybdenum (Mo) and the interface comprises molybdenum silicide.
Wilkerson teaches:
wherein the metal material comprises molybdenum (Mo) (para. 146 “In some examples, the metal bit line comprises tungsten, tantalum, niobium, molybdenum, titanium, or a combination thereof”) and the interface comprises molybdenum silicide (para. 130 “in some examples, the metal silicon nitride layer comprises tungsten silicon nitride, tantalum silicon nitride, niobium silicon nitride, molybdenum silicon nitride, titanium silicon nitride, or a combination thereof.”)
The Examiner notes that in para. 41 teaches that the “metal silicon nitride” is not limiting to specific stoichiometric proportions and that the concentration of nitrogen can be as low as 1%. The Examiner therefore determines that the metal silicon nitride can be considered to be a metal silicide doped with nitrogen which therefore teaches the limitation of the instant application under broadest reasonable interpretation.
Kim-766/Kim-424 differs from the claimed invention in that Kim-766/Kim-424 does not teach the same specific metal and metal silicide as the claimed invention. Wilkerson teaches that a bit line metal layer can be made of Molybdenum and that the bit line may be covered with a silicide layer that includes molybdenum silicide. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to look to analogous art teachings of alternative suitable or useful material such as molybdenum and molybdenum silicide, as the selection of a known material based on its suitability for intended purpose deemed obvious. See MPEP 2144.07.
With respect to claim 18, Kim-766/Kim-424 teaches all limitations of claim 15 upon which claim 18 depends. Kim-766/Kim-424 does not specify the metal and metal silicide used in the bitline and therefore does not teach:
wherein the metal material comprises titanium (Ti) and the interface comprises titanium silicide.
Wilkerson teaches:
wherein the metal material comprises titanium (Ti) (para. 146 “In some examples, the metal bit line comprises tungsten, tantalum, niobium, molybdenum, titanium, or a combination thereof”) and the interface comprises titanium silicide (para. 130 “in some examples, the metal silicon nitride layer comprises tungsten silicon nitride, tantalum silicon nitride, niobium silicon nitride, molybdenum silicon nitride, titanium silicon nitride, or a combination thereof.”)
The Examiner notes that in para. 41 teaches that the “metal silicon nitride” is not limiting to specific stoichiometric proportions and that the concentration of nitrogen can be as low as 1%. The Examiner therefore determines that the metal silicon nitride can be considered to be a metal silicide doped with nitrogen which therefore teaches the limitation of the instant application under broadest reasonable interpretation.
Kim-766/Kim-424 differs from the claimed invention in that Kim-766/Kim-424 does not teach the same specific metal and metal silicide as the claimed invention. Wilkerson teaches that a bit line metal layer can be made of titanium and that the bit line may be covered with a silicide layer that includes titanium silicide. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to look to analogous art teachings of alternative suitable or useful material such as titanium and titanium silicide, as the selection of a known material based on its suitability for intended purpose deemed obvious. See MPEP 2144.07.
Claims 6-7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim-766 (US 2022/0208766 A1) and Kim-424 (US 2023/0048424 A1) as applied to independent claims 1 and 15 above and in view of Kang (US 2021/0249415 A1).
With respect to claim 6, Kim-766/Kim-424 is silent to the dimensions of the semiconductor layer and therefore does not teach:
wherein the semiconductor layer has:
width of between 20 nm and 60 nm in a second direction that is orthogonal to the first direction,
thickness of between 10 nm and 30 nm in the first direction,
and a vertical spacing from the semiconductor layer of an adjacent memory level of the plurality of memory levels of between 140 nm and 180 nm.
Kang teaches:
wherein the semiconductor layer has:
width of between 50 nm and 300 nm in a second direction (first direction 20 (X) which is orthogonal to the bit line 170 and corresponds to the second direction of the instant application) that is orthogonal to the first direction (third direction 40 (Z)),
thickness of each layer of the unit cell (the semiconductor region 115 is one of the layers of the unit cell) between 15 nm and 30 nm in the first direction,
The ranges taught by Kang recited above overlap with the ranges of the claimed invention. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim-766/Kim-424 with the teaching of Kang to choose dimensions within the claimed ranges with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Kim-766, Kim-424 and Kang do not specify the vertical spacing of semiconductor layers. Kang shows in Fig. 23 that semiconductor layers are separated by two dielectric layers 230, a recessed sacrificial layer 300, and two gate oxides 325 but does not specify the dimensions of the layers.
It would be obvious to modify Kim-766/Kim-424/Kang to meet the limitation:
and a vertical spacing from the semiconductor layer of an adjacent memory level of the plurality of memory levels of between 140 nm and 180 nm.
It would have been an obvious matter of design choice to modify Kim-766/Kim-424/Kang to have a vertical spacing in the claimed range, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
With respect to claim 7, Kang further teaches:
wherein the bit line has:
width of between 40 nm and 120 nm in the second direction (para. 110 “in some embodiments, the bit line 170 has a length along the first direction 20 in the range of 75 nm to 90 nm”),
and thickness of between 40 nm and 120 nm in a third direction that is orthogonal to the first direction and the second direction (para. 110 “in some embodiments, the bit line 170 has a width along the second direction 20 in the range of 75 nm to 90 nm”).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Kim-766 in view of Kim-424 and Kang as explained above.
With respect to claim 20, Kim-766/Kim-424 is silent to the dimensions of the semiconductor layer and therefore does not teach:
wherein the semiconductor layer has:
width of between 20 nm and 60 nm in a second direction that is orthogonal to the first direction,
thickness of between 10 nm and 30 nm in the first direction,
and a vertical spacing from the semiconductor layer of an adjacent memory level of the plurality of memory levels of between 140 nm and 180 nm.
and the bit line has:
width of between 40 nm and 120 nm in the second direction,
and thickness of between 40 nm and 120 nm in a third direction that is orthogonal to the first direction and the second direction.
Kang teaches:
wherein the semiconductor layer has:
width of between 50 nm and 300 nm in a second direction (first direction 20 (X) which is orthogonal to the bit line 170 and corresponds to the second direction of the instant application) that is orthogonal to the first direction (third direction 40 (Z)),
thickness of each layer of the unit cell (the semiconductor region 115 is one of the layers of the unit cell) between 15 nm and 30 nm in the first direction,
wherein the bit line has:
width of between 40 nm and 120 nm in the second direction (para. 110 “in some embodiments, the bit line 170 has a length along the first direction 20 in the range of 75 nm to 90 nm”),
and thickness of between 40 nm and 120 nm in a third direction that is orthogonal to the first direction and the second direction (para. 110 “in some embodiments, the bit line 170 has a width along the second direction 20 in the range of 75 nm to 90 nm”).
The ranges taught by Kang recited above overlap with the ranges of the claimed invention. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim-766 with the teaching of Kang to choose dimensions within the claimed ranges with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Kim-766, Kim-424, and Kang do not specify the vertical spacing of semiconductor layers. Kang shows in Fig. 23 that semiconductor layers are separated by two dielectric layers 230, a recessed sacrificial layer 300, and two gate oxides 325 but does not specify the dimensions of the layers.
It would be obvious to modify Kim-766/Kim/424/Kang to meet the limitation:
and a vertical spacing from the semiconductor layer of an adjacent memory level of the plurality of memory levels of between 140 nm and 180 nm.
It would have been an obvious matter of design choice to modify Kim-766/Kim-424/Kang to have a vertical spacing in the claimed range, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897