Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 3, 2026 has been entered.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed May 26, 2026 and entered with the request for continued examination filed June 3, 2026. Claims 1, 6, 15, and 20 are amended. Claims 8-14 are cancelled. The Examiner notes that claims 1-7 and 15-20 are examined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5, 15-16, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim (US 2022/0208766 A.)
With respect to claim 1, Kim teaches in Fig. 2A:
A semiconductor structure, comprising:
a bit line (bit line BL) extending in a first direction (D1); and
a plurality of memory levels (Fig. 2A shows two memory cells MC stacked) stacked in a first direction (D1), each of the plurality of memory levels comprising:
a semiconductor layer (active layer ACT, para 36 “the active layer ACT may include a semiconductor material. The active layer ACT may include a silicon-containing layer or a silicon germanium-containing layer”);
a word line metal layer (word line WL, para. 38 “The word line WL may include a low-resistance metal material.”) above the semiconductor layer in the first direction
a spacer (cell isolation layers LIL and VIL) disposed between the word line metal layer (GM) and the bit line (BL) in a second direction (D2) that is orthogonal to the first direction (D1) and adjacent to the word line (GM) metal layer in the first direction (D1, LIL is adjacent in the first direction, VIL is disposed between the layers in the first direction);
and an interface (bit line contact node BLC) on a cross section of the semiconductor layer and in contact with the bit line (BL);
wherein the bit line comprises metal material (para. 33 “The bit line BL may include a silicon-based material, a metal-based material…”), and the interface comprises silicide (para. 34 “the bit line contact node BLC may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof”).
Kim fails to teach:
and an interface on a cross section of the semiconductor layer and not on a cross section of a spacer;
and a bit line (bit line BL) in contact with the interface (BLC) and the cross section of the spacer of each of the plurality of memory levels (MC)
With respect to claim 2, Kim further teaches:
wherein the semiconductor layer comprises silicon (active layer ACT, para 36 “the active layer ACT may include a semiconductor material. The active layer ACT may include a silicon-containing layer or a silicon germanium-containing layer”)
With respect to claim 5, Kim further teaches:
wherein the spacer comprises (LIL) silicon nitride (para. 52 “The cell isolation layers LIL and VIL may include silicon oxide (SiO.sub.2)”).
With respect to claim 15, Kim teaches in Fig. 2A:
A three dimensional (3D) dynamic random-access memory (DRAM) device (para. 26 “The memory cells MC may include memory cells of the three-dimensional (3D) DRAM having a 1T-1C (1 transistor-1 capacitor) structure”), comprising:
a bit line (BL) extending in a first direction (D1); and
a plurality of memory levels (Fig. 2A shows two memory cells MC stacked) stacked in the first direction (D1), each of the plurality of memory levels comprising:
a semiconductor layer (active layer ACT, para 36 “the active layer ACT may include a semiconductor material. The active layer ACT may include a silicon-containing layer or a silicon germanium-containing layer”) having a first end (left) and a second end (right) in a second direction (D2) that is orthogonal to the first direction (D1);
a word line metal layer (word line WL, para. 38 “The word line WL may include a low-resistance metal material.”);
a spacer (interlayer dielectrics VIL and LIL) disposed between the word line metal (GM) and the bit line (BL) in the second direction (D2) and adjacent to the word line metal layer in the first direction (D1, LIL is adjacent in the first direction and VIL is between GM and BL in the second direction);
and an interface (bit line contact node BLC) on a cross section at the first end (left) of the semiconductor layer (in contact with source region SR of active layer ACT) and in contact with the bit line (bit line BL),
wherein the bit line comprises metal material (para. 33 “The bit line BL may include a silicon-based material, a metal-based material…”), and the interface comprises silicide (para. 34 “the bit line contact node BLC may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof”).
With respect to claim 16, Kim further teaches:
wherein the semiconductor layer comprises silicon (active layer ACT, para 36 “the active layer ACT may include a semiconductor material. The active layer ACT may include a silicon-containing layer or a silicon germanium-containing layer”)
With respect to claim 19, Kim further teaches:
wherein the spacer comprises (LIL) silicon nitride (para. 52 “The cell isolation layers LIL and VIL may include silicon oxide (SiO.sub.2)”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022/0208766 A1) as applied to independent claims 1 and 15 above and in view of Wilkerson (US 2019/0165046 A1).
With respect to claim 3, Kim teaches all limitations of claim 1 upon which claim 3 depends. Kim does not specify the metal and metal silicide used in the bitline and therefore does not teach:
wherein the metal material comprises molybdenum (Mo) and the interface comprises molybdenum silicide.
Wilkerson teaches:
wherein the metal material comprises molybdenum (Mo) (para. 146 “In some examples, the metal bit line comprises tungsten, tantalum, niobium, molybdenum, titanium, or a combination thereof”) and the interface comprises molybdenum silicide (para. 130 “in some examples, the metal silicon nitride layer comprises tungsten silicon nitride, tantalum silicon nitride, niobium silicon nitride, molybdenum silicon nitride, titanium silicon nitride, or a combination thereof.”)
The Examiner notes that in para. 41 teaches that the “metal silicon nitride” is not limiting to specific stoichiometric proportions and that the concentration of nitrogen can be as low as 1%. The Examiner therefore determines that the metal silicon nitride can be considered to be a metal silicide doped with nitrogen which therefore teaches the limitation of the instant application under broadest reasonable interpretation.
Kim differs from the claimed invention in that Kim does not teach the same specific metal and metal silicide as the claimed invention. Wilkerson teaches that a bit line metal layer can be made of Molybdenum and that the bit line may be covered with a silicide layer that includes molybdenum silicide. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to look to analogous art teachings of alternative suitable or useful material such as molybdenum and molybdenum silicide, as the selection of a known material based on its suitability for intended purpose deemed obvious. See MPEP 2144.07.
With respect to claim 4, Kim teaches all limitations of claim 1 upon which claim 4 depends. Kim does not specify the metal and metal silicide used in the bitline and therefore does not teach:
wherein the metal material comprises titanium (Ti) and the interface comprises titanium silicide.
Wilkerson teaches:
wherein the metal material comprises titanium (Ti) (para. 146 “In some examples, the metal bit line comprises tungsten, tantalum, niobium, molybdenum, titanium, or a combination thereof”) and the interface comprises titanium silicide (para. 130 “in some examples, the metal silicon nitride layer comprises tungsten silicon nitride, tantalum silicon nitride, niobium silicon nitride, molybdenum silicon nitride, titanium silicon nitride, or a combination thereof.”)
The Examiner notes that in para. 41 teaches that the “metal silicon nitride” is not limiting to specific stoichiometric proportions and that the concentration of nitrogen can be as low as 1%. The Examiner therefore determines that the metal silicon nitride can be considered to be a metal silicide doped with nitrogen which therefore teaches the limitation of the instant application under broadest reasonable interpretation.
Kim differs from the claimed invention in that Kim does not teach the same specific metal and metal silicide as the claimed invention. Wilkerson teaches that a bit line metal layer can be made of titanium and that the bit line may be covered with a silicide layer that includes titanium silicide. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to look to analogous art teachings of alternative suitable or useful material such as titanium and titanium silicide, as the selection of a known material based on its suitability for intended purpose deemed obvious. See MPEP 2144.07.
With respect to claim 17, Kim teaches all limitations of claim 15 upon which claim 17 depends. Kim does not specify the metal and metal silicide used in the bitline and therefore does not teach:
wherein the metal material comprises molybdenum (Mo) and the interface comprises molybdenum silicide.
Wilkerson teaches:
wherein the metal material comprises molybdenum (Mo) (para. 146 “In some examples, the metal bit line comprises tungsten, tantalum, niobium, molybdenum, titanium, or a combination thereof”) and the interface comprises molybdenum silicide (para. 130 “in some examples, the metal silicon nitride layer comprises tungsten silicon nitride, tantalum silicon nitride, niobium silicon nitride, molybdenum silicon nitride, titanium silicon nitride, or a combination thereof.”)
The Examiner notes that in para. 41 teaches that the “metal silicon nitride” is not limiting to specific stoichiometric proportions and that the concentration of nitrogen can be as low as 1%. The Examiner therefore determines that the metal silicon nitride can be considered to be a metal silicide doped with nitrogen which therefore teaches the limitation of the instant application under broadest reasonable interpretation.
Kim differs from the claimed invention in that Kim does not teach the same specific metal and metal silicide as the claimed invention. Wilkerson teaches that a bit line metal layer can be made of Molybdenum and that the bit line may be covered with a silicide layer that includes molybdenum silicide. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to look to analogous art teachings of alternative suitable or useful material such as molybdenum and molybdenum silicide, as the selection of a known material based on its suitability for intended purpose deemed obvious. See MPEP 2144.07.
With respect to claim 18, Kim teaches all limitations of claim 15 upon which claim 18 depends. Kim does not specify the metal and metal silicide used in the bitline and therefore does not teach:
wherein the metal material comprises titanium (Ti) and the interface comprises titanium silicide.
Wilkerson teaches:
wherein the metal material comprises titanium (Ti) (para. 146 “In some examples, the metal bit line comprises tungsten, tantalum, niobium, molybdenum, titanium, or a combination thereof”) and the interface comprises titanium silicide (para. 130 “in some examples, the metal silicon nitride layer comprises tungsten silicon nitride, tantalum silicon nitride, niobium silicon nitride, molybdenum silicon nitride, titanium silicon nitride, or a combination thereof.”)
The Examiner notes that in para. 41 teaches that the “metal silicon nitride” is not limiting to specific stoichiometric proportions and that the concentration of nitrogen can be as low as 1%. The Examiner therefore determines that the metal silicon nitride can be considered to be a metal silicide doped with nitrogen which therefore teaches the limitation of the instant application under broadest reasonable interpretation.
Kim differs from the claimed invention in that Kim does not teach the same specific metal and metal silicide as the claimed invention. Wilkerson teaches that a bit line metal layer can be made of titanium and that the bit line may be covered with a silicide layer that includes titanium silicide. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to look to analogous art teachings of alternative suitable or useful material such as titanium and titanium silicide, as the selection of a known material based on its suitability for intended purpose deemed obvious. See MPEP 2144.07.
Claims 6-7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022/0208766 A1) as applied to independent claims 1 and 15 above and in view of Kang (US 2021/0249415 A1).
With respect to claim 6, Kim is silent to the dimensions of the semiconductor layer and therefore does not teach:
wherein the semiconductor layer has:
width of between 20 nm and 60 nm in a third direction that is orthogonal to the first direction and the second direction,
thickness of between 10 nm and 30 nm in the first direction,
and a vertical spacing from the semiconductor layer of an adjacent memory level of the plurality of memory levels of between 140 nm and 180 nm.
Kang teaches:
wherein the semiconductor layer has:
width of between 50 nm and 300 nm in a third direction (second direction 30 (Y), para. [0104] “in some embodiments, the width of the active region 115 along the second direction 30 is in the range of 50 nm to 300 nm”) which is orthogonal to the bit line 170 and corresponds to the third direction of the instant application) that is orthogonal to the first direction (third direction 40 (Z)) and the second direction (first direction 20 (X)),
thickness of each layer of the unit cell (the semiconductor region 115 is one of the layers of the unit cell) between 15 nm and 30 nm in the first direction,
The ranges taught by Kang recited above overlap with the ranges of the claimed invention. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teaching of Kang to choose dimensions within the claimed ranges with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Kim and Kang do not specify the vertical spacing of semiconductor layers. Kang shows in Fig. 23 that semiconductor layers are separated by two dielectric layers 230, a recessed sacrificial layer 300, and two gate oxides 325 but does not specify the dimensions of the layers.
It would be obvious to modify Kim/Kang to meet the limitation:
and a vertical spacing from the semiconductor layer of an adjacent memory level of the plurality of memory levels of between 140 nm and 180 nm.
It would have been an obvious matter of design choice to modify Kim/Kang to have a vertical spacing in the claimed range, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
With respect to claim 7, Kang further teaches:
wherein the bit line has:
width of between 40 nm and 120 nm in the second direction (para. 110 “in some embodiments, the bit line 170 has a length along the first direction 20 in the range of 75 nm to 90 nm”),
and thickness of between 40 nm and 120 nm in a third direction that is orthogonal to the first direction and the second direction (para. 110 “in some embodiments, the bit line 170 has a width along the second direction 20 in the range of 75 nm to 90 nm”).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Kim in view of Kang as explained above.
With respect to claim 20, Kim is silent to the dimensions of the semiconductor layer and therefore does not teach:
wherein the semiconductor layer has:
width of between 20 nm and 60 nm in a third direction that is orthogonal to the first direction and the second direction,
thickness of between 10 nm and 30 nm in the first direction,
and a vertical spacing from the semiconductor layer of an adjacent memory level of the plurality of memory levels of between 140 nm and 180 nm.
and the bit line has:
width of between 40 nm and 120 nm in the second direction,
and thickness of between 40 nm and 120 nm in a third direction that is orthogonal to the first direction and the second direction.
Kang teaches:
wherein the semiconductor layer has:
width of between 50 nm and 300 nm in a third direction ((second direction 30 (Y), para. [0104] “in some embodiments, the width of the active region 115 along the second direction 30 is in the range of 50 nm to 300 nm” which is orthogonal to the bit line 170 and corresponds to the third direction of the instant application) that is orthogonal to the first direction (third direction 40 (Z)) and the second direction (first direction 20),
thickness of each layer of the unit cell (the semiconductor region 115 is one of the layers of the unit cell) between 15 nm and 30 nm in the first direction,
wherein the bit line has:
width of between 40 nm and 120 nm in the second direction (para. 110 “in some embodiments, the bit line 170 has a length along the first direction 20 in the range of 75 nm to 90 nm”),
and thickness of between 40 nm and 120 nm in a third direction that is orthogonal to the first direction and the second direction (para. 110 “in some embodiments, the bit line 170 has a width along the second direction 20 in the range of 75 nm to 90 nm”).
The ranges taught by Kang recited above overlap with the ranges of the claimed invention. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim with the teaching of Kang to choose dimensions within the claimed ranges with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Kim, and Kang do not specify the vertical spacing of semiconductor layers. Kang shows in Fig. 23 that semiconductor layers are separated by two dielectric layers 230, a recessed sacrificial layer 300, and two gate oxides 325 but does not specify the dimensions of the layers.
It would be obvious to modify Kim/Kang to meet the limitation:
and a vertical spacing from the semiconductor layer of an adjacent memory level of the plurality of memory levels of between 140 nm and 180 nm.
It would have been an obvious matter of design choice to modify Kim/Kang to have a vertical spacing in the claimed range, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Response to Arguments
Applicant's arguments filed May 26, 2026 have been fully considered but they are not persuasive. The Examiner has considered the amended claims and finds that the prior art of record still reads on the claims as described above.
Conclusion
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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