DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 6-8, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U. S. Patent Application Publication No. 2010/0261118 (hereinafter referred to as Liu).
Liu, in paragraph nos. [0001]-[0004], [0034], discloses a process for planarizing the non-uniform coating of the photoresist layer formed over the varying topography of the semiconductor substrate ([0015]). Liu, in [0013], discloses that the semiconductor substrate includes shallow trench isolation (STI) region that separates two sections (active regions), and in each sections (regions) are features (plurality of features, 110a, 110b, and 110c each of different height) of different thicknesses (different heights) and is the claimed uneven strip structures. Liu, in [0031], discloses that the substrate with the features that includes the STI includes layers of gate electrode, sacrificial layers etc., i.e., the substrate also includes a stack structure. Liu, in [0032], discloses coating a photoresist layer over the structures (including the stack structures) on the substrate resulting in a non-uniform coating with different heights (due to varied thicknesses of the photoresist formed corresponding to the varying topography of the underlying stack features, see figure 1, and substrate/target of figure 4) with at least in one portion the height is greater than the height of the photoresist layer formed in another portion of the substrate and includes the claimed first thickness and second thickness H1 and H2 (See Liu’s T5 > T6 or T3>T2). Liu, in [0020], lines 1-6, and in [0021], discloses that the photomask to be used for the exposure includes a pattern associated with the main feature (to be imaged in one region of the target/substrate) and also includes plurality of features of sub-resolution features (auxiliary pattern, unit patterns) i.e., the plurality (array) of sub-resolution assist features (SRAF) includes rows and columns of the sub-resolution assist features of integers greater than 1. Liu, in [0037], discloses using the photomask to exposure the different regions of the photoresist coated semiconductor substrate (includes the different regions of the substrate with different thickness of the photoresist, thereby different heights of the photoresist layer) at the same time (simultaneously, see figure 4). Liu, in [0016]-[0017], [0021], discloses that the intensity/energies of the exposure at different locations of the photoresist is varied in accordance to the thickness of the photoresist using the gradated photomask thereby allowing different thicknesses of the photoresist to be developed at different positions of the substrate such that greater exposure energy at a target surface with greater height. Liu, discloses in [0024], that using/varying the density of the sub-resolution features so as to vary the energy of the radiation exposure traversing to the photoresist layer such that in some sections the radiation incident is blocked and in some sections the exposure intensity is only decreased i.e., in some regions (sections) only part of the photoresist is developed and in some regions (sections) none of the photoresist is developed and in some regions the main feature is formed (imaged, lines 1-3 of [0020], section 416 of figure 5, pattern transferred in the second region) such that after the exposure using the gradated photomask and after development (transferred) the thickness of the photoresist is substantially planar (see [0034], i.e., the first region and second region photoresist thickness, claimed thickness in the first region becomes H2) (claims 1, and 7). Liu, in [0021], discloses that the plurality of features (unit patterns, 312)) that constitute the sub-resolution assist features includes the claimed rectangular structures , see reference 312 of figure 3b (claim 3). Liu, in [0038], discloses the photoresist is developed using a positive tone developer such as TMAH i.e., the photoresist is a positive tone photoresist (claim 6). Liu, in [0020]-[0021], discloses the use of sub-resolution assist features (claimed auxiliary pattern) that are non-printing features i.e., inherently less than a minimum dimension according to a design rule of an exposure layer (claim 8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-5, is/are rejected under 35 U.S.C. 103 as being unpatentable over U. S. Patent Application Publication No. 2010/0261118 (hereinafter referred to as Liu) in view of U. S. Patent Application Publication No. 2005/0026047 (hereinafter referred to as Yang).
Liu is discussed in paragraph no. 3, above.
Liu, in [0016]-[0017], [0021], [0024], discloses that the sub-resolution features are non-printing features that are arranged at different spacings (varying the density of the features) in different sections of the mask and that the features are sub-resolution non-printing features i.e., the dimension of the sub-resolution feature is less than the wavelength of the light used for exposure is less DUV wavelengths i.e., includes the dimension of 30nm.
The difference between the claims and Liu is that Liu does not disclose that spacing between two of the sub-resolution features is 40nm (claim 4) or that the dimension of the sub-resolution feature is 30nm (claim 5).
Yang, in the abstract, and in [0033], and in figure 8, discloses a mask with a plurality of assist features (auxiliary unit patterns) that are positioned at different sections of the mask, wherein the assist features can have a width that is larger than one-fourth of the wavelength of the exposure and the spacing between adjacent assist features is at least equal to larger than the width of the assist feature.
Therefore, it would be obvious to a skilled artisan to modify Liu by employing the dimensions of the assist features taught by Yang because Liu teaches that the non-printing features are sub-resolution assist features and as disclosed in figure 3b, the assist features in one section are positioned at a space width that is equal to the width of the assist features, and Liu teaches using DUV wavelengths for exposure i.e., wavelength as low as 100nm for exposure, and the sub resolution features include the claimed dimension and spacing, and Yang, in [0033], teaches using greater than one-fourth the wavelength of exposure as the dimensions (both width and spacing) of the assist features in order to have the features on the mask as non-resolvable features.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over U. S. Patent Application Publication No. 2010/0261118 (hereinafter referred to as Liu) in view of U. S. Patent Application Publication No. 2015/0303057 (hereinafter referred to as Lee) and U. S. Patent Application Publication No. 2021/0287912 (hereinafter referred to as Shiba).
Liu is discussed in paragraph no. 3 above.
Liu in [0031], discloses that the semiconductor substrate can includes sacrificial hard mask layers, gate layers etc.
The difference between the claims and Liu is that Liu does not specify the layers recited in claim 2.
Lee, in [0013], discloses that the substrate includes STI and that the semiconductor substrate includes gate dielectric layers, hard mask layer, doped silicon containing material layers, insulating layers etc., and Lee in [0013]-[0023], discloses forming planarizing ILD layer that includes silicon oxide , SiON or other low dielectric constant material, followed by interlayers such as silicon oxide or its matrix and silicon oxynitride and teaches subjecting the interlayer matrix to passivation with NF3 i.e., forming a passivating layer that include the NF3 component, and then coating a capping layer of TiN on the stack.
The difference between the claims and Liu in view of Lee is that Liu in view of Lee does not disclose that the SiON containing layers are the claimed nitrogen doped SiOC layers.
Shiba, in [0050], discloses that the silicon oxynitride or silicon nitride film include carbon and that SiON film include doped content of nitrogen and carbon to form SiOCN films.
Therefore, it would be obvious to a skilled artisan to modify Liu by employing the layers taught by Lee and Shiba because Liu teaches that the substrate is a semiconductor substrate and includes sacrificial and/or hardmask layers that include insulating layers, and Lee teaches that the semiconductor substrate includes hardmask and insulating layers such as silicon oxide containing layers, and Lee in [0011], teaches passivating using NF3 (Lee in [0017]) the interlayers to reduce the number of interface and bulk defects, and Shiba teaches in [0124]-[0125] and [0143] that the insulating and sacrificial layers includes silicon nitride containing film and silicon oxide films wherein the silicon nitride film include SiOCN film.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daborah Chacko-Davis whose telephone number is (571) 272-1380. The examiner can normally be reached on 9:30AM-6:00PM EST Mon-Fri. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark F. Huff can be reached on (571) 272-1385. The fax phone number for the organization where this application or proceeding is assigned is 571-272-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DABORAH CHACKO-DAVIS/Primary Examiner, Art Unit 1737 March 6, 2026.