Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 21, 2026 has been entered.
Response to Arguments
With regards to the amendments submitted on 07/21/2026, amended claims 1 and 13 overcome the previous prior art rejection. The arguments regarding Kim et al and Zang et al on pages 7-10 are not applicable as claims 1-12 are now in a state of allowance. In regards to the arguments on pages 10-11 with regards to the curvature of the gate dielectric layer, per MPEP 2113 Product by process, the method in which a limitation is formed, such as a curve, cannot be examined in a product claim. Claim 13 is a claim of a curvature of the gate dielectric, whether the curve is formed via one way or another is immaterial to the structural product of a curve existing. Thus, only the product that is claimed is examined and not the method that creates the product. In the particular case, this means the curvature is examined whether the curve in the dielectric layer is formed for one reason or another, the mere presence of a curved dielectric layer reads onto the specific claim language. In light of this, the arguments on pages 10-11 with regards to the curve are found not persuasive. Additionally, with regards to the argument about the position of the curved dielectric layer in Yamaguchi et al as disclosed on pages 11-12, upon further search and consideration a new piece of art is found to read onto the claims considering the amendment to claim 13. If the applicant wishes to expound on the nature of the curve and how it is unique to other prior art, the applicant can further detail those in the claim language. Lastly, the arguments with respect to claim 14 found on pages 11-12 with regards to a change in size and shape, in particular for claim 14 with regards to the angle the curve makes with the substrate, a 90 degree angle, greater than or less than would have no significant effect on the function of the device, additionally error tolerances within and around 90 degrees could easily render the curve to be close to 90 degrees, below or above. Thus the arguments are not found persuasive and the rejection of claim 14 is maintained. Note, claim 14 no longer uses Yamaguchi et al but the rational is still the same.
Allowable Subject Matter
Claims 1-12 are allowed. In particular, the limitations of claim 1 “after forming the patterned mask, etching the substrate and the first gate dielectric layer along a sidewall of the patterned mask to form a recess between the first gate structure and the second gate structure and to form a curve on a sidewall of the first gate dielectric layer” in combination with the other limitations of claim 1 overcome the prior art. In particular, Zang et al (US 10629694) details a patterned mask that allows for etching but does not specifically disclose etching the first gate dielectric layer along a sidewall of the patterned mask in the step of after forming the patterned mask. Additionally, Cheng (US 20200066898) details a patterned mask (figure 1E) but fails to disclose etching along a sidewall of the patterned mask. Thus, claim 1 is in a state of allowance. Claims 2-12, as dependent upon claim 1 and furthering the scope of claim 1, are also in a state of allowance as their limitations in combination with the limitations of their parent claim, claim 1, overcome the prior art.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20230059628 A1) in view of Cho et al (US 20230056095).
Kim et al teaches
[claim 13] A semiconductor device, comprising: a substrate comprising a medium-voltage (MV) region and a low-voltage (LV) region (figure 1, paragraph 0047, section 11 is the LV region, and element 12 is the MV region);
a first gate structure on the MV region (paragraph 0064, figure 3, element 45 is the first gate structure in the MV region [element 12]),
wherein the first gate dielectric layer is disposed between the substrate and the first gate electrode (paragraphs 0058-0059, figures 2D-2E, where element 35 is the dielectric layer situated between the substrate [element 21] and the first gate electrode [element 45]);
However, Kim et al does not specifically disclose
[claim 13] wherein the first gate structure comprises: a first gate dielectric layer on the substrate, wherein a cross-sectional profile of a sidewall of the first gate dielectric layer comprises a curve; a first gate electrode on the first gate dielectric layer; and a first epitaxial layer adjacent to the first gate structure.
[claim 15] wherein a width of a bottom surface of the first gate dielectric layer is greater than a width of a top surface of the first gate dielectric layer.
However, Cho et al does teach
[claim 13] wherein the first gate structure comprises: a first gate dielectric layer on the substrate, wherein a cross-sectional profile of a sidewall of the first gate dielectric layer comprises a curve (figure 3, paragraph 0038, where element 124 is the gate dielectric layer on the substrate [element 100], where the cross-sectional profile of the sidewall is curved, note the cross sectional view is looking in the horizontal direction from left to right on figure 3 and the gate dielectric layer starts flat and then curves upward showing a curve in it’s cross-sectional area).
a first gate electrode on the first gate dielectric layer (figure 3, paragraph 0038, where element 132 is the first gate electrode on the first gate dielectric layer [element 124]).
and a first epitaxial layer adjacent to the first gate structure (figure 3, paragraph 0060, where elements F11, F12, etc.. is the epitaxial layer adjacent to the first gate electrode [element 132]).
[claim 15] wherein a width of a bottom surface of the first gate dielectric layer is greater than a width of a top surface of the first gate dielectric layer (figure 3, paragraph 0038, where the gate dielectric layer [element 124] is wider on the bottom than on the top, as the curves are wider on the bottom thus making a larger surface area and a greater length than the top portion of the gate dielectric layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Kim et al to incorporate the teachings of Cho et al in order to curve the gate dielectric layer under the gate electrode to match the shape of the curved gate electrode, which is curved to maximize electric uniformity thus maximizing the efficiency of the device by minimizing any non-uniform electric field degradation.
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20230059628 A1), and Cho et al (US 20230056095).
Kim et al as modified teaches all of the limitations of the parent claim, claim 13, but does not specifically disclose
[claim 14] wherein an angle included by a top surface of the substrate and the curve is less than 90 degrees.
However, according to MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS B. Changes in Shape
In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Kim et al as modified to make the curve with respect to the top of the substrate to be less than 90 degrees in order to fulfill a particular configuration of the gate electrode and play around with different design choices to make the best possible device.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20230059628 A1) and Cho et al (US 20230056095) and in further view of Yamaguchi et al (US 20110037103 A1).
Kim et al as modified teaches all of the limitations of the parent claim, claim 13, but does not specifically disclose
[claim 16] further comprising: a second gate structure on the LV region, wherein the second gate structure comprises: a second gate dielectric layer on the substrate, wherein a sidewall of the second gate dielectric layer comprises a vertical surface; and a second gate electrode on the second gate dielectric layer; and a second epitaxial layer adjacent to the second gate structure.
[claim 17] wherein an angle included by a top surface of the substrate and the vertical surface is equal to 90 degrees.
[claim 18] wherein a width of a bottom surface of the second gate dielectric layer is equal to a width of a top surface of the second gate dielectric layer.
However, Yamaguchi et al does teach
[claim 16] further comprising: a second gate structure on the LV region, wherein the second gate structure comprises: a second gate dielectric layer on the substrate, wherein a sidewall of the second gate dielectric layer comprises a vertical surface (figure 10, paragraphs 0076-0078, where section 1A is located in the LV region of Kim et al and element GE1 in section 1A is in place of the gate electrode 43 in Kim et al [maintaining structural similarities between the two], and a second gate dielectric layer [element 7 in section 1A] is on the substrate and creates a sidewall that is vertical up and around the gate electrode [element GE1 in section 1A]);
and a second gate electrode on the second gate dielectric layer; and a second epitaxial layer adjacent to the second gate structure (figure 10, paragraphs 0076-0078 where element GE1 in section 1A is the second gate electrode and element 10 [lefthand side of element GE1 in section 1B] is the second epitaxial layer and adjacent to the second gate electrode).
[claim 17] wherein an angle included by a top surface of the substrate and the vertical surface is equal to 90 degrees (figure 10, paragraphs 0076-0078, where element 7 in section 1A is vertical and at a 90 degree angle to the substrate in section 1A).
[claim 18] wherein a width of a bottom surface of the second gate dielectric layer is equal to a width of a top surface of the second gate dielectric layer (figure 5, element 7 has a portion [located on the side of the gate electrodes extending vertically where the width of the bottom surface of said layer is equal to the width of the top surface).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Kim et al as modified to incorporate the teachings of Yamaguchi et al in order to maximize efficiency by depositing dielectrics in specific regions without singulating or separating the regions so as to minimize the amount of material used while maximizing the density of the device.
Conclusion
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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