Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
With regards to the applicants’ arguments filed on 04/14/2026, the amendments made to independent claim 1 overcomes the previous USC 112(b) rejection and the USC 112(b) rejection is rescinded.
With response to the applicants arguments regarding Kim et al, Zang et al, and Yamaguchi et al on pages 8-12 with respect to the amended material, specifically the curvature of the sidewall of the dielectric layer, the amendment overcomes the previous prior art rejection. However, upon further search and consideration and new rejection is formulated below upon the same references but said references are not used to read onto the curvature of the dielectric wall, but rather an argument from the MPEP.
It is recommended to the applicant to incorporate some temporal language and more specific language with regards to the curvature of the dielectric layer. In particular, no temporal language is stated in the independent claims 1 and 13, thus methods can be read in any order unless specifically designated by the claim language. Incorporating some language such as “after forming” would aid the case. Additionally, with regards to the curvature of the dielectric layer, if there is a specific cross section of the dielectric layer that is curved and the applicant wants to claim this specific curvature, it is recommended to establish directions in the claim language and then specify a curvature with respect to certain directions claims to ensure the curvature is in reference to a certain cross sectional-view instead of the broadest reasonable interpretation of the word “curved” which in the present case is interpreted broadly as it by nature is a broad word without further clarification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20230059628 A1) in view of Zang et al (US 10629694 B1).
Kim et al teaches
[claim 1] A method for fabricating a semiconductor device, comprising: providing a substrate comprising a medium-voltage (MV) region and a low-voltage (LV) region (paragraphs 0045 and 0048, figures 1-2A, where element 12 is the medium voltage region, element 11 is the low voltage region all formed on a substrate [element 21]),
forming a first gate structure and a second gate structure on the MV region (paragraph 0059, figure 2D, where element 45 and 47 are the formed first and second gate structure in the medium voltage region [region 12], and element 43 is the second gate structure formed in the low voltage region [region 11]),
wherein the first gate structure comprises a first gate dielectric layer on the substrate and a first gate electrode on the first gate dielectric layer, wherein the first gate dielectric layer is disposed between the substrate and the first gate electrode (paragraphs 0058-0059, figures 2D-2E, where element 45 and 35 comprise the first gate structure, where element 35 is the first gate dielectric layer on the substrate [element 21] and situated between the gate electrode [element 45] and the substrate [element 21]),
However, Kim et al does not specifically disclose
[claim 1] and wherein a sidewall of the first gate dielectric layer comprises a curve, forming a patterned mask on the MV region, wherein the patterned mask covers the first gate structure and the second gate structure and exposes the substrate between the first gate structure and the second gate structure; and forming a first epitaxial layer between the first gate structure and the second gate structure.
However, Zang et al does teach
[claim 1] forming a patterned mask on the MV region, wherein the patterned mask covers the first gate structure and the second gate structure and exposes the substrate between the first gate structure and the second gate structure (col 6 lines 3-13, figure 7A, where elements 24 and 26 are the first and second gate structures in place of the first and second gate structures of Kim et al in the medium voltage area, and element 58 is the mask which covers the gate structures but leaves a vacancy to the substrate);
and forming a first epitaxial layer between the first gate structure and the second gate structure (col 4 lines 37-43, figure 7A, where element 44 is situated between elements 24 and 26 and is an epitaxial layer).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Kim et al to incorporate the teachings of Zang et al in order to create a self-aligning transistor by putting the mask only over the gate electrode and not over the source and drain regions to increase precision of the gate and reducing any potential parasitic capacitance between the source and drain and the gate.
However, Kim et al as modified does not specifically disclose
[claim 1] and wherein a sidewall of the first gate dielectric layer comprises a curve.
However, according to MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
B. Changes in Shape
In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Kim et al as modified to have changed the shape of a sidewall of the dielectric layer from being a straight-edge as presented to have some curve shaped as the shape is not paramount for the function of the device.
Claim(s) 2-6, 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20230059628 A1), and Zang et al (US 10629694 B1) in further view of Yamaguchi et al (US 20110037103 A1).
Kim et al as modified teaches all of the limitations of the parent claim, claim 1, and Kim et al further teaches
[claim 2] The method of claim 1, wherein the LV region comprises a first transistor region and a second transistor region (paragraph 0059, figure 2D, section 11 is the LV region comprising a first transistor region which contains elements 41 and 31, and a second transistor region containing elements 43 and 33),
the method comprising: forming a third gate structure on the first transistor region and a fourth gate structure on the second transistor region (paragraph 0059, figure 2D, where elements 41 and 43 are the third and fourth gate structure, respectively, in the first and second transistor region.
However, Kim et al as modified does not specifically disclose
[claim 2] forming the patterned mask on the MV region and the second transistor region; forming the first epitaxial layer on the MV region and a second epitaxial layer adjacent to the third gate structure; and forming a third epitaxial layer adjacent to the fourth gate structure.
[claim 3] wherein the patterned mask covers the MV region and the second transistor region while exposing the first transistor region.
[claim 4] wherein the patterned mask covers the second transistor region completely.
[claim 5] wherein the first epitaxial layer and the second epitaxial layer comprise same conductive type.
[claim 6] wherein the first epitaxial layer and the third epitaxial layer comprise different conductive type.
[claim 9] wherein a width of a bottom surface of the first gate dielectric layer is greater than a width of a top surface of the first gate dielectric layer.
[claim 10] wherein the third gate structure comprises: a third gate dielectric layer on the substrate, wherein a sidewall of the third gate dielectric layer comprises a vertical surface; and a third gate electrode on the third gate dielectric layer.
[claim 11] wherein an angle included by a top surface of the substrate and the vertical surface is equal to 90 degrees.
[claim 12] wherein a width of a bottom surface of the third gate dielectric layer is equal to the width of a top surface of the third gate dielectric layer.
However, Yamaguchi et al teaches
[claim 2] forming the patterned mask on the MV region and the second transistor region (figure 5, paragraphs 0066-0067, where elements 1C and 1D map onto the medium voltage region of Kim et al, and element 1A maps onto the second transistor region in the low voltage region, and element 1B maps onto the fourth transistor in the low voltage region, and element PR1 is the mask formed over the MV region and the second transistor region);
forming the first epitaxial layer on the MV region and a second epitaxial layer adjacent to the third gate structure; and forming a third epitaxial layer adjacent to the fourth gate structure (figures 5-7, paragraph 0069, where the third gate structure is element BE1, and the second epitaxial layer adjacent to the third gate structure is element 10 [the one left of element GE2], and the third epitaxial layer is eleent 10 to the right of element GE2, which is the fourth gate structure).
[claim 3] wherein the patterned mask covers the MV region and the second transistor region while exposing the first transistor region (paragraph 0184, figure 28, where the first transistor region is region 1C in the MV, and the second transistor region includes element 1D in the MV region, where element PR2 is the mask over the second transistor region but not over the first transistor region).
[claim 4] wherein the patterned mask covers the second transistor region completely (figure 5, paragraphs 0066-0067, where element PR1 is the mask and covers the entire second transistor region which comprises sections 1D of the MV region and element 1A of the LV region).
[claim 5] wherein the first epitaxial layer and the second epitaxial layer comprise same conductive type (paragraph 0081, figure 7, element 10 [left hand side] is the second epitaxial layer, and the first epitaxial layer [imported from Kim et al, paragraph 0061, figure 1, element 11P in section LV, is p-type]).
[claim 6] wherein the first epitaxial layer and the third epitaxial layer comprise different conductive type (paragraph 0081, figure 7, where element 10 [both the left hand and right-hand element 10] are of p-type and are the second and third epitaxial layers).
[claim 9] wherein a width of a bottom surface of the first gate dielectric layer is greater than a width of a top surface of the first gate dielectric layer (figure 5, element 7 has a portion [located between the gate electrodes] where the width of the bottom surface of said layer is greater than a top surface of element 7 in the same position [take note that the bottom surface by nature must extend beyond the top surface for the right angle to be produced]).
[claim 10] wherein the third gate structure comprises: a third gate dielectric layer on the substrate, wherein a sidewall of the third gate dielectric layer comprises a vertical surface; and a third gate electrode on the third gate dielectric layer (figure 5, paragraphs 0064-0065, where element 7 is the gate dielectric layer [silicon oxide is a dielectric layer], and the third dielectric layer surrounds the third gate structure [element GE1] and comprises a curve [as it goes around element GE1] and the first gate electrode [element GE3] is on the dielectric layer).
[claim 11] wherein an angle included by a top surface of the substrate and the vertical surface is equal to 90 degrees (figure 5, element 7 over element GE1 is the vertical surface of the gate dielectric layer and is a 90 degree angle with the top surface of the substrate [element 1 of figure 2]).
[claim 12] wherein a bottom surface of the third gate dielectric layer is equal to a top surface of the third gate dielectric layer (figure 5, element 7 has a portion [located on the side of the gate electrodes extending vertically where the width of the bottom surface of said layer is equal to the width of the top surface).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Kim et al as modified to include the teachings of Yamaguchi et al in order to efficiently deposit layers on each of the regions specifically so as to not waste material but utilize the material only where needed so as to maximize efficiency.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20230059628 A1), Zang et al (US 10629694 B1), and Yamaguchi et al (US 20110037103 A1).
Kim et al as modified teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 8] wherein an angle included by a top surface of the substrate and the curve is less than 90 degrees.
However, according to MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
B. Changes in Shape
In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Kim et al as modified to make the curve with respect to the top of the substrate to be less than 90 degrees instead of 90 degrees in order to fulfill a particular configuration of the gate electrode.
Claim(s) 13, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20230059628 A1) in view of Yamaguchi et al (US 20110037103 A1).
Kim et al teaches
[claim 13] A semiconductor device, comprising: a substrate comprising a medium-voltage (MV) region and a low-voltage (LV) region (figure 1, paragraph 0047, section 11 is the LV region, and element 12 is the MV region);
a first gate structure on the MV region (paragraph 0064, figure 3, element 45 is the first gate structure in the MV region [element 12]),
wherein the first gate dielectric layer is disposed between the substrate and the first gate electrode (paragraphs 0058-0059, figures 2D-2E, where element 35 is the dielectric layer situated between the substrate [element 21] and the first gate electrode [element 45]);
However, Kim et al does not specifically disclose
[claim 13] wherein the first gate structure comprises: a first gate dielectric layer on the substrate, wherein the first gate dielectric layer comprises a curve; a first gate electrode on the first gate dielectric layer; and a first epitaxial layer adjacent to the first gate structure.
[claim 15] wherein a width of a bottom surface of the first gate dielectric layer is greater than a width of a top surface of the first gate dielectric layer.
[claim 16] further comprising: a second gate structure on the LV region, wherein the second gate structure comprises: a second gate dielectric layer on the substrate, wherein a sidewall of the second gate dielectric layer comprises a vertical surface; and a second gate electrode on the second gate dielectric layer; and a second epitaxial layer adjacent to the second gate structure.
[claim 17] wherein an angle included by a top surface of the substrate and the vertical surface is equal to 90 degrees.
[claim 18] wherein a width of a bottom surface of the second gate dielectric layer is equal to a width of a top surface of the second gate dielectric layer.
However, Yamaguchi et al does teach
[claim 13] wherein the first gate structure comprises: a first gate dielectric layer on the substrate, wherein the first gate dielectric layer comprises a curve; a first gate electrode on the first gate dielectric layer; and a first epitaxial layer adjacent to the first gate structure (figure 10, paragraphs 0076-0078, where element GE1 in section 1B is the first gate electrode supplanted onto the element 45 of Kim et al in the MV region, and contains a gate dielectric layer [element 7] which curves around the gate electrode [element GE1], and a first epitaxial layer [element 10 on the right-hand side of element GE1 in section 1B] that is adjacent to the first gate structure).
[claim 15] wherein a bottom surface of the first gate dielectric layer is greater than a top surface of the first gate dielectric layer (figure 5, element 7 has a portion [located between the gate electrodes] where the width of the bottom surface of said layer is greater than a top surface of element 7 in the same position [take note that the bottom surface by nature must extend beyond the top surface for the right angle to be produced]).
[claim 16] further comprising: a second gate structure on the LV region, wherein the second gate structure comprises: a second gate dielectric layer on the substrate, wherein a sidewall of the second gate dielectric layer comprises a vertical surface (figure 10, paragraphs 0076-0078, where section 1A is located in the LV region of Kim et al and element GE1 in section 1A is in place of the gate electrode 43 in Kim et al [maintaining structural similarities between the two], and a second gate dielectric layer [element 7 in section 1A] is on the substrate and creates a sidewall that is vertical up and around the gate electrode [element GE1 in section 1A]);
and a second gate electrode on the second gate dielectric layer; and a second epitaxial layer adjacent to the second gate structure (figure 10, paragraphs 0076-0078 where element GE1 in section 1A is the second gate electrode and element 10 [lefthand side of element GE1 in section 1B] is the second epitaxial layer and adjacent to the second gate electrode).
[claim 17] wherein an angle included by a top surface of the substrate and the vertical surface is equal to 90 degrees (figure 10, paragraphs 0076-0078, where element 7 in section 1A is vertical and at a 90 degree angle to the substrate in section 1A).
[claim 18] wherein a width of a bottom surface of the second gate dielectric layer is equal to a width of a top surface of the second gate dielectric layer (figure 5, element 7 has a portion [located on the side of the gate electrodes extending vertically where the width of the bottom surface of said layer is equal to the width of the top surface).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Kim et al to incorporate the teachings of Yamaguchi et al in order to maximize efficiency by depositing dielectrics in specific regions so as to not waste material.
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20230059628 A1), and Yamaguchi et al (US 20110037103 A1).
Kim et al as modified teaches all of the limitations of the parent claim, claim 7, but does not specifically disclose
[claim 14] wherein an angle included by a top surface of the substrate and the curve is less than 90 degrees.
However, according to MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
B. Changes in Shape
In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Kim et al as modified to make the curve with respect to the top of the substrate to be less than 90 degrees instead of 90 degrees in order to fulfill a particular configuration of the gate electrode.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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