Prosecution Insights
Last updated: April 19, 2026
Application No. 18/143,083

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

Final Rejection §102§103
Filed
May 04, 2023
Examiner
ALBRECHT, PETER M
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hannstar Display Corporation
OA Round
2 (Final)
70%
Grant Probability
Favorable
3-4
OA Rounds
2y 10m
To Grant
73%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allow Rate
332 granted / 475 resolved
+1.9% vs TC avg
Minimal +3% lift
Without
With
+2.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
30 currently pending
Career history
505
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
41.5%
+1.5% vs TC avg
§102
25.6%
-14.4% vs TC avg
§112
30.0%
-10.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 475 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2009/0101903 A1 (hereinafter “Chen”). Regarding claim 15, Chen discloses in Fig. 2D and related text a thin film transistor (Abstract, line 1), comprising: a substrate (202; [0022]); a gate (208; [0022]) disposed on the substrate; a gate insulating layer (210; [0023]) disposed on the gate; a semiconductor layer (212; [0023]) disposed on the gate insulating layer; and a drain (214 (one of the two); [0024]) and a source (214 (the other of the two); [0024]), and each of the drain and the source comprises: a first conductive layer (218a; [0023]-[0024]) disposed on the semiconductor layer and the gate insulating layer, and the first conductive layer comprises copper; a covering layer (220 (portion thereof corresponding to an upper surface of 218a); [0026]) disposed on an upper surface of the first conductive layer, and the covering layer comprises copper nitride; a first sidewall protection layer (220 (portion thereof corresponding to a sidewall of 218a); [0026]) disposed on a side surface of the first conductive layer, and the first sidewall protection layer comprises copper nitride; a second conductive layer (216a; [0023]-[0024]) disposed between the first conductive layer and the semiconductor layer and between the first conductive layer and the gate insulating layer, and the second conductive layer comprises molybdenum (e.g., a copper molybdenum oxide or a copper molybdenum oxynitride as described in [0023]); and a second sidewall protection layer (220 (portion thereof corresponding to a sidewall of 216a); [0026]) disposed on a side surface of the second conductive layer, and the second sidewall protection layer comprises molybdenum nitride (“copper alloy nitride” in [0026] is copper molybdenum nitride when molybdenum is selected as the metal element to be alloyed with copper to form the barrier layer 216a as described in [0023]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of US 2007/0122649 A1 (hereinafter “Lee”). Regarding claim 18, Chen discloses the thin film transistor according to claim 15. Chen does not disclose the each of the drain and the source further comprises a third conductive layer disposed between the second conductive layer and the first conductive layer, and the third conductive layer comprises copper nitride. Lee teaches in Fig. 8C and related text the each of the drain (66; [0086]) and the source (65; [0086]) further comprises a third conductive layer (655, 665; [0043] and [0088]) disposed between the second conductive layer (651, 661; [0026] and [0084]) and the first conductive layer (652, 662; [0084]), and the third conductive layer comprises copper nitride ([0043]). Chen and Lee are analogous art because they both are directed to thin film transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen with the specified features of Lee because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the each of the drain and the source to further comprise a third conductive layer disposed between the second conductive layer and the first conductive layer, wherein the third conductive layer comprises copper nitride, as taught by Lee, in order to further prevent the copper metal in the first conductive layer from directly contacting with either the gate insulating layer or the semiconductor layer therebelow, thereby further preventing electrical degradation of the thin film transistor (Chen: [0025]). Response to Arguments Applicant’s arguments with respect to claim(s) 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M ALBRECHT whose telephone number is (571)272-7813. The examiner can normally be reached M-F 9:30 AM - 6:30 PM (CT). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PETER M ALBRECHT/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

May 04, 2023
Application Filed
Sep 03, 2025
Non-Final Rejection — §102, §103
Nov 11, 2025
Response Filed
Nov 20, 2025
Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604677
SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING
2y 5m to grant Granted Apr 14, 2026
Patent 12593506
ARRAY SUBSTRATE, PREPARATION METHOD THEREOF, AND DISPLAY PANEL
2y 5m to grant Granted Mar 31, 2026
Patent 12593505
FLEXIBLE ELECTRONIC DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12588284
THIN-FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, AND DISPLAY SUBSTRATE
2y 5m to grant Granted Mar 24, 2026
Patent 12588285
DISPLAY PANEL AND MOBILE TERMINAL
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
70%
Grant Probability
73%
With Interview (+2.8%)
2y 10m
Median Time to Grant
Moderate
PTA Risk
Based on 475 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month