Prosecution Insights
Last updated: May 29, 2026
Application No. 18/144,162

ELECTRONIC PACKAGE

Final Rejection §102
Filed
May 05, 2023
Examiner
JEAN BAPTISTE, WILNER
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Semiconductor Engineering Inc.
OA Round
2 (Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
932 granted / 1079 resolved
+18.4% vs TC avg
Moderate +5% lift
Without
With
+5.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
23 currently pending
Career history
1110
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
81.0%
+41.0% vs TC avg
§102
11.9%
-28.1% vs TC avg
§112
4.1%
-35.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1079 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 3. Claim(s) 1, is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Sakurai et al., US 2001/0040290 A1. Claim 1. Sakurai et al., disclose an electronic package (such as the one in fig. 11, [0151]), comprising: -a pad (item 12); -a dielectric layer (item 14/24) encapsulating the pad, and including an opening (item 52/22) exposing the pad; -a bump (item 46) disposed over the pad, wherein the bump includes a first layer (item 33) and a second layer (item 44) disposed on the first layer; -and a conductive element (item 30) disposed in the opening between the pad and the bump, wherein the conductive element comprises an upper portion (as seen in the structure of fig. 11) and a lower portion (as seen in the structure of fig. 11), and the upper portion of the conductive element is surrounded by the first layer of the bump (as seen in the structure of fig. 11). Allowable Subject Matter 4. Claims 21-28, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. (A) Claim 21 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the first layer of the bump includes a first portion disposed on a top surface of the conductive element and a second portion disposed on a lateral surface of the conductive element, wherein a vertical thickness of the first portion is greater than a lateral width of the second portion. (B) Claim 22 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein a lateral surface of the second layer is substantially aligned with a lateral surface of the first layer, wherein the second layer vertically overlaps the conductive element. (C) Claim 23 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein a lateral width of the second layer is greater than a lateral width of the first layer, wherein an indentation is formed near a bottom corner of the second layer. (D) Since claims 24-28, dependent of objected claim (claim 23), are also objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claim (e.g., claim 23). 5. Claims 12, 17, 29-37 allowed. Reasons for Allowance 6. The following is an examiner's statement of reasons for allowance: 7. Regarding claims 12, 29-35, the prior art failed to disclose or reasonably suggest wherein the conductive element comprises an upper portion and a lower portion, and the upper portion of the conductive element is surrounded by the bump: and a seed layer disposed between the conductive element and the bump, wherein the seed layer covers a top surface and a lateral surface of the upper portion of the conductive element, wherein the seed layer includes a first portion disposed between the dielectric layer and the bump, wherein the lower portion of the conductive element directly contacts the dielectric layer. 8. Regarding claims 17, 36-37, the prior art failed to disclose or reasonably suggest a conductive element disposed in the opening, wherein the conductive element is configured to inhibit a tilt of the bump and enhance a reliability of a connection between the bump and the conductive element, wherein the conductive element is recessed from a top surface of the dielectric layer. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

May 05, 2023
Application Filed
Aug 27, 2025
Non-Final Rejection mailed — §102
Dec 29, 2025
Response Filed
Mar 20, 2026
Final Rejection mailed — §102
May 20, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12642139
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
3y 1m to grant Granted May 26, 2026
Patent 12629782
WAFER PROCESSING METHOD
2y 4m to grant Granted May 19, 2026
Patent 12628662
SEMICONDUCTOR CHIP, CHIP SYSTEM, METHOD OF FORMING A SEMICONDUCTOR CHIP, AND METHOD OF FORMING A CHIP SYSTEM
3y 4m to grant Granted May 12, 2026
Patent 12628687
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted May 12, 2026
Patent 12628430
3D SEMICONDUCTOR DEVICE AND STRUCTURE INCLUDING POWER DISTRIBUTION GRIDS
11m to grant Granted May 12, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
92%
With Interview (+5.4%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1079 resolved cases by this examiner. Grant probability derived from career allowance rate.

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