Prosecution Insights
Last updated: July 17, 2026
Application No. 18/145,502

POWER ELECTRONICS PACKAGE LAYOUTS, STRUCTURES, AND/OR CONFIGURATIONS FOR ONE OR MORE POWER DEVICES AND PROCESSES IMPLEMENTING THE SAME

Non-Final OA §102§103
Filed
Dec 22, 2022
Examiner
KLEIN, JORDAN M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wolfspeed Inc.
OA Round
3 (Non-Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
460 granted / 538 resolved
+17.5% vs TC avg
Moderate +9% lift
Without
With
+8.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
18 currently pending
Career history
558
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
86.7%
+46.7% vs TC avg
§102
10.1%
-29.9% vs TC avg
§112
1.0%
-39.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 538 resolved cases

Office Action

§102 §103
DETAILED ACTION This Office Action is in response to the applicant's amendment entered with the RCE filed June 17th, 2026. In virtue of this communication, claims 1, 3-30, 59, and 86-88 are currently presented in the instant application. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3, 6-8, 11-13, 16-24, 26-28, 30, 59, and 86-88 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by McPherson (US 2021/0313243 A1). With respect to claim 1, McPherson teaches a power package 10 in at least Figs. 1-14D comprising: a power substrate 14 (see Figs. 4-6, Abstract, and paragraphs 71, 72); one or more power devices 16 on the power substrate 14 (see Figs. 4-7, Abstract, and paragraphs 71, 73, 75, 76); a lead frame power interconnection 44 comprising a lead frame first portion 20 and a lead frame second portion 18 (see Figs. 3-8, 11-13, and paragraphs 71, 73, 74, 76, 79, 80); and a connector (comprising 20L, 20B, 20L) configured and/or operable to reduce transconductance mismatches between paralleled implementations of the one or more power devices 16 (see Figs. 3-8, 11-13, and paragraphs 80-83, 103-105), wherein the connector (comprising 20L, 20B, 20L) is configured as a centralized connecting bar (at 20B) positioned between implementations of the one or more power devices 16 (see Figs. 3-8, 11-13, and paragraphs 80-83, 103-105; note in at least Fig. 7 that portions of 20B are between 16 and also that the middle section of 20B is between 16 of left and 16 on right in Fig. 7); and wherein the centralized connecting bar (at 20B) is vertically and horizontally offset from the one or more power devices 16 (see Figs. 3-8, 11-13, and paragraphs 80-83, 103-105; note in at least Fig. 7 that portions of 20B are between 16 and also that the middle section of 20B is between 16 on left and 16 on right in Fig. 7, i.e., horizontally offset; also note that in Figs. 6 and 7, element 20B is attached to the source contacts of the transistors Q1 by lead frame attach material, i.e., vertically offset). With respect to claim 3, McPherson teaches the power package according to claim 1 wherein the connector (comprising 20L, 20B, 20L) is configured and/or operable to provide a balancing current flow between the one or more power devices 16; and wherein the connector (comprising 20L, 20B, 20L) is connected to and centrally between the one or more power devices 16 (see Figs. 3-8, 11-13, and paragraphs 73, 81, 87, 88, 103-105). With respect to claim 6, McPherson teaches the power package according to claim 1 further comprising a molded assembly 12 comprising a dielectric mold compound (of 12) (see Figs. 3, 6, 14A-14D, and paragraphs 70, 78-80, 106, 107), wherein the lead frame first portion 20 comprises at least one strain relieving feature 62 (see Fig. 18 and paragraph 119); and wherein the dielectric mold compound (of 12) extends at least partially through the at least one strain relieving feature 62 and the dielectric mold compound (of 12) is configured and/or operable to provide electrical isolation, voltage safety distances, and/or mechanical support to an internal layout and the one or more power devices 16 (see Figs. 3, 6, 14A-14D, 18 and paragraphs 70, 78-80, 106, 107, 113, 119; by molding process 12 extends through holes or over pin bars). With respect to claim 7, McPherson teaches the power package according to claim 1 further comprising a source Kelvin terminal 26 implemented separate from the lead frame first portion 20 that comprises at least one dedicated kelvin bond to a source pad on one of the one or more power devices 16 (see Figs. 4, 5, 8, 11, and paragraphs 67, 74, 76, 77, 84, 98-100). With respect to claim 8, McPherson teaches the power package according to claim 7 further comprising signal bonds stitched between source pads of the one or more power devices 16 (see Figs. 4, 5, 8, 11, and paragraphs 67, 74, 76, 77, 83, 84, 98-100; note bond wires 32. Also see paragraph 208 of applicants published disclosure as US 2024/0213124 A1 defining signal bonds ‘stitched’ as bonded; see MPEP 2111.01 I). With respect to claim 11, McPherson teaches the power package according to claim 1 further comprising at least one signal contact and wirebonds (at 32), wherein the power substrate 14 comprises a first metal (24, 26, 28, 30) having a first contoured potion; and wherein the wirebonds (at 32) extend from the at least one signal contact to the first metal (24, 26, 28, 30) (see Figs. 3-8, 11-15 and paragraphs 74, 76, 77, 83, 110). With respect to claim 12, McPherson teaches the power package according to claim 1 wherein the power substrate 14 comprises a first metal (24, 26, 28, 30) having a first contoured portion; and wherein the first contoured portion is located on the power substrate 14 at a hold down pin location (see Figs. 3-8, 11-15 and paragraphs 74, 76, 77, 83, 107, 110; hold-down pins near contoured portions). With respect to claim 13, McPherson teaches the power package according to claim 11 wherein the first contoured portion comprises non-rectangular shape (see Figs. 3-8, 11-15, and paragraphs 76, 110; non-rectangular contoured portions). With respect to claim 16, McPherson teaches the power package according to claim 1 wherein the power substrate 14 is configured to form a mechanical and electrical connection (at 20J) with the lead frame first portion 20 by attachment to a trace on the power substrate 14 (see Figs. 4, 5, 7, 12, and paragraphs 73, 81, 87). With respect to claim 17, McPherson teaches the power package according to claim 1 wherein the lead frame second portion 18 comprises portions (18L, 18B, 18L) extending over a second metal portion of the power substrate 14 and the portions extending past one or more implementations of the one or more power devices 16 (see Figs. 4, 5, 7, 12, and paragraphs 79, 81, 82, 83). With respect to claim 18, McPherson teaches the power package according to claim 6 further comprising at least one strain relieving feature 62 on one of the lead frame first portion 20, the lead frame second portion 18, and/or a signal contact, wherein the at least one strain relieving feature 62 comprises one or more holes or slots in the lead frame first portion 20, the lead frame second portion 18, and/or the signal contact (see Figs. 4-8, 16A-16D, 18 and paragraphs 70, 78-80, 106, 107, 113, 119; note holes 30H, pin bar 30B for strain relief). With respect to claim 19, McPherson teaches the power package according to claim 18 wherein the dielectric mold compound (of 12) comprises portions that extend through the at least one strain relieving feature 62 (see Figs. 3-8, 14A-16D, 18 and paragraph 70, 78-80, 106, 107, 113, 119; by molding process 12 extends through holes or over pin bars). With respect to claim 20, McPherson teaches the power package according to claim 1 further comprising a mold assembly feature on the lead frame first portion and configured and/or operable to provide mold flow enhancement, hold down access, and/or lead strengthening, wherein the mold assembly feature comprises at least one or more holes or slots 62 in the lead frame first portion 20 (see Figs. 1-18 and paragraphs 117-119). With respect to claim 21, McPherson teaches the power package according to claim 1 wherein the lead frame first portion 20 comprises at least one opening configured and/or operable for manufacturing tooling access (see Figs. 4-8, 11-13 and paragraphs 71, 73, 74, 76, 79, 80, 116, 118-120; note holes, slots capable of tooling access). With respect to claim 22, McPherson teaches the power package according to claim 1 further comprising signal bonds implemented for each of the one or more power devices 16 stitched signal bonds extending at least to two of the one or more power devices 16 (see Figs. 1-13 and paragraphs 67, 74, 76, 83, 84, 96, 98-101; note bond wires 32. Also see paragraph 208 of applicants published disclosure as US 2024/0213124 A1 defining signal bonds ‘stitched’ as bonded; see MPEP 2111.01 I). With respect to claim 23, McPherson teaches the power package according to claim 1 further comprising power connections extending from the lead frame first portion to the one or more power devices, wherein the power connections comprise ribbon bonds and/or wire bonds (see Figs. 1-14D and paragraphs 116, 118, 121; lead frame 44 attached to power devices and wire bonded). With respect to claim 24, McPherson teaches the power package according to claim 1 further comprising a molded assembly 12 comprising a dielectric mold compound (of 12) (see Figs. 2, 6, 14A-14D, and paragraphs 70, 78-80, 106, 107), wherein the lead frame first portion 20 a first power contact 20C and the lead frame second portion 18 comprises a second power contact 18C (see Figs. 3-8, 11-13 and paragraphs 71, 73, 74, 76, 79, 80, 82, 88); wherein the molded assembly 12 comprises creepage extenders 60 on ends of the molded assembly 12 adjacent the first power contact 20C and the second power contact 18C (see Figs. 3, 6, 14A-14D, and paragraphs 70, 78-80, 106-109; note 20C and 18C at perimeter of 12 and adjacent to 60); and wherein the creepage extenders 60 extend between sides of the molded assembly 12 and comprise at least one groove, ripple, and/or trench acting as creepage distance extension (see Figs. 14A-14D and paragraphs 108, 109). With respect to claim 26, McPherson teaches the power package according to claim 1 wherein the lead frame second portion 18 is bonded to the power substrate 14 (see Figs. 1-13 and paragraphs 73, 76, 79, 116-118, 121; bonded by way of 16). With respect to claim 27, McPherson teaches the power package according to claim 1 wherein the lead frame first portion 20 is bonded to the power substrate 14 (see Figs. 1-13 and paragraphs 73, 76, 81, 116-118, 121; bonded by way of 16 and 20J). With respect to claim 28, McPherson teaches the power package according to claim 1 wherein components of the power package 10 are configured for one, two, three, or four implementations of the one or more power devices 16 within a same structure of the power package 10 (see Figs. 2, 4-8, 11-13, and paragraphs 69, 71; note plural Q1 and Q2 power device transistors). With respect to claim 30, McPherson teaches a power package 10 in at least Figs. 1-14D comprising: a power substrate 14 (see Figs. 4-6, Abstract, and paragraphs 71, 72); one or more power devices 16 on the power substrate 14 (see Figs. 4-7, Abstract, and paragraphs 71, 73, 75, 76); a lead frame power interconnection 44 comprising a lead frame first portion 20 and a lead frame second portion 18 that comprise power contacts (20C and 18C, respectively) (see Figs. 3-8, 11-13, and paragraphs 71, 73, 74, 76, 79, 80, 82, 88); and a molded assembly 12 configured to provide electrical isolation, voltage safety distances, and/or mechanical support to an internal layout and the one or more power devices 16 (see Figs. 3, 6, 14A-14D, and paragraphs 70, 78-80, 106, 107); and a connector (comprising 20L, 20B, 20L) configured and/or operable to reduce transconductance mismatches between paralleled implementations of the one or more power devices 16 (see Figs. 3-8, 11-13, and paragraphs 80-83, 103-105), wherein the connector (comprising 20L, 20B, 20L) is configured as a centralized connecting bar (at 20B) positioned centrally between implementations of the one or more power devices 16 (see Figs. 3-8, 11-13, and paragraphs 80-83, 103-105; note in at least Fig. 7 that portions of 20B are between 16 and also that the middle section of 20B is between 16 of left and 16 on right in Fig. 7); wherein the centralized connecting bar (at 20B) is vertically and horizontally offset from the one or more power devices 16 (see Figs. 3-8, 11-13, and paragraphs 80-83, 103-105; note in at least Fig. 7 that portions of 20B are between 16 and also that the middle section of 20B is between 16 on left and 16 on right in Fig. 7, i.e., horizontally offset; also note in Figs. 6 and 7, element 20B is attached to the source contacts of the transistors Q1 by lead frame attach material, i.e., vertically offset); wherein the molded assembly 12 comprises creepage extenders 60 on ends of the molded assembly adjacent the power contacts (20C and 18C) (see Figs. 3, 6, 14A-14D, and paragraphs 70, 78-80, 106-109; note 20C and 18C at perimeter of 12 and adjacent to 60); and wherein the creepage extenders 60 extend between sides of the molded assembly 12 and comprise at least one groove, ripple, and/or trench acting as creepage distance extension (see Figs. 14A-14D and paragraphs 108, 109). With respect to claim 59, McPherson teaches a power package 10 in at least Figs. 1-14D comprising: a power substrate 14 (see Figs. 4-6, Abstract, and paragraphs 71, 72); one or more power devices 16 on the power substrate 14 (see Figs. 4-7, Abstract, and paragraphs 71, 73, 75, 76); a lead frame power interconnection 44 comprising a lead frame first portion 20 and a lead frame second portion 18 (see Figs. 3-8, 11-13, and paragraphs 71, 73, 74, 76, 79, 80); a source Kelvin terminal 26 separate from the lead frame first portion 20 (see Figs. 4, 5, 8, 11, and paragraphs 67, 74, 76, 77, 84, 98-100); the source Kelvin terminal 26 comprises at least one dedicated kelvin bond to a source pad on at least one of the one or more power devices 16 and signal bonds connected between source pads of the one or more power devices 16 (see Figs. 4, 5, 8, 11, and paragraphs 67, 74, 76, 77, 83, 84, 98-100, 110); and a thermal pad 56 comprises an exposed metal surface configured to thermally and mechanically attach to another component (see Figs. 14A-14D and paragraphs 106, 107). With respect to claim 86, McPherson teaches the power package according to claim 1 further comprising: a source Kelvin terminal 26 implemented separate from the lead frame first portion 20 that comprises at least one dedicated kelvin bond to a source pad on the one or more power devices 16 and signal bonds stitched between source pads of the one or more power devices 16 (see Figs. 4, 5, 8, 11, and paragraphs 67, 74, 76, 77, 83, 84, 96, 98-101; note bond wires 32. Also see paragraph 208 of applicants published disclosure as US 2024/0213124 A1 defining signal bonds ‘stitched’ as bonded; see MPEP 2111.01 I). With respect to claim 87, McPherson teaches the power package according to claim 59 further comprising a connector (comprising 20L, 20B, 20L) configured and/or operable to reduce transconductance mismatches between paralleled implementations of the one or more power devices 16 (see Figs. 3-8, 11-13, and paragraphs 80-83, 103-105), wherein the connector (comprising 20L, 20B, 20L) is configured as a centralized connecting bar (at 20B) positioned centrally between implementations of the one or more power devices 16 (see Figs. 3-8, 11-13, and paragraphs 80-83, 103-105; note in at least Fig. 7 that portions of 20B are between 16 and also that the middle section of 20B is between 16 of left and 16 on right in Fig. 7); and wherein the centralized connecting bar (at 20B) is vertically and horizontally offset from the one or more power devices 16 (see Figs. 3-8, 11-13, and paragraphs 80-83, 103-105; note in at least Fig. 7 that portions of 20B are between 16 and also that the middle section of 20B is between 16 on left and 16 on right in Fig. 7). With respect to claim 88, McPherson teaches the power package according to claim 59 further comprising a molded assembly 12 comprising a dielectric mold compound (of 12) (see Figs. 2, 6, 14A-14D, and paragraphs 70, 78-80, 106, 107), wherein components of the power package 10 are configured for one, two, three, or four implementations of the one or more power devices 16 within a same structure of the power package 10 (see Figs. 2, 4-8, 11-13, and paragraphs 69, 71; not plural Q1 and Q2 power device transistors); wherein the lead frame first portion 20 a first power contact 20C and the lead frame second portion 18 comprises a second power contact 18C (see Figs. 3-8, 11-13 and paragraphs 71, 73, 74, 76, 79, 80, 82, 88); wherein the molded assembly 12 comprises creepage extenders 60 on ends of the molded assembly 12 adjacent the first power contact 20C and the second power contact 18C (see Figs. 3, 6, 14A-14D, and paragraphs 70, 78-80, 106-109; note 20C and 18C at perimeter of 12 and adjacent to 60); and wherein the creepage extenders 60 extend between sides of the molded assembly 12 and comprise at least one groove, ripple, and/or trench acting as creepage distance extension (see Figs. 14A-14D and paragraphs 108, 109). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4, 5, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over McPherson (US 2021/0313243 A1; hereinafter McPherson43) in view of McPherson et al. (US 2020/0395322 A1; hereinafter McPherson22). With respect to claim 4, McPherson43 discloses the power package according to claim 1 further comprising a thermal pad 56 configured as an exposed metal surface configured to thermally and mechanically attach to another component (see Figs. 14A-14D and paragraphs 106, 107), wherein the lead frame first portion 20 comprises a first power contact 20C and the lead frame second portion 18 comprises a second power contact 18C (see Figs. 3-8, 11-13, and paragraphs 71, 73, 74, 76, 79, 80, 82, 88). McPherson43 does not explicitly disclose the first power contact and/or the second power contact comprise a width that is 60%-100% of a width of the power package. McPherson22 discloses a power package in at least Figs. 2-8 wherein a first power contact 40 and/or a second power contact 42 comprise a width that is 60%-100% of a width of a power package 36 (see Figs. 2-8 and paragraphs 33, 35, 36; note width of 40 and 42 almost equal to width of 36). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that first power contact and/or the second power contact of McPherson43 would comprise a width that is 60%-100% of a width of the power package as taught by McPherson22 because it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only ordinary skill in the art (see MPEP 2144.05 I). It is noted that the specification contains no disclosure of either the critical nature of the claimed width or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical (see MPEP 2144.05 III A). With respect to claim 5, the combination of McPherson43 and McPherson22 discloses teaches the power package according to claim 4 wherein the thermal pad 56 is configured to be attached to the another component via sintering, soldering, conductive epoxy, and/or thermal paste (see McPherson43: Figs. 14A-14D and paragraphs 106, 107). With respect to claim 9, the combination of McPherson43 and McPherson22 discloses the power package according to claim 4 wherein the thermal pad 56 comprises hold down configurations arranged thereon (see McPherson43: Figs. 14A-14D and paragraph 107; note hold-down pins). Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over McPherson (US 2021/0313243 A1) in view of Olson et al. (US 2019/0326255 A1; hereinafter Olson). With respect to claim 10, McPherson discloses the power package according to claim 1. McPherson does not disclose wherein the power substrate comprises at least one a fiducial for pattern recognition systems of manufacturing equipment. Olson discloses a power package wherein a power substrate (56, 58) comprises at least one a fiducial for pattern recognition systems of manufacturing equipment (see Figs. 2A and paragraphs 43, 44). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the power substrate of McPherson would comprise at least one a fiducial for pattern recognition systems of manufacturing equipment as taught by Olson for use in properly positioning semiconductor die 24 on carrier 56 (see Olson: paragraph 43). Claims 14, 15, 25, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over McPherson (US 2021/0313243 A1) in view of Terrill et al. (US 2017/0162403 A1; hereinafter Terrill). With respect to claim 14, McPherson discloses the power package according to claim 1. McPherson does not disclose wherein the lead frame first portion is implemented as a clip attach and a power interconnection attach is arranged between the one or more power devices and the clip attach. Terrill discloses a power package wherein a lead frame first portion is implemented as a clip attach 416 and a power interconnection attach 426 is arranged between the one or more power devices and the clip attach (see Fig. 16 and paragraph 69). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the lead frame first portion of McPherson would be implemented as a clip attach and a power interconnection attach is arranged between the one or more power devices and the clip attach as taught by Terrill in order to eliminate the need to do wiring bonding and reduce cost (see Terrill: paragraphs 4, 46). With respect to claim 15, the combination of McPherson and Terrill discloses the power package according to claim 14, wherein the power interconnection attach 426 comprises welded portions, soldered portions, sintered portions, and/or preformed portions (see Terrill: Fig. 16 and paragraph 69). With respect to claim 25, McPherson discloses the power package according to claim 1. McPherson does not disclose wherein the lead frame first portion is configured as a clip, and wherein the clip is configured as a formed metal contact connecting a topside of all implementations of the one or more power devices to the lead frame first portion. Terrill discloses a power package wherein the lead frame first portion is configured as a clip 420a, and wherein the clip is configured as a formed metal contact connecting a topside of all implementations of the one or more power devices 418 to the lead frame first portion 402 (see Fig. 4 and paragraph 36-38). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the lead frame first portion of McPherson would be configured as a clip, and wherein the clip is configured as a formed metal contact connecting a topside of all implementations of the one or more power devices to the lead frame first portion as taught by Terrill in order to eliminate the need to do wiring bonding and reduce cost (see Terrill: paragraphs 4, 46). With respect to claim 29, McPherson discloses the power package according to claim 1. McPherson does not disclose a modular clip attached to the lead frame first portion and also attached to the one or more power devices. Terrill discloses a power package further comprising a modular clip attached to the lead frame first portion and also attached to the one or more power devices (see Figs. 8-11 and paragraphs 50, 57, 59; note various clips 420a, 420b, 616a, 616b, 620, 902; 902 can include any of sets of clips 420a and 420b or clips 616a and 616b). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the power package of McPherson to further comprise modular clip attached to the lead frame first portion and also attached to the one or more power devices as taught by Terrill to allow for various die connection configurations (see MPEP 2144 I. Also Terrill: paragraphs 50, 59). Response to Arguments Applicant's arguments filed May 14th, 2026 have been fully considered but they are not persuasive. With respect to claim 1, the applicant argues that “MCPHERSON43 contains no disclosure of a connector that: is positioned between device implementations, is spatially offset from those devices, and is configured specifically to manage transconductance induced balancing currents independently of the main source terminal. Accordingly, MCPHERSON43 fails to disclose at least the limitations of: ‘the centralized connecting bar being vertically and horizontally offset from the one or more power devices.’” The examiner respectfully disagrees. McPherson43 teaches that the connector (comprising 20L, 20B, 20L) is configured as a centralized connecting bar (at 20B) positioned between implementations of the one or more power devices 16. Additionally, McPherson43 teaches that the centralized connecting bar (at 20B) is vertically and horizontally offset from the one or more power devices 16 (see Figs. 3-8, 11-13, and paragraphs 80-83, 103-105). As shown in Fig. 7 of McPherson, portions of 20B are between 16 and also that the middle section of 20B is between 16 on the left and 16 on the right, i.e., horizontally offset. As shown in Figs. 6 and 7, element 20B is attached to the source contacts of the transistors Q1 by lead frame attach material, i.e., vertically offset. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the centralized connector bar not having a primary source current function) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). With respect to claim 30, the applicant argues that McPherson43 does not disclose the offset centralized connecting bar as recited in claim 1. The examiner respectfully disagrees and arguments in response are the same as those provided in response to claim 1 above. Additionally, with respect to claim 30, the applicant argues that “McPherson43 does not disclose creepage extenders that are: End located adjacent power contacts, and Continuous between opposing sides of the molded assembly.” The examiner respectfully disagrees. McPherson43 teaches that the molded assembly 12 comprises creepage extenders 60 on ends of the molded assembly adjacent the power contacts (20C and 18C) (see Figs. 3, 6, 14A-14D, and paragraphs 70, 78-80, 106-109). As shown in Figs. 14A-14D, elements 20C and 18C are at the perimeter of 12 and thus adjacent to 60. McPherson43 also teaches that the creepage extenders 60 extend between sides of the molded assembly 12 and comprise at least one groove, ripple, and/or trench acting as creepage distance extension (see Figs. 14A-14D and paragraphs 108, 109). Paragraph 78 of McPherson states that “the housing 12 may be formed using a transfer or an injection molding process to provide mechanical structure, high voltage isolation.” Paragraph 106 of McPherson states that “Turning now to FIGS. 14A-14D, the package is encased by a protective plastic or epoxy housing 12 through transfer molding, compression molding, injection molding, or similar process.” Thus, McPherson43 discloses all elements of the claim as recited in a single reference. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the creepage extenders are continuous between opposing sides of the molded assembly) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). With respect to claim 59, the applicant argues that “Claim 59 affirmatively requires a true source Kelvin terminal that is: structurally separate from the lead frame first portion, and implemented via dedicated Kelvin bonds combined with stitched signal bonds interconnecting source pads of multiple devices, as part of the Kelvin signal loop.” The applicant also argues that “MCPHERSON43 does not disclose: a Kelvin terminal that is separate from the lead frame first portion, nor a Kelvin signal topology that includes signal bonds connected between source pads of multiple devices to define a composite Kelvin reference independent of the power path.” The examiner respectfully disagrees. McPherson teaches a source Kelvin terminal 26 separate from the lead frame first portion 20 (see Figs. 4, 5, 8, 11, and paragraphs 67, 74, 76, 77, 84, 98-100); and the source Kelvin terminal 26 comprises at least one dedicated kelvin bond to a source pad on at least one of the one or more power devices 16 and signal bonds connected between source pads of the one or more power devices 16 (see Figs. 4, 5, 8, 11, and paragraphs 67, 74, 76, 77, 83, 84, 98-100, 110). In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., a true source kelvin terminal that is structurally separate from the lead frame first portion, stitched signal bonds, and a Kelvin signal loop) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Independent claims 1, 30, and 59 and the claims that depend therefrom remain rejected. Inquiry Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.M.K/Examiner, Art Unit 2893 /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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Prosecution Timeline

Dec 22, 2022
Application Filed
Jun 11, 2025
Non-Final Rejection mailed — §102, §103
Nov 11, 2025
Response Filed
Feb 18, 2026
Final Rejection mailed — §102, §103
May 14, 2026
Response after Non-Final Action
Jun 17, 2026
Request for Continued Examination
Jun 23, 2026
Response after Non-Final Action
Jul 02, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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LIGHT EMITTING MODULE FOR A LIGHT EMITTING DISPLAY
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SEMICONDUCTOR DEVICE PACKAGE FOR PRESS FIT ASSEMBLY
3y 2m to grant Granted Jun 16, 2026
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CONNECTOR VIA STRUCTURES FOR NANOSTRUCTURES AND METHODS OF FORMING THE SAME
3y 1m to grant Granted Jun 09, 2026
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3y 4m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
94%
With Interview (+8.7%)
2y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 538 resolved cases by this examiner. Grant probability derived from career allowance rate.

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