DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/06/2026 has been entered.
Response to Amendment
The amendment with respect to claim(s) 11 filed on 03/06/2026 have been fully considered for examination based on their merits. The previously presented claims 12-15 have been considered. Claims 1-10, and 16-17 are canceled.
Response to Arguments
Applicant's arguments (see Remarks, pages 5-9) filed 03/06/2026 have been fully considered but they are not persuasive. LI as modified by MOON disclose or suggest all the limitations of Claim 11. More specifically, MOON teaches the amended features of Claim 11 as detailed in the paragraph below.
Regarding Independent Claim 11. Applicant argues (see Remarks, page 6) that MOON fails to disclose or suggest the amended feature, “the protruding portion of the substrate is spaced from the gate.” Examiner respectfully disagrees for the fact that MOON teaches all the elements and their structural relations of the instant applications, such as (i) the first and second portions of the source region (mapped as 120 in this office action), (ii) the first and second portions of the first isolation layers (mapped as 170 in this OA), (iii) the protruding portions as annotated in Figure 1, (iv) the protruding portion as extended from the substrate 110 and is annotated in Figure 14 inset of the Figure 1, (v) the location of first/second portions of the isolation layers in between the protruding portions and the first/second portions of the source, (vi) the locations protruding portion is spaced from the gate by gate insulating layer, and (vii) the top surface of the first isolation layer is co-planar with a top surface of the source. MOON further teaches the amended features such as etching of an isolation layer and source region to form a trench, exposing the body portion of the substrate, forming a second isolation layer in the trench and forming a gate on the second isolation layer and in the trench. Based on the evidence as annotated in Figure 1 of MOON, the Examiner maintains the rejection of the record in regard to the independent Claim 11.
Regarding Claim(s) 12-15. The independent Claim(s) 12-15 follow similar arguments as Claim 11, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Juntao Li et al, (hereinafter LI), US 20190386135 A1, in view of Jung-Min Moon et al, (hereinafter MOON), US 20130234240 A1.
Regarding Claim 11, LI teaches in Figure 7, a manufacturing method of a semiconductor structure (100, method for forming a semiconductor structure, [0003]), comprising:
etching a substrate (102, [0036]) such that the substrate (102) has a body portion (annotated Figure 3) and a protruding portion (annotated Figure 3) extending from the body portion;
forming a first isolation layer on the substrate (Fig. 4, 402/404/406);
forming a source on the first isolation layer (Fig. 7, 702, drain); and
etching ([0036]) the first isolation layer (Fig. 4, 402/404/406) and the source such that a top surface of the protruding portion is exposed (Fig. 5, 502), wherein the source (Fig. 7, 702, drain) has a first portion (annotated Figure 7) and a second portion (annotated Figure 7) opposite to the first portion, and the protruding portion of the substrate is located between the first portion and the second portion of the source (annotated Figure 7),
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LI does not explicitly disclose a manufacturing method of a semiconductor structure, comprising: etching through the first isolation layer and the source to form a trench exposing the body portion of the substrate; forming a second isolation layer in the trench and forming a gate on the second isolation layer and in the trench.
MOON teaches a manufacturing method a semiconductor of a semiconductor structure (Figs. 1, 12, 15, 18, 21, 24, 27 and 30, a method of manufacturing a semiconductor device having a junctionless vertical gate transistor, [0091-0092]), comprising:
etching through the first isolation layer (compare Figures 15 and 17, 125) and the source (compare Figures 18 and 20, 120) to form a trench (Figs. 14/25, T1/T2) exposing the body portion of the substrate (Figs. 14/25, 110);
forming a second isolation layer (Figs. 29/31, 140/170, second/third isolation layers) in the trench (Figs. 14/25, T1/T2) and forming a gate (Fig. 31, 160, gate electrodes) on the second isolation layer (Figs. 29/31, 140/170, second/third isolation layers) and in the trench (Figs. 14/25, T1/T2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention (AIA ) to have modified LI to incorporate the teaching of MOON such that a manufacturing method of a semiconductor structure, comprising: etching through the first isolation layer and the source to form a trench exposing the body portion of the substrate; forming a second isolation layer in the trench and forming a gate on the second isolation layer and in the trench, so that the arrangements of the junctionless vertical gate transistor for a semiconductor device such as DRAM and the like, it is advantageous to have a high on/off ratio in order to secure sufficient read/write operation (MOON, [0054]).
LI further does not explicitly disclose a manufacturing method of a semiconductor structure, comprising: the first isolation layer has a first portion and a second portion, the first portion of the first isolation layer is disposed between the protruding portion and the first portion of the source, the second portion of the first isolation layer is disposed between the protruding portion and the second portion of the source, and a top surface of the first isolation layer is coplanar with a top surface of the source.
MOON further teaches a manufacturing method a semiconductor of a semiconductor structure (Figs. 1, 12, 15, 18, 21, 24, 27 and 30, a method of manufacturing a semiconductor device having a junctionless vertical gate transistor, [0091-0092]), comprising:
the first isolation layer (annotated Figure 1) has a first portion (annotated Figure 1) and a second portion (annotated Figure 1), the first portion of the first isolation layer (annotated Figure 1) is disposed between the protruding portion (annotated Figure 1) and the first portion of the source (annotated Figure 1), the second portion of the first isolation layer (annotated Figure 1) is disposed between the protruding portion (annotated Figure 1) and the second portion of the source (annotated Figure 1), and a top surface of the first isolation layer (annotated Figure 1) is coplanar (annotated Figure 1) with a top surface of the source (annotated Figure 1) source (annotated Figure 1), the protruding portion (annotated Figure 1) of the substrate (Fig. 1, and therein the inset Fig. 14, 110) is spaced (Fig. 1, spaced by a gate insulating layer, 150) from the gate (annotated Figure 1, 160).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention (AIA ) to have modified LI to incorporate the teaching of MOON such that a manufacturing method of a semiconductor structure, comprising: the first isolation layer has a first portion and a second portion, the first portion of the first isolation layer is disposed between the protruding portion and the first portion of the source, the second portion of the first isolation layer is disposed between the protruding portion and the second portion of the source, and a top surface of the first isolation layer is coplanar with a top surface of the source, the protruding portion of the substrate is spaced from the gate. The manufacturing of aforementioned design leads to junctionless vertical gate transistor and thus does not suffer from a floating body effect, which causes an increase in voltage of the body due to holes generated during operation of the device, despite the absence of body contact (MOON, [0016]).
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Regarding Claim 12, LI as modified by MOON and BURNS teaches the method of claim 11.
LI further teaches the method in Figure 7, the method (100, method for forming a semiconductor structure, [0003]), wherein etching ([0036]) the first isolation layer (402/404/406) and the source (702, drain) is performed such that the first portion and the second portion of the source are symmetrically disposed along the protruding portion of the substrate (annotated Figure 7).
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Regarding Claim 13, LI as modified by MOON and BURNS teaches the method of claim 11.
LI further teaches the method in Figure 7, the method (100, method for forming a semiconductor structure, [0003]), wherein etching ([0036]) the first isolation layer (402/404/406) and the source (702, drain) is performed such that the top surface of the protruding portion of the substrate is coplanar with the top surface of the source (annotated Figure 7).
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Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over LI in view of MOON, and further in view of Nir Tessler et al, (hereinafter TESSLER), US 20120097949 A1.
Regarding Claim 14, LI as modified by MOON teaches the method of claim 13.
LI further teaches the method in Figure 7, the method (100, method for forming a semiconductor structure, [0003]), further comprising: forming a channel (104/106/108, fin channels) to cover the top surface of the protruding portion of the substrate (annotated Figure 7).
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LI as modified by MOON does not explicitly disclose the method, further comprising: forming a channel to cover the top surface of the protruding portion of the substrate and the top surface of the source.
TESSLER teaches in Figure 2A, the method (method for use in manufacturing a VOFET, [0035]), further comprising: forming a channel (106, active cell, [0067]) to cover the top surface of the protruding portion of the substrate and the top surface of the source (102, source layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention (AIA ) to have LI as modified by MOON to incorporate the teaching of TESSLER such that the method, further comprising: forming a channel to cover the top surface of the protruding portion of the substrate and the top surface of the source, so that when positive (or negative) charge is accumulated on the layers thus creating a channel in the active layer between the source and the drain electrodes (TESSLER, [0013]).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over LI in view of MOON, further in view of TESSLER, and further in view of Tao Li et al, (hereinafter LIT), US 20210288164 A1.
Regarding Claim 15, LI as modified by MOON, and TESSLER teaches the method of claim 14.
LI further teaches the method in Figure 7, the method (100, method for forming a semiconductor structure, [0003]), further comprising:
forming a drain (1402/1404/1406, drain layers) on the channel (104/106/108, fin channels).
TESSLER further teaches in Figure 2A, the method (method for use in manufacturing a VOFET structure, [0035]), further comprising: forming a drain (112, drain electrode) on the channel (106, active cell, [0067]).
LI as modified by MOON, and TESSLER does not explicitly disclose the method of claim 14, further comprising: forming a drain on the channel such that a thickness of the drain is substantially similar to a thickness of the channel.
LIT teaches in Figure 10B, the method (100, method of fabricating VTFET, [0043]) of claim 14, further comprising: forming a drain (1010 and 1014, drain layer and drain contact) on the channel (102, fins, [0072]) such that a thickness of the drain is substantially similar to a thickness of the channel (annotated Figure 10B).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention (AIA ) to have LI as modified by MOON, and TESSLER to incorporate the teaching of LIT such that the method, further comprising: forming a drain on the channel such that a thickness of the drain is substantially similar to a thickness of the channel, so that based on the type of vertical transistor device, the top source/drain layers (1010) are formed via epitaxial material grown from the fins or channel layer (102) thereby the current runs vertically from source to drain (LIT, [0003], [0072]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 9735255 B2 – Figure 24a
STATEMENT OF RELEVANCE – Cross-sectional views of p-channel finFET devices with the arrangements of isolation structures and gate structure within a trench.
US 6077745 A – Figure 26
STATEMENT OF RELEVANCE – The gate stack is formed on the exposed pillars, above the isolation oxide, 250.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (572)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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