Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is a non-final office action in response to the communication filed 7/14/2025.
Claims 1-17 and 21-23 are currently pending.
Claims 1-17 and 21-23 have been amended.
Claims 18-20 were been previously canceled.
Claims 1-17 and 21-23 have been examined.
Claim 21 has the incorrect claim label of (Previously Presented) where it is (Currently Amended)
Response to Arguments
The rejection in view of §112(b) to claims 15-17 are withdrawn in light of the amendments to claims 15-17.
Applicant’s arguments with respect to claim 9 and 12 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claims 9-12 and 14-17 remain rejected. Claim 13 has allowable subject matter identified. See below for further details.
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claims 1-8 remain rejected. See below for further details.
Applicant’s arguments with respect to claim 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claims 22-23 remain rejected. See below for further details.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 9, 12, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 20160372467 A1 (hereinafter Kim1) in view Guler et al. US 20240113233 A1 (hereinafter Guler).
The following annotated Fig. 4 will be used in discussion:
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Regarding claim 1, Kim1 discloses:
A semiconductor device, (Fig. 4, [0053], semiconductor device) comprising:
an isolation structure (Fig. 2, insulating film 102) in the substrate and …;
a first fin (first active fin F1) …
a gate structure (gate structure 192) extending across the at least one first semiconductor channel and the one or more at least one second semiconductor channel along a second direction different from than the first direction from in the top view, (Fig. 4, the gate structure 192 extends along the Y-direction over the first active fin F1 and the second active fin F2)
wherein from in the top view (Fig. 4), the gate structure comprises:
a first profile (annotated Fig. 4, profile 1) …
and a second profile over the isolation structure. (annotated Fig. 4, profile 2)
Kim1 does not appear to disclose that the isolation structure in the substrate “a dielectric wall on a substrate and extending along a first direction in a top view, the dielectric wall comprising a first sidewall and a second sidewall facing away from the first sidewall,”.
Furthermore, Kim1 discloses a fin structure F1 and can be used with semiconductor devices with three-dimensional semiconductor element. However, Kim1, does not appear to specifically disclose that the first structure F1 has as a part of that structure “a first fin comprising at least one first semiconductor channel extending from the first sidewall along a second direction different than the first direction,” and “a second fin comprising at least one second semiconductor channel extending from the second sidewall along the second direction,”
Guler, which teaches a forkFET transistor structure with a dielectric wall adjacent to stacks of nanoribbons (Guler, Abstract), discloses:
a dielectric wall (Fig. 1A, wall 120) on a substrate (substrate 160) and extending along a first direction from in a top view; (Fig. 1D, shows that 120 extends in a thickness direction for the device.)
a first fin (first stack of nanoribbions 112) comprising at least one first semiconductor channel on a first side of the dielectric wall extending from the first sidewall along a second direction different than the first direction; (Fig. 1A, [0021], the nanoribbions being made of silicon or silicon germanium acting as channels and physically coupled to the wall 120)
a second fin (second stack of nanoribbions 114) comprising at least one second semiconductor channel on a second side of the dielectric wall opposite the first side of the dielectric wall extending from the second sidewall along the second direction; and (Fig. 1A, [0021], the nanoribbions being made of silicon or silicon germanium acting as channels and physically coupled to the wall 120)
an isolation structure (Fig. 1A, first dielectric 151) in the substrate (is deposited within groves in the substrate 160) and having a top surface lower than a top surface of the dielectric wall; (Fig. 1A, the top surface of the 151 is lower than the top surface of the wall 120)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim1 to have a dielectric wall on a substrate and extending along a first direction in a top view, the dielectric wall comprising a first sidewall and a second sidewall facing away from the first sidewall, a first fin comprising at least one first semiconductor channel extending from the first sidewall along a second direction different than the first direction, a second fin comprising at least one second semiconductor channel extending from the second sidewall along the second direction, and a top surface of the isolation structure lower than a top surface of the dielectric wall as taught by Guler for purposes of having a forkFET transistor structure (Guler, [0024]) which allows for more transistors in a smaller foot print (Guler, [0010]) and where the dielectric wall material be thinner than the material used for field isolation. (Guler, [0024]. See also Guler [0023] and [0026], the material for the wall 120 may be HfO, AlN, or other dielectric material and the first dielectric may be SiO or SiN.)
The combination of Kim and Guler according to the known method would yield predictable results such that:
wherein in the top view,(Kim, Fig. 4) the gate structure (gate structure 192) comprises:
a first profile (Kim1, annotated Fig. 4, profile 1) overlying the at least one first semiconductor channel, the at least one second semiconductor channel, and the dielectric wall, (The combination of Kim1 with Guler would have profile overlaying first stack of nanoribbions 112, second stack of nanoribbions 114, and wall 120) the first profile having a fourth width (Kim1, Fig. 4, second width W2) overlying the dielectric wall and offset from the first sidewall and the second sidewall along the second direction; and (Kim1, the second width W2 is in the middle of active fin F1. Therefore the over the structures of Guler including wall 120.)
a second profile over the isolation structure, (Kim1, annotated Fig. 4, profile 2) the second profile having a third width overlying the isolation structure,(Kim1, width W1) the fourth width (second width W2) exceeding the third width. (Fig. 4, [0066], W2 is greater than W1)
One of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately. The result of the combination would have yielded a predictable combination to one of ordinary skill in the art. (MPEP 2143.I.A.)
Regarding claim 2, Kim1 as modified by Guler disclose all the elements of claim 1.
The following figure will be used in discussion:
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The combination of Kim1 and Guler further discloses:
in the top view, the first profile (Kim1, annotated Fig. 4, profile 1) has a first width at a first position overlying the at least one first semiconductor channel (See below for close up of annotated Fig. 4, width W2_1 which is offset from W2 and would cover where the first stack of nanoribbions 112.) and a second width at a second position overlying the at least one first semiconductor channel, (See below for close up of annotated Fig. 4, width W2_2 which is offset from W2 and would cover where the first stack of nanoribbions 112 near side of the fin structure Fin 1.) the first position is nearer the first sidewall (W2_1 would be nearer to the sidewall of wall 120 of Guler in the combination of Kim and Guler) than the second position is, and the second width is less than the first width. (See annotated Fig. 4.)
Regarding claim 3, Kim1 as modified by Guler disclose all the elements of claim 2.
The combination of Kim1 and Guler further discloses:
wherein the second width (width W2_2) is substantially equal to the third width.(Kim1, width W1) ([0104] The difference from W2 to W1 is a continuous change. The term substantially equal is taken to mean anything with a maximum difference of 20% of the given value as defined by the specification at [0018]. According to Kim1 the width of W2 may be 16nm and W1 maybe 14nm therefore a value for W2_2 which is between those two would be considered to be less than W2 and within 20% difference of W1 therefore being substantially equal to W1.)
Regarding claim 4, Kim1 as modified by Guler disclose all the elements of claim 1.
Kim1 further discloses:
in the top view, the first profile narrows continuously with increased distance from the dielectric wall along the second direction. (See Fig. 4)
Regarding claim 5, Kim1 as modified by Guler disclose all the elements of claim 1.
The following annotated Figure will be used:
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The combination of Kim1 and Guler further discloses:
in the top view the first profile (annotated Fig. 4, profile 1) has a fifth width (width W2_3) overlying the at least one first semiconductor channel, the fifth width substantially equal to the third width (W1). ([0104] The difference from W2 to W1 is a continuous change. The term substantially equal is taken to mean anything with a maximum difference of 20% of the given value as defined by the specification at [0018]. According to Kim1 the width of W2 may be 16nm and W1 maybe 14nm therefore a value for W2_3 which is between those two would be considered to within 20% difference of W2 therefore being substantially equal to W2.)
Regarding Claim 9, Kim1 discloses:
The following annotated drawing will be used in discussion from Kim1:
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The following annotated drawing will be used in discussion from Guler Fig 1A:
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A semiconductor device, (Fig. 4, [0053], semiconductor device) comprising:
…
a gate structure (Fig. 4, gate structure 192) over the semiconductor channel, (the gate structure 192 is extended over the active fin F1) wherein in a top views the gate structure has a first width (width W2_1) … and a second width (width W2_2) …, and the first width of the gate structure is greater than the second width of the gate structure. (See Fig. 4)
Kim1 does not appear to teach:
a dielectric wall on a substrate;
a first source/drain epitaxial structure;
a second source/drain epitaxial structure;
a semiconductor channel laterally extending from a side surface of the dielectric wall, the semiconductor channel having a first sidewall interfacing the dielectric wall, a second sidewall facing away from the dielectric wall, a third sidewall interfacing the first source/drain epitaxial structure, and a fourth sidewall interfacing the second source/drain epitaxial structure; and
Guler, which teaches a forkFET transistor structure with a dielectric wall adjacent to stacks of nanoribbons (Guler, Abstract), discloses:
a dielectric wall (Fig. 1A, wall 120) on a substrate; (substrate 160)
a first source/drain epitaxial structure; (Fig. 1C, first epitaxial layer 111a)
a second source/drain epitaxial structure; (Fig. 1C, second epitaxial layer 111b)
a semiconductor channel (first stack of nanoribbions 112) laterally extending from a side surface of the dielectric wall, (See Fig. 1A) the semiconductor channel (first stack of nanoribbions 112) having a first sidewall (S1) interfacing the dielectric wall and a second sidewall (S2) facing away from the dielectric wall, a third sidewall (S3) interfacing the first source/drain epitaxial structure (Fig. 1C, first epitaxial layer 111a), and a fourth sidewall (S4) interfacing the second source/drain epitaxial structure; and (Fig. 1C, second epitaxial layer 111b)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim1 to have a dielectric wall on a substrate, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a semiconductor channel laterally extending from a side surface of the dielectric wall, the semiconductor channel having a first sidewall interfacing the dielectric wall, a second sidewall facing away from the dielectric wall, a third sidewall interfacing the first source/drain epitaxial structure, and a fourth sidewall interfacing the second source/drain epitaxial structure as taught by Guler for purposes of having a forkFET transistor structure (Guler, [0024]) which allows for more transistors in a smaller foot print (Guler, [0010]).
The combination of Kim and Guler according to the known method would yield predictable results such that:
a gate structure over the semiconductor channel, wherein in a top view, the gate structure has a first width overlying the first sidewall of the semiconductor channel (The combination of Kim1 with Guler would have the gate structure of Kim1 overlaying the first sidewall S1 of the first stack of nanoribbons 112 which would have the first width of W2_1.) and a second width overlying a position between the first sidewall and the second sidewall of the semiconductor channel, (The combination of Kim1 with Guler would have the gate structure of Kim1 overlaying the first sidewall S1 of the first stack of nanoribbons 112 which would have the first width of W2_2.)
One of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately. The result of the combination would have yielded a predictable combination to one of ordinary skill in the art. (MPEP 2143.I.A.)
Regarding claim 12, Kim1 and Guler disclose all the elements of claim 9 above.
The combination of Kim1 further disclose:
wherein in the top view, the gate structure (Kim1, Fig. 4, gate structure 192) has a curved sidewall profile between the first side of the semiconductor channel and the second side of the semiconductor channel. (Fig. 4, sidewall profile of the is curved and continuous. See also [0103].)
Regarding claim 21, Kim1 discloses:
The following annotated Figure of Kim1 will be used in discussion:
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The following annotated drawing of Guler will be used in discussion:
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A semiconductor device, (Fig. 4, [0053], semiconductor device) comprising:
…;
a gate structure (Fig. 4, gate structure 192) extending along a first direction (y-direction)
Kim1 teaches that the embodiments herein can be used with three-dimensional semiconductor elements including transistors using nano elements such as nanowires but doesn’t specifically disclose:
“a first stack comprising a first semiconductor channel, and a second semiconductor channel overlying the first semiconductor channel, the first stack having a first sidewall and a second sidewall facing away from the first sidewall;
a second stack comprising a third semiconductor channel, and a fourth semiconductor channel overlying the third semiconductor channel, the second stack having a third sidewall and a fourth sidewall facing away from the first sidewall;
a dielectric wall extending from the first sidewall of the first stack to the third sidewall of the second stack; and”
Guler, which teaches a forkFET transistor structure with a dielectric wall adjacent to stacks of nanoribbons (Guler, Abstract), discloses:
a first stack (Fig. 1A, stack of nanoribbons 112) comprising a first semiconductor channel, and a second semiconductor channel overlying the first semiconductor channel, (first stack of nanoribbions 112 having a first channel and a second channel overlaying the first semiconductor) the first stack having a first sidewall (S1) and a second sidewall (S2) facing away from the first sidewall; ([0021] and Fig. 1B the stack of nanoribbons 112 including individual nanoribbons 102 that are stacks such that a second nanoribbon channel overlays a first.)
a second stack (nanoribbons 114) comprising a third semiconductor channel, and a fourth semiconductor channel overlying the third semiconductor channel, (second stack of nanoribbions 114 having a third channel and a fourth channel overlaying the third semiconductor) the second stack having a third sidewall (S3) and a fourth sidewall (S4) facing away from the first sidewall;(S1)
a dielectric wall (Guler, wall 120) extending from the first sidewall (S1) of the first stack to the third sidewall (S3) of the second stack; and
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim to have a first stack comprising a first semiconductor channel, and a second semiconductor channel overlying the first semiconductor channel, the first stack having a first sidewall and a second sidewall facing away from the first sidewall, a second stack comprising a third semiconductor channel, and a fourth semiconductor channel overlying the third semiconductor channel, the second stack having a third sidewall and a fourth sidewall facing away from the first sidewall, and a dielectric wall extending from the first sidewall of the first stack to the third sidewall of the second stack as taught by Guler for purposes of including more transistors in a smaller footprint. (Guler, [0010].)
The combination of Kim and Guler according to the known method would yield predictable results such that:
a gate structure (Kim1, Fig. 4, gate structure 192) extending along a first direction (y-direction) across and over the first stack, the second stack and the dielectric wall, (The combination of Kim1with Guler would have profile overlaying first stack of nanoribbions 112, second stack of nanoribbions 114, and wall 120)the gate structure (gate structure 192) comprising:
a first portion (annotated Figure 4 and annotated Guler showing a first portion) overlying a sidewall of the dielectric wall (Kim1, the second width W2 is in the middle of active fin F1. Therefore the over the structures of Guler including wall 120.), and having a first width (width W2) along a second direction (x-direction) different than the first direction (y-direction); and
a second portion (annotated Fig. 4 of Kim and annotated Fig. 1A of Guler showing a second portion) overlying the first stack, the second portion being offset from the first sidewall (S1) and the second sidewall (S2) and having a second width along (width W2_2) the second direction (x-direction), the first width exceeding the second width. (W2 is greater than W2_2.)
One of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately. The result of the combination would have yielded a predictable combination to one of ordinary skill in the art. (MPEP 2143.I.A.)
Regarding claim 22, Kim1 as modified by Guler disclose all the elements of claim 9.
Guler further discloses:
a first source/drain region adjacent the first semiconductor channel and the second semiconductor channel; (Fig. 1B, epitaxial layer 110 within a source 106 and epitaxial layer 111 within a drain 108. See also [0027] the epitaxial layer 111a is connected to the nanoribbons in stack 112 and a similar connection is made for the drain region.)
a second source/drain region adjacent the third semiconductor channel and the fourth semiconductor channel; and (Fig. 1B, epitaxial layer 110 within a source 106 and epitaxial layer 111 within a drain 108. See also [0027] the epitaxial layer 111b is connected to the nanoribbons in stack 114 and a similar connection is made for the drain region)
a source/drain contact extending across the dielectric wall, the first source/drain region, and the second source/drain region, the source/drain contact having a recessed width along the second direction overlying dielectric wall. (Fig. 1E, the first and second epitaxial layers 111a and 111b extend over the wall 120 which includes a wall material 124 that has portions that include a recessed width.)
Regarding claim 23, Kim1 as modified by Guler disclose all the elements of claim 21.
Kim1 further discloses:
a third portion overlying the third sidewall, (See Kim annotated Fig. 4, third portion with S4 and see Guler annotated Fig. 1A, third portion with S3) the second sidewall being opposite the sidewall, (See annotated Fig. 1A, S2 is option of S3) the third portion having a third width (width W2_3) along the second direction (x-direction), the third width exceeding the second width. (W2_3 is greater than W2_2.)
Claims 6-7 are rejected under 35 U.S.C. 103 as obvious over Kim1 and Guler.
Regarding claim 6, Kim1 and Guler disclose all the element of claim 1.
Kim1, Fig. 4 shows sidewall profile as the width at the midpoint of fin F1 is a discrete value separate from the width of the midpoint of the first active layer I. (Kim1, [103-106]) Kim Fig. 4, does not appear to show the first profile has uniform width between the isolation structure adjacent the first fin and a second isolation structure adjacent the second fin.
Kim1, Fig. 1 which teaches the device with a different gate profile, further discloses:
the first profile has uniform width between the isolation structure adjacent the first fin and a second isolation structure adjacent the second fin. (Kim1, Fig. 1 shows a rectangular stepped profile for the sidewall profile which is uniform in width.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim1 Fig.4 to have the first profile has uniform width between the isolation structure adjacent the first fin and a second isolation structure adjacent the second fin as taught by Kim1, Fig. 1 for purposes of ease of manufacturing with rectangular regions these regions having the uniform with between the width of the first section defined by W2 in the active region and the second section defined by W1 in the isolation area. (Kim1, [0050] and Fig. 1.) Combining two embodiments disclosed adjacent to each other in a prior art patent does not require a leap of inventiveness, Boston Scientific v. Cordis (Fed. Cir. 2009).
Regarding claim 7, Kim1 and Guler disclose all the element of claim 1.
Kim1, Fig. 4 shows sidewall profile as the width at the midpoint of fin F1 is a discrete value separate from the width of the midpoint of the first active layer I. (Kim1, [103-106]) Kim Fig. 4, does not appear to show a portion of the first profile overlying the dielectric wall has uniform width.
Kim1, Fig. 1 which teaches the device with a different gate profile, further discloses:
a portion of the first profile overlying the dielectric wall has uniform width. (Kim1, Fig. 1 shows a rectangular stepped profile for the sidewall profile which is uniform in width.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim1 Fig.4 to have a portion of the first profile overlying the dielectric wall has uniform width as taught by Kim1, Fig. 1 for purposes of ease of manufacturing with rectangular regions these regions having the uniform with between the width of the first section defined by W2 in the active region and the second section defined by W1 in the isolation area. (Kim1, [0050] and Fig. 1.) Combining two embodiments disclosed adjacent to each other in a prior art patent does not require a leap of inventiveness, Boston Scientific v. Cordis (Fed. Cir. 2009).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim1 and Guler, as applied to claim 1 above, and further in view of Chanemougame US 20200035567 A1 (hereinafter Chanemougame).
Regarding claim 8, Kim1 as modified by Guler disclose all the elements of claim 1.
Kim1 further discloses:
the gate structure comprises a first portion having a first metal composition([0082]- [0083], work function control layer 142 is an p-type work function) and a second portion having a second metal composition ([0082], work function control layer 142 is an n-type work function) different than the first metal composition, (an n-type work function is different than a p-type work function).
Kim1 and Guler do not appear to disclose:
“an interface between the first portion and the second portion overlies the dielectric wall.”
Chanemougame, which teaches a nanostructure which has an isolation pillar between first and second adjacent structures (Chanemougame, Abstract), discloses:
an interface (Chanemougame, Fig. 20B) between the first portion (a first metal 180, [0062] a P-FET metal) and the second portion (second metal 210, [0066] a N-FET metal) overlies the dielectric wall (isolation pillar 160).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim and Guler to have an interface between the first portion and the second portion overlies the dielectric wall as taught by Chanemougame for purposes of reducing gate end capacitance. (Chanemougame, [0066].)
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim1 and Guler as applied to claim 9 above, and further in view of Kim et al. US 20130285019 A1 (hereinafter Kim2).
Regarding claim 10, Kim1 and Guler disclose all the element of claim 9.
Kim1 and Guler does not appear to disclose:
the semiconductor channel is thicker at the first sidewall than at the second sidewall.
Kim2, which teaches a nano-sized channel region which is smaller at the source region than at the drain region (Kim2, Abstract), discloses:
wherein the semiconductor channel (Fig. 1, channel region CR) is thicker at the first sidewall than at the second sidewall. ([0058], channel region is non-uniform with the channel being smaller at the source than at the drain.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim1 to have the semiconductor channel is thicker at the first side than at the second side as taught by Choi for purposes of reduce fluctuation in transconductance, drain conductance, and quantum capacitance to improve the stability of the device. (Kim2, [0099].)
Claims 11 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim1 and Guler as applied to claim 9 above, and further in view of Choi et al. US 20220052046 A1 (hereinafter Choi).
The following annotated drawing will be used in discussion of Choi.
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Regarding claim 11, Kim1 and Guler disclose all the elements of claim 9.
Kim1 and Guler does not appear to disclose:
Choi, which teaches an integrated circuit device which a gate structure and adjacent source/drain regions, (Choi, Abstract) discloses:
a source/drain contact comprising a metal, (Fig. 4A, contact plugs 184, [0085] made of metal such as copper.) the source/drain contact positioned over the first source/drain epitaxial structure, (Fig. 2C, source/drain region 130 is adjacent to the nanosheet stack NSS and [0037] formed by epitaxial growth) wherein in the top views the source/drain contact has a first width adjacent to the first sidewall of the semiconductor channel (annotated Fig. 2C, width W1) and a second width adjacent to the second sidewall of the semiconductor channel, (annotated Fig. 2C, width W2) and the first width of the source/drain contact is less than the second width of the source/drain contact. (W1 is less than W2.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim1 and Guler to have a source/drain contact comprising a metal, the source/drain contact positioned over the first source/drain epitaxial structure, wherein in the top view, the source/drain contact has a first width adjacent to the first side sidewall of the semiconductor channel and a second width adjacent to the second side sidewall of the semiconductor channel, and the first width of the source/drain contact is less than the second width of the source/drain contact as taught by Choi for purposes of having a contact to the source and drain of the device.
Regarding claim 14, Kim1 disclose all the elements of claim 9.
Choi, which teaches an integrated circuit device which a gate structure and adjacent source/drain regions, (Choi, Abstract) discloses:
The semiconductor device of claim 9, wherein in the top view, the gate structure has a tapered sidewall profile between the first sidewall of the semiconductor channel and the second sidewall of the semiconductor channel. (Fig. 2C, gate structure GST has a tapered sidewall profile.)
Since Kim1 and Guler are silent regarding the gate structure having a tapered sidewall profile between the first side of the semiconductor channel and the second side of the semiconductor channel, this would motivate one of ordinary skill to seek out teachings such as Choi in order to practice the invention of primary.
Regarding claim 15, Kim1 as modified by Choi disclose all the elements of claim 14.
Choi further discloses:
a source/drain contact (Fig. 4A, contact plugs 184, [0085] made of metal such as copper.) over the first source/drain epitaxial structure, (Fig. 2C, source/drain region 130 is adjacent to the nanosheet stack NSS and [0037] formed by epitaxial growth) wherein a first portion of the sidewall of the source/drain contact extending in a first direction and a second portion of the sidewall extending in a second direction different than the first direction. (Fig. 2C shows the top that the capping layer is defined by the shape of the gate and extends a first and second direction which are different from each other.)
Regarding claim 16, Kim1 as modified by Choi disclose all the elements of claim 15.
Choi further discloses:
wherein in the top view, source/drain contact (Fig. 1, source/drain area 130) non-uniform width, such that a first portion of the source/drain contact overlying the dielectric wall is narrower than a second portion overlying the first source/drain epitaxial structure. (Fig. 1, the source/drain area 130 is shown to have a profile over isolation layer 114)
Regarding claim 17, Kim1 as modified by Choi disclose all the elements of claim 16.
Choi further discloses:
wherein in the top view, the second portion of the source/drain contact (Fig. 1, source/drain area 130) is adjacent semiconductor channel. (Fig. 1, the source/drain area is shown adjacent stack of nanosheets include the nanosheet channels N1, N2, and N3.)
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a semiconductor device comprising “the stepped sidewall profile being positioned nearer to the first sidewall than to the second sidewall.”
Prior Art Considered Pertinent
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gaul US 20240204079 A1 - A semiconductor stack including nanosheets (Abstract), Fig. 1A and Fig. 1B, shows a contact 190 on surrounding gate metal in work function metal (WFM) films 140 and 145 and which are over the spacer body 136.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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