Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is a non-final office action in response to the communication filed 7/14/2025.
Claims 1-17 and 21-23 are currently pending.
Claims 1-17 have been amended.
Claims 18-20 have been canceled.
Claims 1-17 and 21-23 have been examined.
Election/Restriction
Applicant's election with traverse of claims 1-17 in the reply filed on 9/15/2025 is acknowledged. New claims 21-23 read on elected group I and will be examined along with claims 1-17.
The traversal is on the ground(s) that applicant alleges that Examiner did not demonstrate a serious search or examination burden. This is not found persuasive because Examiner on page 3 of the restriction requirement presented the serious and examination burden was shown at due to at least separate fields of search, shown by different classification numbers that would need to be search under.
The requirement is still deemed proper and is therefore made FINAL. Furthermore, the request for rejoinder is considered moot in light of the cancellation of the claims 18-20 which were in Group II.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 1/3/2023, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Interpretation
Claims 16 and 17 include the term “recessed profile” for the source/drain contact. The Examiner was not able to understand if the “recessed profiled” was intended in the x-y top view or recessed within the thickness/z direction. For purposes of the examination the claim is read as “a recessed profile in the thickness direction.”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 15 includes the term “non-linear” as used to define the type of sidewall which is used in the specification at [0062] but is not given a particular definition, nor is it clear to the Examiner based on the plain meaning of non-linear what that means when applied to the sidewall as viewed in the top view. Arguably each sidewall component of the structure is actually linear in the top view, as each component lies within a 2D plane. However, figure 16B does appear to show that the source-drain contacts 250 each has a non-uniform shape when viewed in the top view of the structure. Thus, it seems the phrase “non-linear sidewall” does not accurately convey the structure that applicant is trying to define with the shape of the source/drain contact.
For the purposes of examination, based on Examiner’s understanding in view of the drawings, the phrase “in the top view the source/drain contact has a nonlinear sidewall” will be interpreted to mean as “in the top view the source/drain contact has a non-uniform shape.”
Claims 16 and 17 are rejected based on their dependence to claim 15. For consistency when interpreting claim 16, the phrase “the non-linear sidewall of the source/drain contact” will be interpreted to mean “the non-uniform shape of the source/drain contact”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. US 20160372467 A1 (hereinafter Kim1).
Regarding Claim 9, Kim1 discloses:
A semiconductor device, (Fig. 4, [0053], semiconductor device) comprising:
a dielectric wall (field insulating layer 101, shown in related Fig. 2 [0103]) on a substrate; (active layer 100, shown in related Fig. 2 [0103])
a semiconductor channel (active fin F1) laterally extending from a side surface of the dielectric wall, the semiconductor channel having a first side interfacing the dielectric wall and a second side facing away from the dielectric wall; and (See Fig. 4, first side being the side of the active fin that is at the interface between the area I and area II and the second side being the region that is opposite that side.)
a gate structure (Fig. 4, gate structure 192) the semiconductor channel, (the gate structure 192 is extended over the active fin F1) wherein in a top views the gate structure has a first width (width W2) adjacent to the first side of the semiconductor channel and a second width adjacent to the second side of the semiconductor channel (width W1), and the first width of the gate structure is greater than the second width of the gate structure. ([0066], W2 is greater than W1)
Regarding claim 12, Kim further discloses:
wherein in the top view, the gate structure (gate structure 192) has a curved sidewall profile between the first side of the semiconductor channel and the second side of the semiconductor channel. (Fig. 4, sidewall profile of the is curved and continuous. See also [0103].)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 13 is rejected under 35 U.S.C. 103 as obvious over Kim1.
Kim1, Fig. 4 shows sidewall profile as the width at the midpoint of fin F1 is a discrete value separate from the width of the midpoint of the first active layer I. (Kim1, [103-106]) Kim Fig. 4, does not appear to show that the profiled is necessarily a stepped profile.
Kim1, Fig. 1 which teaches the device with a different gate profile, further discloses:
wherein in the top view, the gate structure has a stepped sidewall profile between the first side of the semiconductor channel and the second side of the semiconductor channel. (Kim1, Fig. 1 shows a rectangular stepped profile for the sidewall profile.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim1 Fig.4 to have stepped sidewall profile between the first side of the semiconductor channel and the second side of the semiconductor channel as taught by Kim1, Fig. 1 for purposes of ease of manufacturing with rectangular regions these regions having the stepped profile between the width of the first section defined by W2 in the active region and the second section defined by W1 in the isolation area. (Kim1, [0050] and Fig. 1.) Combining two embodiments disclosed adjacent to each other in a prior art patent does not require a leap of inventiveness, Boston Scientific v. Cordis (Fed. Cir. 2009).
Claims 1-8 and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Kim1 in view Guler et al. US 20240113233 A1 (hereinafter Guler).
The following annotated Fig. 4 will be used in discussion:
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Regarding claim 1, Kim1 discloses:
A semiconductor device, (Fig. 4, [0053], semiconductor device) comprising:
a dielectric wall (field insulating layer 101) on a substrate (active layer 100) and extending along a first direction (Fig. 1, X-direction) from in a top view; (Fig. 4, first area I is disposed on the field insulating layer)
an isolation structure (Fig. 2, insulating film 102) in the substrate and …;
at least one first semiconductor channel (first active fin F1) on a first side of the dielectric wall; (Fig. 4, the first active fin F1 is on side of the first area I)
at least one second semiconductor (second active fin F2) channel on a second side of the dielectric wall opposite the first side of the dielectric wall; and (Fig. 4, the second active fin F2 is on the second side of the first area I)
a gate structure (gate structure 192) extending across the at least one first semiconductor channel and the one or more at least one second semiconductor channel along a second direction different from than the first direction from in the top view, (Fig. 4, the gate structure 192 extends along the Y-direction over the first active fin F1 and the second active fin F2)
wherein from in the top view (Fig. 4), the gate structure comprises a first profile (second width W2) over the at least one first semiconductor channel ([0066] the second width W2 is over the second area II), and a second profile (first width I)()over the isolation structure, the first profile has a first width adjacent the first side of the dielectric wall (Fig.1, [0066] first area I and second area II are adjacent to each other), and the first width is greater than a third width of the second profile. ([0066], W2 is greater than W1)
Kim does not appear to disclose that the isolation structure in the substrate “having a top surface lower than a top surface of the dielectric wall”.
Guler, which teaches a forkFET transistor structure with a dielectric wall adjacent to stacks of nanoribbons (Guler, Abstract), discloses:
a dielectric wall (Fig. 1A, wall 120) on a substrate (substrate 160) and extending along a first direction from in a top view; (Fig. 1D, shows that 120 extends in a thickness direction for the device.)
an isolation structure (Fig. 1A, first dielectric 151) in the substrate (is deposited within groves in the substrate 160) and having a top surface lower than a top surface of the dielectric wall; (Fig. 1A, the top surface of the 151 is lower than the top surface of the wall 120)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim to have a top surface of the isolation structure lower than a top surface of the dielectric wall as taught by Guler for purposes of having the dielectric wall material be thinner than the material used for field isolation. (Guler, [0024]. See also Guler [0023] and [0026], the material for the wall 120 may be HfO, AlN, or other dielectric material and the first dielectric may be SiO or SiN.)
Regarding claim 2, Kim1 as modified by Guler disclose all the elements of claim 1.
Kim1 further discloses:
wherein in the top view, the first profile has a second width (See annotated Fig. 4, second width WA2) at a position offset from the first side of the dielectric wall, and the second width is less than the first width. (WA2 is less than W2)
Regarding claim 3, Kim1 as modified by Guler disclose all the elements of claim 2.
Kim1 further discloses:
wherein the second width (WA2) of the first profile of the gate structure is substantially equal to the third width (W1) of the second profile of the gate structure. ([0104] The difference from W2 to W1 is a continuous change. The term substantially equal is taken to mean anything with a maximum difference of 20% of the given value as defined by the specification at [0018]. According to Kim1 the width of W2 may be 16nm and W1 maybe 14nm therefore a value for WA2 which is between those two would be considered to be less than W2 and within 20% difference of W1 therefore being substantially equal to W1.)
Regarding claim 4, Kim1 as modified by Guler disclose all the elements of claim 1.
Kim1 further discloses:
wherein in the top view, the gate structure comprises a third profile over the dielectric wall, and the third profile has a fourth width (W4 defining the width of the third profile) greater than the third width of the second profile. (W4 is greater than WA2)
Regarding claim 5, Kim1 as modified by Guler disclose all the elements of claim 1.
Kim1 further discloses:
wherein in the top view the gate structure comprises a third profile over the dielectric wall, and the third profile has a fourth width (annotated Fig. 4, width W4) substantially equal to the first width (W2) of the first profile. ([0104] The difference from W2 to W1 is a continuous change. The term substantially equal is taken to mean anything with a maximum difference of 20% of the given value as defined by the specification at [0018]. According to Kim1 the width of W2 may be 16nm and W1 maybe 14nm therefore a value for W4 which is between those two would be considered to within 20% difference of W2 therefore being substantially equal to W2.)
Regarding claim 6, Kim1 as modified by Guler disclose all the elements of claim 1.
Kim1 further discloses:
wherein in the top view, the gate structure comprises a third profile over the dielectric wall, and the third profile has a fourth width (annotated Fig. 4, width W4) less than the first width of the first profile. (W2) ([0104] The difference from W2 to W1 is a continuous change. According to Kim1 the width of W2 may be 16nm and W1 maybe 14nm therefore a value for W4 which is between those two would be less than W2.)
Regarding claim 7, Kim1 as modified by Guler disclose all the elements of claim 1.
Kim1 further discloses:
The semiconductor device of claim 1, wherein in the top view, the gate structure comprises a third profile over the at least one second semiconductor channel, and the third profile has a fourth width at adjacent the second side of the dielectric wall, the fourth width being greater than the third width of the second profile.
Regarding claim 8, Kim1 as modified by Guler disclose all the elements of claim 7.
Kim1 discloses:
wherein a second metal composition ([0082], work function control layer 142 is an n-type work function) of the third profile (W4 in second active fin F2) of the gate structure is different than a first metal composition ([0082]- [0083], work function control layer 142 is an p-type work function) of the first profile (W2 in first active fin F1) of the gate structure.
Regarding claim 21, Kim1 discloses:
A semiconductor device, (Fig. 4, [0053], semiconductor device) comprising:
…;
a dielectric wall (field insulating layer 101) extending from the first (stack) (first active fin F1) to the second (stack) (second active fin F2); and
a gate structure (Fig. 4, gate structure 192) extending along a first direction (y-direction) across and over the first (stack) (first active fin F1), the second (stack) (second active fin F2), and the dielectric wall (field insulting layer 101), the gate structure (gate structure 192) comprising:
a first portion (annotated Figure 4, portion defined by WA2) overlying a sidewall of the dielectric wall (field insulting layer 101), and having a first width (width WA2) along a second direction (x-direction) different than the first direction (y-direction); and
a second portion (portion defined by W1) offset from the sidewall (W1 is offset from WA2) and having a second width along (width W1) the second direction (x-direction), the first width exceeding the second width. (WA2 is greater than W1.)
Kim1 teaches that the embodiments herein can be used with three-dimensional semiconductor elements including transistors using nano elements such as nanowires but doesn’t specifically disclose:
“a first stack comprising a first semiconductor channel, and a second semiconductor channel overlying the first semiconductor channel;
a second stack comprising a third semiconductor channel, and a fourth semiconductor channel overlying the third semiconductor channel;”
Guler, which teaches a forkFET transistor structure with a dielectric wall adjacent to stacks of nanoribbons (Guler, Abstract), discloses:
a first stack (Fig. 1A, stack of nanoribbons 112) comprising a first semiconductor channel, and a second semiconductor channel overlying the first semiconductor channel; ([0021] and Fig. 1B the stack of nanoribbons 112 including individual nanoribbons 102 that are stacks such that a second nanoribbon channel overlays a first.)
a second stack (nanoribbons 114) comprising a third semiconductor channel, and a fourth semiconductor channel overlying the third semiconductor channel; ([0021] and Fig. 1B the stack of nanoribbons 114 including individual nanoribbons 102 that are stacks such that a third nanoribbon channel overlays a fourth.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim to have a first stack comprising a first semiconductor channel, and a second semiconductor channel overlying the first semiconductor channel and a second stack comprising a third semiconductor channel, and a fourth semiconductor channel overlying the third semiconductor channel as taught by Guler for purposes of including more transistors in a smaller footprint. (Guler, [0010].)
Regarding claim 22, Kim1 as modified by Guler disclose all the elements of claim 9.
Guler further discloses:
a first source/drain region adjacent the first semiconductor channel and the second semiconductor channel; (Fig. 1B, epitaxial layer 110 within a source 106 and epitaxial layer 111 within a drain 108. See also [0027] the epitaxial layer 111a is connected to the nanoribbons in stack 112 and a similar connection is made for the drain region.)
a second source/drain region adjacent the third semiconductor channel and the fourth semiconductor channel; and (Fig. 1B, epitaxial layer 110 within a source 106 and epitaxial layer 111 within a drain 108. See also [0027] the epitaxial layer 111b is connected to the nanoribbons in stack 114 and a similar connection is made for the drain region)
a source/drain contact extending across the dielectric wall, the first source/drain region, and the second source/drain region, the source/drain contact having a recessed profile over the dielectric wall. (Fig. 1E, the first and second epitaxial layers 111a and 111b extend over the wall 120 and are have a recessed profile over the wall 120.)
Regarding claim 23, Kim1 as modified by Guler disclose all the elements of claim 21.
Kim1 further discloses:
a third portion (See annotated Fig. 4, the portion defined by W3) overlying a second sidewall of the dielectric wall (field insulting layer 101), the second sidewall being opposite the sidewall, (See annotated Fig. 4) the third portion having a third width (width W3) along the second direction (x-direction), the third width exceeding the second width. (W3 is greater than W1.)
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim1 as applied to claim 9 above, and further in view of Kim et al. US 20130285019 A1 (hereinafter Kim2).
Regarding claim 10, Kim1 disclose all the element of claim 9.
Kim2, which teaches a nano-sized channel region which is smaller at the source region than at the drain region (Kim2, Abstract), discloses:
wherein the semiconductor channel (Fig. 1, channel region CR) is thicker at the first side than at the second side. ([0058], channel region is non-uniform with the channel being smaller at the source than at the drain.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim1 to have the semiconductor channel is thicker at the first side than at the second side as taught by Choi for purposes of reduce fluctuation in transconductance, drain conductance, and quantum capacitance to improve the stability of the device. (Kim2, [0099].)
Claims 11 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim1 as applied to claim9 above, and further in view of Choi et al. US 20220052046 A1 (hereinafter Choi).
The following annotated drawing will be used in discussion of Choi.
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Regarding claim 11, Kim1 disclose all the elements of claim 9.
Choi, which teaches an integrated circuit device which a gate structure and adjacent source/drain regions, (Choi, Abstract) discloses:
a source/drain epitaxial structure adjacent the semiconductor channel; (Fig. 2C, source/drain region 130 is adjacent to the nanosheet stack NSS and [0037] formed by epitaxial growth) and
a source/drain contact over the source/drain epitaxial structure, (capping layer 138) wherein in the top views the source/drain contact has a first width adjacent to the first side of the semiconductor channel (annotated Fig. 2C, width W1) and a second width adjacent to the second side of the semiconductor channel, (annotated Fig. 2C, width W2) and the first width of the source/drain contact is less than the second width of the source/drain contact. (W1 is less than W2.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim1 to have a source/drain epitaxial structure adjacent the semiconductor channel, a source/drain contact over the source/drain epitaxial structure, wherein in the top views the source/drain contact has a first width adjacent to the first side of the semiconductor channel and a second width adjacent to the second side of the semiconductor channel, and the first width of the source/drain contact is less than the second width of the source/drain contact as taught by Choi for purposes of having a contact to the source and drain of the device.
Regarding claim 14, Kim1 disclose all the elements of claim 9.
Choi, which teaches an integrated circuit device which a gate structure and adjacent source/drain regions, (Choi, Abstract) discloses:
The semiconductor device of claim 9, wherein in the top view, the gate structure has a tapered sidewall profile between the first side of the semiconductor channel and the second side of the semiconductor channel. (Fig. 2C, gate structure GST has a tapered sidewall profile.)
Since Kim1 is silent regarding the gate structure has a tapered sidewall profile between the first side of the semiconductor channel and the second side of the semiconductor channel, this would motivate one of ordinary skill to seek out teachings such as Choi in order to practice the invention of primary.
Regarding claim 15, Kim1 as modified by Choi disclose all the elements of claim 14.
Choi further discloses:
a source/drain epitaxial structure (Fig. 2B, source/drain areas 130 and [0027] formed by epitaxial growth) interfacing the semiconductor channel; and (Fig. 2B, nanosheet stack NSS including nanosheets N1, N2, N3)
a source/drain contact (capping layer 138) over the source/drain epitaxial structure, wherein in the top views the source/drain contact has a has a non-uniform shape. (Fig. 2C shows the top that the capping layer is defined by the shape of the gate and is there for a non-uniform shape when in top view.)
Regarding claim 16, Kim1 as modified by Choi disclose all the elements of claim 15.
Choi further discloses:
wherein in the top view, the non-unform shaped source/drain contact (Fig. 1, source/drain area 130) has a recessed profile over the dielectric wall. (Fig. 1, the source/drain area 130 is shown to have a profile over isolation layer 114)
Regarding claim 17, Kim1 as modified by Choi disclose all the elements of claim 16.
Choi further discloses:
wherein in the top view, the recessed profile of the source/drain contact (Fig. 1, source/drain area 130) is over semiconductor channel. (Fig. 1, the source/drain area is shown over stack of nanosheets include the nanosheet channels N1, N2, and N3.)
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tsai et al. US 20190172909 A1 – Fig. 2 gate structure 120 is L-shaped therefore having an area where the width is wider than a second area over the active region on the transistor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812