DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 recites the limitation "the first surface" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13 thru 15, 17, 19, 20 thru 26, and 33 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. US 10,446,688 B1. Huang discloses (see, for example, FIG. 1) a method of forming a thin film transistor 101 comprising forming a gate material layer 22 over a substrate 10, forming a first interfacial layer 32, forming an insulator 33 on the first interfacial layer 32, and active layer 40P.
Regarding claim 14, see, for example, FIG. 1 wherein Huang discloses a gate electrode structure comprising the gate material layer 22 and the first interfacial layer 32. In column 7, lines 18-20, Huang discloses the gate material layer (i.e. first work function) 22 being metals such as copper, etc., and, in column 7, lines 39-51, discloses the first interfacial layer (i.e. second work function) 32 being silicon oxide, etc. wherein these materials have different work function from each other. In FIG. 3, Huang discloses increasing the work function by an oxygen doping treatment (i.e. surface treatment) 91.
Regarding claim 15, see, for example, FIG. 3 wherein Huang discloses an oxygen doping treatment (i.e. surface treatment) 91 wherein the oxygen doping treatment 91 is applied closest to the top surface of the first interfacial layer 32 rather than the bottom surface so that the top surface has a highest concentration of dopants (i.e. oxygen) at the top surface rather than the bottom surface of the first interfacial layer 32. In FIG. 1, Huang discloses the first surface of the first interfacial layer 32 contacting the first lower surface of the insulator 33.
Regarding claim 17, see, for example, FIG. 1 wherein Huang also discloses depositing a second interfacial layer 32 on the first interfacial layer 31, thereby forming a dipole between the first interfacial layer 31 and the second interfacial layer 32.
Regarding claim 19, see, for example, column 7, lines 39-51 wherein Huang discloses the first interfacial layer 31, second interfacial layer 32, and insulator may include different materials such as silicon oxide, and high dielectric constant materials like aluminum oxide, etc.
Regarding claim 20, see, for example, column 8, lines 38-50 wherein Huang discloses the active layer 40P comprises a metal oxide film, wherein the active layer 40P is separated from the first interfacial layer 32 by the insulator 33, and wherein the insulator 33 is separated from the gate material layer 40P by the first interfacial layer 32.
Regarding claim 21, see, for example, FIG.1 wherein Huang discloses a method of forming an integrated device 101 comprising forming a gate material layer 22 and a first interfacial layer 31 over a substrate 10, and forming an insulator 33 on the first interfacial layer 31. In FIG. 3, Huang discloses an oxygen doping treatment (i.e. surface treatment) 91 wherein the oxygen doping treatment 91 is applied closest to the top surface of the first interfacial layer 31 rather than the bottom surface so that the top surface has a highest concentration of dopants (i.e. oxygen) at the top surface rather than the bottom surface of the first interfacial layer 31. The oxygen doping treatment 91 implants oxygen (i.e. oxygen areal density) into the first interfacial layer 31, and insulator 33. In FIG. 5, Huang discloses forming an active layer 40P on the insulator 32 after forming the insulator 33, and, in FIG. 10, forming source/drain terminals 50S/50D on the active layer 40P.
Regarding claim 22, see, for example, column 8, lines 38-50 wherein Huang discloses the active layer 40P comprises II-VI compounds (i.e. undoped semiconductor material), and in FIG. 3 wherein Huang discloses the active layer 40P being separated from the first interfacial layer 31 by the insulator 33.
Regarding claim 23, see, for example, FIG. 3 wherein Huang discloses an oxygen doping treatment (i.e. surface treatment) 91 wherein the oxygen doping treatment 91 is applied closest to the top surface of the first interfacial layer 31 rather than the bottom surface so that the top surface has a highest concentration of dopants (i.e. oxygen) at the top surface rather than the bottom surface of the first interfacial layer 31.
Regarding claim 24, see, for example, FIG. 3, and column 7, lines 18-20 wherein Huang discloses the gate material layer 22 being conductive, and being formed on the first interfacial layer 31. In FIG. 3, Huang discloses the first interfacial layer 31, second interfacial layer 32, and insulator 33. In column 7, lines 39-51, Huang discloses the first interfacial layer 31, second interfacial layer 32, and insulator 33 may include different materials such as silicon oxide, high dielectric constant materials like aluminum oxide, etc.
Regarding claim 25, see, for example, column 7, lines 66-column 8, lines 10 wherein Huang discloses the first interfacial layer 31 may be the oxygen provider layer as well as second interfacial layer 32, and insulator 33.
Regarding claim 26, see, for example, column 7, lines 35-39 wherein Huang discloses the first interfacial layer 31, second interfacial layer 32, and insulator 33 being stacked sequentially, and on the upper surface of the gate electrode structure 22, and in FIG. 5, Huang discloses the active layer 40P being subsequently formed on an exposed upper surface of the insulator 33.
Regarding claim 33, see, for example, FIG. 1 wherein Huang discloses forming a source/drain structures 50S/50D over the active layer 40P, wherein the source/drain structures 50S/50D interface with the second upper surface of the active layer 40P, and wherein the active layer 40P is directly between the source/drain structures 50S/50D and the insulator 33 and separates the source/drain structures 50S/50D from the insulator 33.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. US 10,446,688 B1 as applied to claims 13-15, 17, 19, 20-26, and 33, and further in view of
above, and further in view of Wang et al. US 2019/0140106 A1. Huang discloses (see, for example, column 7, lines 39-51) the first interfacial layer 32 includes silicon oxide, but does not expressly disclose the surface treatment comprises a hydrogen treatment, an oxygen treatment, and a nitrogen treatment, each performed consecutively in situ. However, Wang discloses (see, for example, paragraph [0024]) forming a silicon oxide layer by mixing hydrogen, then oxygen/nitrogen. It would have been obvious to one of ordinary skill in the art to have the surface treatment comprising a hydrogen treatment, an oxygen treatment, and a nitrogen treatment, each performed consecutively in situ in order to precisely control the characteristics of the interfacial layer while maintaining good film quality.
Claim(s) 27 thru 30, and 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. US 10,446,688 B1 as applied to claims 13-15, 17, 19, 20-26, and 33, and further in view of Koezuka et al. US 2017/0053950 A1. Huang discloses (see, for example, FIG. 1) a method of forming an integrated device 101 comprising forming a gate material layer 22 over a substrate 10, the gate material layer 22 comprising a conductive material and having a first thickness; forming a first interfacial layer 31, forming an insulator 33 over the first interfacial layer 31; forming an active layer 40P having a fourth thickness; and forming source/drain terminals 50S/50D. In column 8, lines 38-50, Huang discloses the active layer 40P comprises II-VI compounds (i.e. dopant concentration less than 1010 atoms per cubic centimeter) that are undoped. Even though Huang shows (see, for example, FIG. 1) the fourth thickness of the active layer 40P being less than the first thickness of the gate material layer 22, Huang does expressly disclose the fourth thickness of the active layer being less than the first thickness of the gate material layer. However, Koezuka discloses (see, for example, FIG. 2A) a method comprising forming an active layer 105 and a gate material layer 102. In paragraph [0269], Koezuka discloses the active layer 105 being greater than or equal to 3 nm, etc., and in paragraph [0171], Koezuka discloses the gate material layer 102 being 100 nm. It would have been obvious to one of ordinary skill in the art to have the fourth thickness of the active layer being less than the first thickness of the gate material layer in order to minimize leakage while improving overall stability according to the preferences of the user. Further, a change in size is generally recognized as being with the level of ordinary skill in the art. In re Rose, 105 UPSQ 237 (CCPA 1955).
Regarding claim 28, see, for example, FIG. 3 wherein Huang discloses a first interfacial layer 31 and the insulator 33 being exposed to an oxygen doping process 91 wherein the oxygen doped process produces different oxygen areal densities between the first interfacial layer 31 and insulator 33.
Regarding claims 29-30, see, for example, column 7, lines 66-column 8, lines 10 wherein Huang discloses the first interfacial layer 31 may be the oxygen provider layer as well as second interfacial layer 32, and insulator 33, and the oxygen doping process 91 consequently alters the oxygen areal density.
Regarding claim 32, see, for example, FIG. 1 wherein Huang disclose a second interfacial layer 33, which is exposed to the oxygen doping process 91.
Claim(s) 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. US 10,446,688 B1 in view of Koezuka et al. US 2017/0053950 A1 as applied to claims 27-30, and 32 above, and further in view of Wang et al. US 2019/0140106 A1. Huang in view of Koezuka does not disclose a nitrogen treatment. However, Wang discloses (see, for example, paragraph [0024]) forming a silicon oxide layer by mixing hydrogen, then oxygen/nitrogen. It would have been obvious to one of ordinary skill in the art to have a nitrogen treatment in order to precisely control the characteristics of the interfacial layer while maintaining good film quality.
Response to Arguments
Applicant’s arguments with respect to claim(s) 13-17, and 19-33 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Eugene Lee
January 12, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815