Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, drawn to a method of manufacture, in the reply filed on 12/05/2025 is acknowledged.
Claim Objections
Claim 21 is objected to because of the following informalities: the phrase “gate tack”, presumably, is meant to read, “gate stack”, and will be examined as such in Claim 21. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3,8,11 and 21-24 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ryu et al (USPGPUB 20240055425, hereinafter “Ryu”).
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Regarding Claim 1, Ryu teaches (Fig. 11A and 12A) a method for forming a semiconductor device structure, comprising: forming a gate stack (165 of Fig. 12A), a first source/drain structure (120A, hereinafter “1SD”) and a second source/drain structure (the epitaxial structure seen to the right of, and identical to, structure 120A, hereinafter “2SD”) over a front surface (bottom surface of Fig. 11A) of a substrate (the semiconductor device is seen in Fig. 11A being made of a substrate 101), wherein the gate stack (165) is between the (gate stack 165 is seen situated between the first and second source drain structures 1SD and 2SD) first source/drain structure (1SD) and the second source/drain structure (2SD); removing a first portion of the substrate (a portion of the substrate 101of the device is seen being removed from the back surface) from a back surface (top surface of the device could be considered a back surface of the substrate) of the substrate to form a through hole (RC) in the substrate (a through hole is seen formed in the substrate from the back surface), wherein the through hole (RC) passes through the substrate and exposes a second portion of the first source/drain structure ([0046], “the source/drain regions 120 in this embodiment may include a plurality of epitaxial layers having different compositions and/or impurity concentrations ”; Fig. 10A, the through hole RC is seen, and one of the inherent possible embodiments seen here would be the forming of a second epitaxial layer 120B only after forming 120A exposing a second portion of 120B); forming a semiconductor structure (120B) in the through hole (RC); forming a silicide layer (181) in the through hole (RC) and over the semiconductor structure (120B); and forming a contact structure (180 and 182, which together form a single conductive body, hereinafter “CS”) in the through hole (RC) and over the silicide layer (181).
Regarding Claim 2, Ryu teaches the method for forming the semiconductor device structure as claimed in claim 1, wherein the semiconductor structure (120B) is in contact with the first source/drain structure (120A).
Regarding Claim 3, Ryu teaches the method for forming the semiconductor device structure as claimed in claim 1, wherein the silicide layer (181) is in contact with the semiconductor structure (120B) and the contact structure (CS).
Regarding Claim 8, Ryu teaches the method for forming the semiconductor device structure as claimed in claim 1, wherein a width of the semiconductor structure (120B) decreases toward (the width of the semiconductor structure 120B is seen having a region where there is a tapering shape, and thus a decreasing width, as it moves towards the front side, bottom, of the device) the first source/drain structure (120A).
Regarding Claim 11, Ryu teaches a method for forming a semiconductor device structure, comprising: forming a gate stack (165), a first source/drain structure (1SD) and a second source/drain structure (2SD) over a front surface (bottom of Fig. 12A) of a substrate, wherein the gate stack (165) is between (the gate stack 165 is seen between the first source/drain structure 1SD and the second source/drain structure 2SD) the first source/drain structure (1SD) and the second source/drain structure (2SD); removing a first portion of the substrate from a back surface (top surface of Fig. 12A) of the substrate to form a through hole (RC) in the substrate, wherein the through hole passes through the substrate (101) and exposes a second portion of ([0046], “the source/drain regions 120 in this embodiment may include a plurality of epitaxial layers having different compositions and/or impurity concentrations ”; Fig. 10A, the through hole RC is seen, and one of the inherent possible embodiments seen here would be the forming of a second epitaxial layer 120B only after forming 120A of the first source/drain structure 1SD exposing a second portion of 120B) the first source/drain structure (1SD) ; and performing an epitaxial process on the second portion of the first source/drain (2SD) structure to form a source/drain extension structure (120B) on the second portion (top portion of first source/drain structure 1SD) of the first source/drain structure (1SD).
Regarding Claim 21, Ryu teaches (Figs. 11A, 12A) a method for forming a semiconductor device structure, comprising: forming a channel structure (145), a gate stack (165), and an epitaxial structure (120A) over a substrate, wherein the epitaxial structure (120A) is beside the channel structure (145), and the gate stack (165) covers (gate stack 165 covers the channel structure 145) the channel structure (145); partially removing the substrate to form an opening (RC) exposing a bottom of () the epitaxial structure (120A); growing a semiconductor structure (120B) on the bottom (from the perspective seen in Fig. 12A, the bottom of the device would actually be the top of the figure) of the epitaxial structure to partially fill the opening (the opening RC is seen partially filled by the semiconductor structure 120B); and forming a backside contact (180) structure at least partially filling (part of the opening RC is seen filled by the backside contact structure 180 as seen in Fig. 14) the opening (RC).
Regarding Claim 22, Ryu teaches the method for forming the semiconductor device structure as claimed in claim 21, wherein the opening (RC) gradually becomes wider along a direction away from (the opening RC is seen widening in a direction towards the backside of the device, away from epitaxial structure 120A) the epitaxial structure (120A).
Regarding Claim 23, Ryu teaches (Fig. 12A) the method for forming the semiconductor device structure as claimed in claim 21, wherein a bottommost surface of the gate stack (165) is vertically between (Fig. 12A, bottommost surface of the gate stack 165 is seen between opposite vertical surfaces of semiconductor structure 120B) opposite surfaces of the semiconductor structure (120B).
Regarding Claim 24, Ryu teaches (Figs. 6A-12B) the method for forming the semiconductor device structure as claimed in claim 21, further comprising: forming a metal silicide structure (181) on a surface of the semiconductor structure (120B) before (the method seen in Figs. 6A-12B illustrates working backwards from the bottom of the opening RC, and thus it is understood to be inherent that the silicide structure 181 is formed prior to the formation of the backside contact structure 180) the backside contact structure is formed (180).
Allowable Subject Matter
Claims 4-7, 9-10, 12-15, and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 4, the closest available reference, that of Ryu, fails to teach, alone or in any reasonable combination with any other available reference, the limitation, “further comprising: forming a dielectric layer over an inner wall of the through hole before the forming of the semiconductor structure in the through hole”. Ryu is silent with regards to a dielectric layer, and no other reference available teaches a dielectric layer being placed adjacent to a semiconductor structure that would motivate one to incorporate it as seen in Claim 4. Claims 5-7 are dependent upon Claim 4.
Regarding Claim 9, the closest available reference, that of Ryu, fails to teach, alone or in any reasonable combination with any other available reference, the limitation, “the silicide layer is wider than the second portion of the first source/drain structure”. Ryu is silent with regards to the silicide layer being wider than the source/drain structure, and altering the geometry of the device would not be reasonably suggested/motivated by any other available references.
Regarding Claim 10, the closest available reference, that of Ryu, fails to teach, alone or in any reasonable combination with any other available reference, the limitation, “forming an insulating layer over the front surface of the substrate before the forming of the first source/drain structure and the second source/drain structure over the front surface of the substrate”. Ryu is silent with regards to an insulation layer on the front side of the device, and no other reference would reasonably motivate incorporating the formation of the device prior to forming source/drain structures.
Regarding Claim 12, the closest available reference, that of Ryu, fails to teach, alone or in any reasonable combination with any other available reference, the limitation “forming a dielectric layer over an inner wall of the through hole before the epitaxial process, wherein the dielectric layer separates the source/drain extension structure from the substrate”. Ryu is silent with regards to a dielectric layer, and no other reference available teaches a dielectric layer being placed adjacent to the source/drain structures, and that would motivate one to incorporate it as seen in Claim 12. Claim 13 is dependent upon Claim 12.
Regarding Claim 14, the closest available reference, that of Ryu, fails to teach, alone or in any reasonable combination with any other available reference, the limitation, ” forming an insulating layer over the front surface of the substrate before the forming of the first source/drain structure and the second source/drain structure over the front surface of the substrate”. Ryu is silent with regards to an insulation layer on the front side of the device, and no other reference would reasonably motivate incorporating the formation of the device prior to forming source/drain structures. Claim 15 is dependent upon Claim 14.
Regarding Claim 25, the closest available reference, that of Ryu, fails to teach, alone or in any reasonable combination with any other available reference, the limitation, “forming a frontside contact structure electrically connected to the epitaxial structure before the opening is formed.”. Ryu is silent with regards to a contact structure electrically connected to the epitaxial structure, and the incorporation of such a structure would not be reasonably taught so as to be incorporated into the device of Ryu, at the point in the process-flow of the method of making the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR J LASASSO whose telephone number is (703)756-5668. The examiner can normally be reached M-F 8-5 EST.
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/V.J.L./Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898