DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 15-20 & 21-34 in the reply filed on 10/09/2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 22-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22 recites the limitations “a first substrate” and “a first semiconductor substrate” in lines 3-4. It is unclear if said terms refer to the same or different structural feature. The same ambiguity remains surrounding “a second substrate” and “a second semiconductor substrate” in lines 7-8. Clarification/correction is required.
Claims 23-28 are rejected for being dependent on claim 22.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15 & 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Thei et al. (US Pub. 2019/0363079) in view of Hoffmann et al.(US Pub. 2012/0280326).
Regarding claim 15, Thei teaches a method for forming a semiconductor structure, the method comprising:
forming a first integrated circuit (IC) die (104a or 104b) repeating across a first substrate (106a or 106b) that is a wafer, wherein the first IC die comprises a first semiconductor device (302a or 302b) on and partially formed by the first substrate (Fig. 3);
forming a second IC die (104b or 104a) comprising a second semiconductor device (302b or 302a) on and partially formed by a second substrate (106b or 106a, see Fig. 3);
bonding and electrically coupling the first and second IC dies (104a & 104b) together while the second IC die 104b overlies the first IC die 104a (Fig. 3); and
singulating the first IC die to separate instances of the first IC die from each other, wherein the singulating of the first IC die is performed after the bonding (Fig. 1-3 and Para [0019 & 0026], note that the first and second IC dies are bonded and singulated after the bonding while being protected by the seal ring structure 102).
Thei is silent on wherein the first and second semiconductor devices comprise group III-V material.
However, Hoffmann discloses wherein a first and second semiconductor devices comprise group III-V material (Para [0006]). This has the advantage of obtaining a semiconductor device with high electron mobility and wide bandgap characteristics. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Thei with incorporating the III-V material into the first and second semiconductor devices, as taught by Hoffmann, so as to obtain a device with high electron mobility and wide bandgap characteristics.
Regarding claim 21, The combination of Thei and Hoffmann teaches the method according to claim 15, wherein the first and second semiconductor devices (302a & 302b) correspond to transistors and have individual source/drain regions electrically coupled together at completion of the bonding (Fig. 3).
Regarding claim 22, Thei teaches a method for forming a semiconductor structure, the method comprising:
forming a first semiconductor device (302a or 302b) over a first substrate (106a or 106b) overlying a first semiconductor substrate (Fig. 3);
forming a first interconnect structure (108a or 108b) overlying and electrically coupled to the first semiconductor device (302a or 302b, Fig. 3);
forming a second semiconductor device (302b or 302a) over a second substrate (106b or 106a) overlying a second semiconductor substrate (Fig. 3);
forming a second interconnect structure (108b or 108a) overlying and electrically coupled to the second semiconductor device (302b or 302a, Fig. 3); and
bonding and electrically coupling the first and second interconnect structures together, such that the first and second semiconductor devices (302a & 302b) are between the first and second substrates (106a & 106b).
Thei is silent on wherein the first and second semiconductor devices comprise a fist and second group III-V layer.
However, Hoffmann discloses wherein a first and second semiconductor devices comprise a first and second group III-V layers (Para [0006]). This has the advantage of obtaining a semiconductor device with high electron mobility and wide bandgap characteristics. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Thei with incorporating the III-V material into the first and second semiconductor devices, as taught by Hoffmann, so as to obtain a device with high electron mobility and wide bandgap characteristics.
Regarding claim 23, The combination of Thei and Hoffmann teaches the method according to claim 22, wherein an outermost edge of the second substrate overlies the first semiconductor device after the bonding (Fig. 3).
Allowable Subject Matter
Claims 29-34 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 29, the prior art of record fails to teach or suggest, a method for forming a semiconductor structure, the method comprising: forming a first integrated circuit (IC) die on a first wafer, wherein the first IC die comprises a first semiconductor device; forming a second IC die on a second wafer, wherein the second IC die comprises a second semiconductor device; bonding and electrically coupling the second IC die to the first IC die; and bonding the first IC die to an interposer, which is on an opposite side of the first IC die as the second IC die; and wire bonding the interposer to the first IC die; wherein the first and second semiconductor devices comprise a wide-bandgap semiconductor material with a bandgap greater than a bandgap of silicon.
Claims 30-34 are allowed as being directly or indirectly dependent of the allowed independent base claim 29.
Claims 16-20 & 24-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TIMOR KARIMY/Primary Examiner, Art Unit 2818