DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 01/27/2026 has been accepted and entered. Claims 18-20, 22-27, 30-31, 34, and 37-44 remain pending in this application.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the method step wherein the etch forms the pair of sidewall spacers from portions of the dielectric layer having individual top surfaces completely exposed to an etchant of the etch, recited in claim 24 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first separation, the second separation, and the third separation recited in claim 42 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 24-27, 30, 38-40, and 42 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) 24 contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 24, the Applicant’s disclosure at the time of the effective filing date did not provide support for the “portions of the dielectric layer having individual top surfaces completely exposed to an etchant of the etch” in Lines L18-19. The support for a method for forming an image sensor wherein having a dielectric layer 1902 etched to form a pair of sidewalls 202A/B and dielectric structure 120 in Fig 19 (pre-exposure) and Fig 20 (post-exposure), does not show possession of a method for forming an image sensor wherein “portions of the dielectric layer having individual top surfaces completely exposed to an etchant of the etch” The specification in paragraph [0132] states that “the etching process removes unmasked horizontal portions of dielectric layer 1902, thereby leaving masked portions of the dielectric layer 1902 in place as the dielectric structure 120 and vertical portions of the dielectric layer 1902 in place as the plurality of sidewall spacers 202. In some embodiments, the etching process may be or comprise, for example, a wet etching process, a dry etching process, a RIE process, some other etching process, or a combination of the foregoing” but does not explain how the portions of the dielectric layer having individual top surfaces completely exposed to an etchant of the etch, and what “completely” consists of.
Consequently, applicant has not pointed out where the new claim 24 is supported, nor does there appear to be a written description of the claim limitation “portions of the dielectric layer having individual top surfaces completely exposed to an etchant of the etch” in the application, as filed on 01/27/2026.
Regarding claim 42, the Applicant’s disclosure at the time of the effective filing date did not provide support for “wherein the pair of gate electrodes have individual bottom surfaces inset into the semiconductor substrate and separated by a first separation and further have individual top surfaces separated by a second separation less than the first separation, and wherein the well region has a pair of outer sidewall boundaries facing the pair of gate electrodes and separated by a third separation that is closer to the second separation than to the first separation” in Lines L1-6.
The support for a method for forming an image sensor wherein having a pair of gate electrodes 114a and 114b formed in the substrate 102 in Fig 22, does not show possession of a method for forming an image sensor “wherein the pair of gate electrodes have individual bottom surfaces inset into the semiconductor substrate and separated by a first separation and further have individual top surfaces separated by a second separation less than the first separation, and wherein the well region has a pair of outer sidewall boundaries facing the pair of gate electrodes and separated by a third separation that is closer to the second separation than to the first separation”.
Applicant fails to point out where support can be found in the specification with enough specificity. Applicant has just pointed out to the general figures Fig3, Fig 13-27. The burden is on the applicant to point out where support where support for each individual claim can be found. Applicant has not pointed out where the new claim 42 is supported, nor does there appear to be a written description of the claim limitation “wherein the pair of gate electrodes have individual bottom surfaces inset into the semiconductor substrate and separated by a first separation and further have individual top surfaces separated by a second separation less than the first separation, and wherein the well region has a pair of outer sidewall boundaries facing the pair of gate electrodes and separated by a third separation that is closer to the second separation than to the first separation” in the application, as filed on 01/27/2026.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 24-27, 30, 38-40, and 42 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 24, the limitation “portions of the dielectric layer having individual top surfaces completely exposed to an etchant of the etch” in Lines L18-19, renders the claim indefinite because the term "completely" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “completely” is defined as "to a full, total, or entire extent” (see Merriam-webster.com). This language is indefinite as the specification does not describe what completely means in regard of exposing portions of the dielectric layer having individual top surfaces to an etchant of the etch. Would this mean that the portions of the dielectric layer having individual top surfaces dipped into a bath of an etchant of the etch, or that the portions of the dielectric layer having individual top surfaces are exposed to an etchant of the etch coming from the top, or coming from all sides? Thus, it is unclear because defining how portions of the dielectric layer having individual top surfaces can be or not exposed to an etchant of the etch, is not clearly defined. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear.
Under the principles of compact prosecution, the claim 24 limitation is being interpretated as – from portions of the dielectric layer having individual top surfaces exposed to an etchant of the etch--.
Claim 42 recites the limitation " closer " in line L6. The term "closer" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Closer” is defined as "less far” (see Merriam-webster.com). This language is indefinite as the specification does not describe what closer means in regard of having a third separation closer to the second separation than to the first separation. Would this mean that the third separation is closer in size to the second separation than to the first separation, or the third separation is in close proximity to the second separation but further away from the first separation? Thus, it is unclear because defining how the third separation is closer to the second separation than to the first separation can be or not, is not clearly defined. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear.
Under the principles of compact prosecution, the claim 42 limitation is being interpretated as –in closer proximity--.
Additionally, regarding claim 42, the limitation “wherein the pair of gate electrodes have individual bottom surfaces inset into the semiconductor substrate and separated by a first separation and further have individual top surfaces separated by a second separation less than the first separation, and wherein the well region has a pair of outer sidewall boundaries facing the pair of gate electrodes and separated by a third separation that is closer to the second separation than to the first separation” in Lines L1-6, renders the claim indefinite because the limitation " individual top surfaces separated by a second separation less than the first separation " is unclear which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The claim limitation “individual top surfaces separated by a second separation less than the first separation” can related to the different dielectric layers or etch stop layer, their length, or width, or can related to the relative distance between the two gate electrodes This language is indefinite as the specification does not describe what individual top surfaces separated by a second separation less than the first separation means in regard of how the first separation is less than the second separation. Would this mean that the different dielectric layers or etch stop layer have one of their dimensions such as length, or width being less than the second dimension, or one of the relative distances between the pair of gate electrodes is less than the second relative distance between the pair of gate electrodes? Thus, it is unclear because defining how portions of the dielectric layer having individual top surfaces can be or not exposed to an etchant of the etch, is not clearly defined. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear.
Under the principles of compact prosecution, the claim 42 limitation is being interpretated as – wherein the pair of gate electrodes have individual bottom surfaces inset into the semiconductor substrate and separated by a first horizontal distance and further have individual top surfaces separated by a second horizontal distance less than the first horizontal distance, and wherein the well region has a pair of outer sidewall boundaries facing the pair of gate electrodes and separated by a third horizontal distance that is in closer proximity to the second horizontal distance than to the first horizontal distance--.
The balance of claims are rejected to for being dependent upon an already rejected claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 24-27, and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sze et al. (US 20200176500 A1 from IDS-Sze00) in view of Lee et al. (US20200212093A1-Lee93).
Regarding claim 24, Sze00 discloses a method for forming an image sensor (Abstract L3), the method comprising:
forming a pair of photodetectors (Forming two photodetectors 108-Fig 1, [0153] L 3-4) bordering in a semiconductor substrate (neighboring so bordering in a semiconductor substrate-[0153] L3-4);
forming a pair of gate electrodes (forming two transfer gates 110 with gate electrodes 112-Fig 1, [0153] L5-6, [0029] L2-4);
respectively overlying the pair of photodetectors (two gate electrodes 112 overlying two photodetectors 108-Fig 1);
depositing a dielectric layer overlying the pair of gate electrodes and a boundary region between the pair of gate electrodes (depositing ILD 140 over two gate electrodes 112 and a region between the gate electrodes-Fig 1, [0091] L12-14);
forming a mask overlying the boundary region (forming a patterned masking layer 1620 over the boundary central region-Examiner's annotated Fig 17F, [0104] L4-7, [0104]), between and laterally offset from the pair of gate electrodes (central part of mask 1620 offset the pairs of electrodes 112-Examiner's annotated Fig 17F);
performing an etch into the dielectric layer with the mask in place to form a dielectric structure underlying the mask at the boundary region (Performing an etch-[0105]; forming the dielectric structure/central part of 140-Examiner's annotated Fig 17F) and
to further form a pair of sidewall spacers respectively on sidewalls of the pair of gate electrodes (Forming pair of sidewall spacers 212 on substrate 104, along the sidewall of gate electrodes 112-Fig 17C, [0122) L2-3,[0089] L2-11);
doping the semiconductor substrate with the dielectric structure in place to form a pair of floating diffusion nodes respectively bordering the pair of gate electrodes and outside the boundary region (Doping the substrate 104 to form a pair of FD nodes 116 closed to gate electrodes 112 outside the boundary/central region- Examiner's annotated Fig 17F, [0090]); and
forming a trench isolation structure extending completely through the semiconductor substrate at the boundary region (Trench 208/210 or BDTI 106 extending across substrate 104-Fig 16E, [0027] L7-8, [0150]).
Sze00 does not disclose a method for forming an image sensor
wherein the etch forms the pair of sidewall spacers with a height greater than a height of the dielectric structure and
from portions of the dielectric layer having individual top surfaces completely exposed to an etchant of the etch.
Lee93 teaches a method for forming an image sensor
wherein the etch forms the pair of sidewall spacers with a height greater than a height of the dielectric structure (the pair of spacers 118 with a height greater than the height of the dielectric structure 206-Fig 3) and
from portions of the dielectric layer having individual top surfaces completely exposed to an etchant of the etch( [0053] L9-12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method for forming an image sensor of Sze00 as taught by Lee93 for the purpose of improving performance of the integrated image sensor by mitigating leakage currents while improving an image lag of the gate structure (Lee93:[0022]).
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Regarding claim 25, Sze00 and Lee93 combination discloses all the elements of claim 24, as noted above.
Sze00 further discloses a method for forming an image sensor
wherein the trench isolation structure (DTI 210 contact the dielectric structure Middle 140-Examiner's annotated Fig 17F) contacts the dielectric structure.
Regarding claim 26, Sze00 and Lee93 combination discloses all the elements of claim 24, as noted above.
Sze00 further discloses a method for forming an image sensor further comprising:
depositing an etch stop layer (Patterned mask 1620-Examiner's annotated Fig 17F) overlying the pair of gate electrodes, the pair of sidewall spacers, and the dielectric structure (1620 overlaying two gate electrodes 112, sidewall spacers 212, and dielectric structure middle 140-Examner's annotated Fig 17F); and
forming a pair of contacts extending through the etch stop layer respectively to the pair of floating diffusion nodes (Forming two contacts 130 in trenches 1622 extending through etch stop 1620 to the pair of FD nodes 116-Examiner's annotated Fig 17F, Fig 17G, [0048] L1-2).
Regarding claim 27, Sze00 and Lee93 combination discloses all the elements of claim 24, as noted above.
Sze00 further discloses a method for forming an image sensor
wherein the forming of the trench isolation structure comprises: performing an additional etch into the semiconductor substrate from an opposite side of the semiconductor substrate as the pair of gate electrodes (etching substrate 104 to form trench 106 from the opposite side of the electrodes 112-Step 1818-Fig 18, [0150], Fig 16R, [0153] L44-48),
wherein the additional etch forms a trench exposing the dielectric structure and spaced from the pair of floating diffusion nodes (Trench 106 exposing Dielectric structure middle 140 and spaced from the pair of FD nodes 116-Examiner's annotated Fig 17K).
Regarding claim 30, Sze00 and Lee93 combination discloses all the elements of claim 24, as noted above.
Sze00 further discloses a method for forming an image sensor
wherein the dielectric structure blocks dopants from entering the semiconductor substrate at the boundary region during the doping (the mask blocks dopants from entering the substrate 104 at the boundary region between the FD nodes 116-[0090] L 6-11).
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Claim(s) 31, 34, 37, 41-43- is/are rejected under 35 U.S.C. 103 as being unpatentable over Sze et al. (US 20200176500 A1 from IDS-Sze00). In view of Hung et al. (US 20210210532 A1-Hung32), and further in view of Cheng et al. (US 20220367535 A1-Cheng35).
Regarding claim 31, Sze00 discloses a method for forming an image sensor (Abstract L3), the method comprising:
forming a pair of photodetectors (Forming two photodetectors 108-Fig 1, [0153] L 3-4) bordering in a semiconductor substrate (neighboring so bordering in a semiconductor substrate-[0153] L3-4);
doping the semiconductor substrate (doping substrate 104-[0078], [0041], [0080], [0040]) to form a well (shallow well 208 same doping type as 104b, 104b is P-type-[0078], Fig 16A) between and bordering the pair of gate electrodes and spaced from the pair of photodetectors (p-well 208 between and bordering gate electrodes 112 and spaced from photosensitive regions 104c-Examiner's annotated Fig 17F, [0078]);
forming a pair of gate electrodes respectively overlying the pair of photodetectors (forming pair of gate electrodes 112 overlying respectively overlying the pair of photodetectors 108/104c-forming two transfer gates 110 with gate electrodes 112-Fig 1, [0153] L5-6, [0029] L2-4)
depositing a dielectric layer overlying the pair of gate electrodes and the well region (Depositing the dielectric layer 140 over substrate first side/top side 104, first/second transfer gates 110 Left/Right and well region 208-Fig 16H,[0045] L1-8);
patterning the dielectric layer to form a dielectric structure between and spaced from the pair of gate electrodes (using patterned masking layer 1620, performing an etching process on dielectric layer 140 according to patterned masking layer 1620 to form dielectric structure middle 140/1620-[0105] L1-5, Examiner's annotated Fig 17F);
doping the semiconductor substrate with the dielectric structure in place to form a pair of floating diffusion nodes respectively bordering the pair of gate electrodes in the well region and separated from each other by a portion of well region masked by the dielectric structure (Doping the substrate 104 to form a pair of FD nodes 116 closed to gate electrodes 112 in the well 208 separated by a well region 208 masked by dielectric structure middle 140 - Examiner's annotated Fig 17F, [0090]); and
forming a pair of contact vias (Etching so forming two/a pair of contact vias 1622-Examiner's annotated Fig 17F, [0105] L5-7) extending respectively to the pair of floating diffusion nodes with the dielectric structure in place (extending to FD nodes 116 with Dielectric structure middle 140/1620 in place-[0105] L5-7, Examiner's annotated Fig 17F).
Sze00 does not disclose a method for forming an image sensor comprising
forming a pair of gate electrodes respectively on opposite sides of the well region;
wherein the pair of contact vias are formed spaced from the dielectric structure,
which is entirely formed before the pair of floating diffusion nodes are formed.
Hung32 teaches a method for forming an image sensor
forming a pair of gate electrodes respectively on opposite sides of the well region (Forming a pairs of electrodes 1102 respectively on opposite sides of the well region 202-Fig 11, Fig 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method for forming an image sensor of Sze00 as taught by Hung32 for the purpose of having high optical and electrical isolation between photodetectors (Hung32:[0021] L20-21).
Hung32 does not teach a method for forming an image sensor
wherein the pair of contact vias are formed spaced from the dielectric structure,
which is entirely formed before the pair of floating diffusion nodes are formed.
Cheng35 teaches a method for forming an image sensor
wherein the pair of contact vias are formed spaced from the dielectric structure (pair of contact vias 132 over 115 formed spaced from dielectric structure 112-Fig 15),
which is entirely formed before the pair of floating diffusion nodes are formed (dielectric structure 112 entirely formed before the pair of floating diffusion nodes 115-Fig 13, Fig 14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method for forming an image sensor of Sze00 in view of Hung32, as taught by Cheng 35 for the purpose of improving the number of white pixels, and/or dark current without impairing device performance (Cheng35:[0020]).
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Regarding claim 32, Sze00, Hung32, and Cheng35 combination discloses all the elements of claim 31, as noted above.
Sze00 further discloses a method for forming an image sensor
wherein the patterning forms a pair of sidewall spacers (Sidewall spacers formed by patterned ILD 140-Examiner's annotated Fig 17F bis) concurrently with the dielectric structure (sidewalls/portions of 140 and dielectric structure/middle portion of 140 are formed during the same patterning of layer 140 and formation of vias 1622-Examiner's annotated Fig 17F, [0130] L 3-7), and
wherein the pair of sidewalls spacers are respectively on sidewalls of the pair of gate electrodes and the dielectric structure is between and spaced from the pair of sidewall spacers (Pair of sidewalls /portions of 140 on sidewalls of the electrodes 112, and dielectric structure/middle portion of 140/1620 is between and spaced from the sidewalls/portions of 140-Examiner's annotated Fig 17F).
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Regarding claim 34, Sze00, Hung32, and Cheng35 combination discloses all the elements of claim 31, as noted above.
Sze00 further discloses a method for forming an image sensor
wherein the pair of floating diffusion nodes have a doping type opposite a doping type of the well region (the well region 208 has an opposite doping types as the floating nodes 116-[0041] L 14-16).
Regarding claim 37, Sze00, Hung32, and Cheng35 combination discloses all the elements of claim 31, as noted above.
Sze00 further discloses a method for forming an image sensor
wherein the dielectric structure comprises silicon nitride (Dielectric structure /middle portion 140/1620 is silicon nitride-[0036] L5-7) .
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Regarding claim 41, Sze00, Hung32, and Cheng35 combination discloses all the elements of claim 31, as noted above.
Sze00 further discloses a method for forming an image sensor
wherein the pair of gate electrodes are formed separated from the semiconductor substrate by individual gate dielectric layers, (the pair of gate electrodes 110 and 112 are formed separated from the semiconductor substrate 104 by individual gate dielectric layers 114 left and 114 right-Fig 17F bis)
which are spaced from the well region (gate electrodes 110 and 112, and their associated gate dielectric layer Left 114 and Right 114 are spaced from the well region 208-Fig 17Fbis).
Regarding claim 42, Sze00, Hung32, and Cheng35 combination discloses all the elements of claim 41, as noted above.
Sze00 further discloses a method for forming an image sensor
wherein the pair of gate electrodes have individual bottom surfaces inset into the semiconductor substrate and separated by a first separation and further have individual top surfaces separated by a second separation less than the first separation (Pair of gate electrodes 112 Left/Right with individual bottom surfaces into substrate 104 separated by a first horizontal distance, and further having top surfaces separated by a second horizontal distance. The distances are represented with dashed arrows-Fig 17F Bis), and
wherein the well region has a pair of outer sidewall boundaries facing the pair of gate electrodes and separated by a third separation that is closer to the second separation than to the first separation.
(The well region 208 in the middle has two sidewall boundaries/spacer 212 facing the pair of gate electrodes 112, separated by a third horizontal distance, in closer proximity to the second horizontal distance than to the first horizontal distance-Fig 17F Bis).
Regarding claim 43, Sze00, Hung32, and Cheng35 combination discloses all the elements of claim 41, as noted above.
Sze00 further discloses a method for forming an image sensor further comprising:
forming a trench isolation structure extending through the semiconductor substrate and the well region to the dielectric structure after the forming of the pair of contact vias (Forming trench isolation structure 106 extending through the substrate 104 and the well region 208 to the dielectric structure middle 140 after forming the pair of contact vias of the layer 138-Fig 16 Q, Examiner’s annotated Fig 16R),
wherein the trench isolation structure is between and spaced from the pair of floating diffusion nodes (the trench isolation structure 106 is between and spaced from the pair of floating diffusion nodes 116 Left/Right-Examiner’s annotated Fig 16R) .
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Allowable Subject Matter
Claims 38-40 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 38, the prior art of record does not teach or suggest a method for forming an image sensor namely “wherein the etch completely clears the dielectric layer from the individual top surfaces and concurrently forms the dielectric structure and the pair of sidewall spacers".
References such as Lee et al. (US 20180130834 A1-Lee34), in view of Hung et al. (US 20210210532 A1-Hung32), in view of Sze et al. (US 20200176500 A1 from IDS-Sze00), teaches a method for forming an image sensor but does not teach or suggest a method for forming an image sensor, namely “wherein the etch completely clears the dielectric layer from the individual top surfaces and concurrently forms the dielectric structure and the pair of sidewall spacers", in combination with other claimed elements.
Regarding claim 40, the prior art of record does not teach or suggest a method for forming an image sensor namely “wherein the dielectric structure has a cross-shaped top geometry at a boundary between the pairs of photodetectors".
References such as Lee et al. (US 20180130834 A1-Lee34), in view of Hung et al. (US 20210210532 A1-Hung32), in view of Sze et al. (US 20200176500 A1 from IDS-Sze00), teaches a method for forming an image sensor but does not teach or suggest a method for forming an image sensor, namely “wherein the dielectric structure has a cross-shaped top geometry at a boundary between the pairs of photodetectors", in combination with other claimed elements.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Claims 44 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 44, the prior art of record does not teach or suggest a method for forming an image sensor namely “wherein the dielectric structure has a cross-shaped top geometry at a boundary between the pairs of photodetectors".
References such as Lee et al. (US 20180130834 A1-Lee34), in view of Hung et al. (US 20210210532 A1-Hung32), in view of Sze et al. (US 20200176500 A1 from IDS-Sze00), teaches a method for forming an image sensor but does not teach or suggest a method for forming an image sensor, namely “wherein the dielectric structure has a cross-shaped top geometry at a boundary between the pairs of photodetectors", in combination with other claimed elements.
The balance of the claims are allowable for at least the above-stated reasons.
Claims 18-20, and 22-23 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 18, the prior art of record does not teach or suggest a method for forming an image sensor namely “wherein the dielectric structure has a cross-shaped top geometry at a boundary between the first and second photodetectors".
References such as Lee et al. (US 20180130834 A1-Lee34), in view of Hung et al. (US 20210210532 A1-Hung32), in view of Sze et al. (US 20200176500 A1 from IDS-Sze00), teaches a method for forming an image sensor but does not teach or suggest a method for forming an image sensor, namely “wherein the dielectric structure has a cross-shaped top geometry at a boundary between the first and second photodetectors", in combination with other claimed elements.
The balance of the claims are allowed for at least the above-stated reasons.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments see pages 8-11 of Remarks, filed on 01/27/2026 with respect to the 35 U.S.C 103 rejection of claim 18 have been fully considered and are persuasive. The 35 U.S.C 103 rejection of claim 18 has been withdrawn.
Therefore, claim 18 is allowed and claims 19-20 and 22-23 are allowed at least for their dependencies.
Applicant’s arguments see pages 8-13 of Remarks, filed on 1/27/2026 with respect to the 35 U.S.C 102 rejection of claims 24-27 and 30 have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections above.
Claim 24 has been amended to further define the claimed subject matter see pages 4-5 of Amendments to Claims, filed on 01/27/2026.
Amended claim(s) 24 is rejected under rejected under 35 U.S.C. 103 as being unpatentable over Sze et al. (US 20200176500 A1 from IDS-Sze00). In view of Lee et al. (US20200212093A1-Lee93), as described above.
Therefore, claims 24-27 and 30 stand rejected under 35 U.S.C. 103 as being unpatentable over Sze et al. (US 20200176500 A1 from IDS-Sze00). In view of Lee et al. (US20200212093A1-Lee93).
Applicant’s arguments see pages 8-13 of Remarks, filed on 1/27/2026 with respect to the 35 U.S.C 102 rejection of claims 31, 37, and 41-43 have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections above.
Claim 31 has been amended to further define the claimed subject matter see pages 5-6 of Amendments to Claims, filed on 01/27/2026.
Amended claim(s) 31 is rejected under rejected under 35 U.S.C. 103 as being unpatentable over Sze et al. (US 20200176500 A1 from IDS-Sze00). In view of Hung et al. (US 20210210532 A1-Hung32), and further in view of Cheng et al. (US 20220367535 A1-Cheng35), as described above.
Therefore, claims 31, 34, 37 and 41-43 stand rejected under 35 U.S.C. 103 as being unpatentable over Sze et al. (US 20200176500 A1 from IDS-Sze00). In view of Hung et al. (US 20210210532 A1-Hung32), and further in view of Cheng et al. (US 20220367535 A1-Cheng35).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang et al. (US 20230261021 A1-Wang21) teaches a method for forming an image sensor comprising forming a pair of gate electrodes, spacers, floating nodes, a trench isolation structure(a pair of gate electrodes 110, spacers 702, floating nodes 106, a trench isolation structure 130-Fig 20).
Lin et al. (US20120099361A1-Lin61) teaches a fabricating method of memory cell wherein the etch forms the pair of sidewall spacers with a height greater than a height of the dielectric structure (the pair of spacers 320 with a height greater than the height of the dielectric structure 324a-Fig 6C).
Weng et al. (Feasible approach for processes integration of CMOS transistor gate/side-wall spacer patterning fabrication, Microelectronics Reliability, Volume 50, Issue 12, 2010-NPLWeng10) teaches a fabricating method for spacers wherein the etch forms the pair of sidewall spacers from portions of the dielectric layer having individual top surfaces completely exposed to an etchant of the etch (After the offset spacer deposition of a silicon nitride film, the etching of individual top surfaces of the offset spacer layer which are completely exposed to an etchant of the etch, forms the pair of spacers-Fig 4 (b), Fig 4 (c)) for the purpose of offsetting ion implantation profiles from the edge of the gate (NPLWeng10: Abstract).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/
Examiner, Art Unit 2812 03/06/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812