DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 24-33, 35-37 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 24, the limitation “wherein the second etch process comprises performing a second etch at a second power level different from the first power level,” does not appear to have adequate support in the originally filed disclosure. Specifically, while the disclosure provides ranges which might result in some instances of different powers, the scope of the claim covers any and all values which are not equal. Accordingly, the full scope of the claim is not supported by the original disclosure. It is noted that applicant appears to be conflating the disclosed relationship of “the second etch process includes performing two or more etch processes having different power levels from one another” (see [0095] of published version of applicant’s disclosure) and the claimed relationship between the “first etch” (understood to be a part or whole of first etch process recited in [0055]) and the “second etch” (understood to be a part or whole of second etch process recited in [0060]).
Regarding claim 29, the limitation “wherein the third power level is less than the first power level,” does not appear to have adequate support in the originally filed disclosure. Specifically, while the disclosure provides ranges which might result in some instances of the powers claimed, the scope of the claim covers any and all values where the values are as claimed. Accordingly, the full scope of the claim is not supported by the original disclosure. It is noted that applicant appears to be conflating the disclosed relationship of the first, second, and third power of the second etch process (described in [0060] of published version of applicant’s disclosure) and the claimed relationship between the “first etch” (understood to be a part or whole of first etch process recited in [0055]) and the “second etch” (understood to be a first part of second etch process recited in [0060]), and the “third etch” (understood to be a second part of second etch process recited in [0060]). A
Regarding claim 31, the limitation “wherein the etching process comprises: performing a first etch at a first power level on the second dielectric structure; and performing a second etch at a second power level on the etch stop structure, wherein the second power level is less than half of the first power level,” does not appear to have adequate support in the originally filed disclosure. Specifically, while some power values for the first and second etches (as best understood to be corresponding to the first etch process and the second etch process, respectively), there is no specific disclosure of “less than half,” or any given endpoints which would provide proper support for the range represented by “less than half.
Regarding claim 33, the limitation “wherein a thickness of the insulator layer is less than a thickness of the third dielectric layer,” does not appear to have adequate support in the originally filed disclosure. Specifically, there does not appear to be any disclosure of a relationship between the thicknesses of the two layers. It is noted that drawings are not taken as to scale.
Regarding claim 35, the limitation “a thickness of the etch stop structure is less than a thickness of the third dielectric layer,” does not appear to have adequate support in the originally filed disclosure. Specifically, there does not appear to be any disclosure of thicknesses of the various layers. It is noted that drawings are not taken as to scale.
Regarding claim 37, the limitation “wherein the upper dielectric structure comprises a first dielectric layer, a third etch stop layer over the first dielectric layer, and a second dielectric layer over the third etch stop layer, wherein the first plasma etch removes portions of the second dielectric layer and stops on the third etch stop layer, wherein the second plasma etch removes the plurality of plugs from over the etch stop structure and the third plasma etch removes portions of the etch stop structure,” does not appear to have support in the originally filed disclosure. Specifically, there is no disclosure of stopping on third etch stop layer, understood to correspond with disclosed element 214.
Note the dependent claims do not cure the deficiencies of the claims on which they depend.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-17, 19-33, and 35-37 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 16, 24 and 28, the limitation “to expand (the) heights of the plurality of openings,” is unclear as to how many heights each opening is required to have.
Regarding claim 24, the limitation “forming a plurality of conductive interconnect structures in the plurality of openings,” is unclear as to if it requires plural conductive interconnects in each opening or a single conductive interconnect in each opening. It is noted the additional recitation of “wherein an individual conductive interconnect structure…” does not make the limitation definite, as it merely recites that one interconnect is in one respective opening, and does not add clarity as to what the relationship each interconnect is.
Regarding claim 24, the limitations “performing a first etch process…” “performing a second etch process…comprising performing a first etch at a first power level…” “performing a third etch process…comprising performing a second etch at a second power level different from the first power level” are unclear. Specifically, it is unclear how the “first etch” corresponds to the “first etch process,” and as to how the “second etch” corresponds to the “second etch process.” Further, due to a large number of etches disclosed in the specification and a lack of antecedent basis in the specification with the claimed limitations, it is unclear as to which of the disclosed etches are intended to correspond to the “first etch process,” the “first etch,” the “second etch process,” the “second etch,” and the “third etch process.” Further, the first and second etches, which appear to possibly correspond to the “first etch process” and the “second etch process” of the disclosure, are disclosed as each comprising multiple etch powers, and it is therefore unclear which of the etches within the first and second etch processes are intended or required to have the claimed relationship, or if applicant intends for the relationship to be required for the entirety of the first etch/first etch process relative to the entirety of the second etch/second etch process.
Regarding claims 28 and 29, the limitation “the third etch process further comprises performing a third etch at a third power level, wherein the third etch expands the heights of the plurality of openings through the first etch stop layer, the insulator layer and the second etch stop layer,” and “wherein the third power level is less than the first power level,” are unclear as to how they are related to the recitations of claim 24. Specifically, due to a large number of etches disclosed in the specification and a lack of antecedent basis in the specification with the claimed limitations, it is unclear as to which of the disclosed etches are intended to correspond to the recited etches. Further, the first and second etches, which appear to possibly correspond to the “first etch process” and the “second etch process” of the disclosure, are disclosed as each comprising multiple etch powers, and it is therefore unclear which of the etches within the first and second etch processes are intended or required to have the claimed relationship, or if applicant intends for the relationship to be required for the entirety of the first etch/first etch process relative to the specific etches of the second etch/second etch process.
Regarding claim 27, the limitation “a width of a respective upper portion of the plurality of openings,” is unclear as to what the “respective” is supposed to indicate.
Regarding claim 31, the limitation “wherein the etching process comprises: performing a first etch at a first power level on the second dielectric structure; and performing a second etch at a second power level on the etch stop structure, wherein the second power level is less than half of the first power level,” is unclear as to what is required by the claim. Specifically, due to a large number of etches disclosed in the specification and a lack of antecedent basis in the specification with the claimed limitations, it is unclear as to which of the disclosed etches are intended to “first etch” and “second etch” are intended to correspond. Further, the first and second etches, which appear to possibly correspond to the “first etch process” and the “second etch process” of the disclosure, are disclosed as each comprising multiple etch powers, and it is therefore unclear which of the etches within the first and second etch processes are intended or required to have the claimed relationship, or if applicant intends for the relationship to be required for the entirety of the first etch/first etch process relative to the entirety of the second etch/second etch process.
Regarding claim 31, the limitation “forming a plurality of conductive interconnects in the plurality of openings,” is unclear as to if it requires plural conductive interconnects in each opening or a single conductive interconnect in each opening. It is noted the additional recitation of “wherein an individual conductive interconnect…” does not make the limitation definite, as it merely recites that one interconnect is in one respective opening, and does not add clarity as to what the relationship each interconnect is.
Regarding claim 37, the limitation “wherein the upper dielectric structure comprises a first dielectric layer, a third etch stop layer over the first dielectric layer, and a second dielectric layer over the third etch stop layer, wherein the first plasma etch removes portions of the second dielectric layer and stops on the third etch stop layer, wherein the second plasma etch removes the plurality of plugs from over the etch stop structure and the third plasma etch removes portions of the etch stop structure,” is unclear as to what is required by “stops.”
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 16-17, 19-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2022/0285210; herein “Lin”) in view of Kim et al. (US 2023/0120474; herein “Kim”).
Regarding claim 16, Lin teaches in Figs. 1A-J and related text a method for forming an integrated chip, comprising:
forming a lower dielectric structure (e.g. 102, see [0017]) over a semiconductor substrate (100, see [0016]);
forming a plurality of first conductive wires (106, see [0018]) within the lower dielectric structure;
forming an etch stop structure (110, see [0022]) over the plurality of first conductive wires, wherein the etch stop structure comprises a first etch stop layer (112A/112B), a first insulator layer (114), and a second etch stop layer (116);
forming an upper dielectric structure (120, see [0035]) over the etch stop structure;
performing a first etch process on the upper dielectric structure to form a plurality of openings in the upper dielectric structure, wherein the first etch stop process exposes an upper surface of the etch stop structure (see Fig. 1F); and
performing a second etch process on the upper dielectric structure and the etch stop structure to expand the plurality of openings, wherein the second etch process etches through the etch stop structure and exposes upper surfaces of the first conductive wires (see Figs. 1G-1I).
Lin does not explicitly disclose
wherein the second etch process comprises performing a first plasma etch at a first power level, a second plasma etch at a second power level, and a third plasma etch at a third power level, wherein the first power level is greater than the second power level and the second power level is greater than the third power level.
In the same field of endeavor, Kim teaches in Fig. 3 and related text a method of forming a semiconductor device including an etch process,
wherein the second etch process comprises performing a first plasma etch at a first power level, a second plasma etch at a second power level, and a third plasma etch at a third power level, wherein the first power level is greater than the second power level and the second power level is greater than the third power level (e.g. in the instance where t2-t3 is a first etch, t3-t4 is a second etch, and t4-t5 is a third etch, see Fig. 3, [0086]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Lin by having the second etch process comprises performing a first plasma etch at a first power level, a second plasma etch at a second power level, and a third plasma etch at a third power level, wherein the first power level is greater than the second power level and the second power level is greater than the third power level, as taught by Kim, in order to improve etching processes for high aspect ratio recesses (see Kim [0003], [0058] at least).
Regarding claim 17, the combined method shows wherein the first etch process comprises performing an initial high powered etch followed by a final low powered etch, wherein the initial high powered etch comprises forming one or more etchants at a fourth power and the final low powered etch comprises forming the one or more etchants at a fifth power less than the first power (Kim: when the ramp down etching process shown in Fig. 3 and related text is applied to the first etch process as well, see Fig. 3 and [0086]).
Regarding claim 19, the combined method wherein the second plasma etch (Lin: see Fig. 1H) is performed after the first plasma etch (see Fig. 1G) and the third plasma etch (see Fig. 1I) is performed after the second plasma etch (see Fig. 1G).
Regarding claim 20, the combined method shows forming a capacitor (see [0016] and [0020]) on the semiconductor substrate, wherein an individual conductive wire of the plurality of first conductive wires (106) is directly electrically coupled to the capacitor (see [0020]).
Regarding claim 21, the combined method shows wherein the first etch stop layer (Lin: 112A/112B) has a first thickness (3 Å to 100 Å, see [0025] and [0030]), the first insulator layer (114) has a second thickness (3 Å to 150 Å, see [0033]), and the second etch stop layer (116) has a third thickness (3 Å to about Å, see [0036]), wherein the second thickness is less than the first thickness and the third thickness (e.g. in the instance that 114 is at the lower end of the disclosed range and 112 and 116 are at the higher end of the disclosed ranges).
Note that the ranges disclosed by Lin overlap the claimed ranges. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art,” a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)). Additionally, one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the thickness to be a result effective variable affecting the ability to act as an etch stop layer, the electrical characteristics such as the parasitic capacitance between wiring layers, and mechanical characteristics such as adhesion between layers. Thus, it would have been obvious to modify the device of Lin to have the thicknesses within the claimed ranges in order to achieve desired balance the various affected characteristics, and since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art. Furthermore, it would have been obvious to modify the device of Lin to have the claimed relative thicknesses for the purpose of choosing from a finite number of identified, predictable solutions (i.e. the same, greater than, or less than), with a reasonable expectation of success (KSR International Co. v. Teleflex Inc. 82 USPQ2d 1385 (2007)).
Regarding claim 22, the combined method shows forming a plurality of conductive vias and a plurality of second conductive wires in the plurality of openings (Lin: e.g. the via and horizontal portions of 142, respectively, see [0045]), wherein the conductive vias extend through the etch stop structure to contact the plurality of first conductive wires.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Kim, as applied to claim 16 above, and further in view of Goldberg et al. (US 2004/0002210; herein “Goldberg”).
Regarding claim 23, Lin does not explicitly disclose forming a plurality of plugs in the plurality of openings before performing the second etch process, wherein the plurality of plugs contacts the second etch stop layer and is vertically offset from the first insulator layer.
In the same field of endeavor, Goldberg teaches in Fig. 2-8 and related text a method of making a semiconductor device comprising forming a plurality of plugs (61, see [0020]) in the plurality of openings before performing the second etch process (see Figs. 6-7), wherein the plurality of plugs contacts the second etch stop layer (42, see [0020]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Lin by forming a plurality of plugs in the plurality of openings before performing the second etch process, wherein the plurality of plugs contacts the second etch stop layer, as taught by Goldberg, in order to prevent damage to underlying dielectric layers and to prevent the width of the recess from increasing (see Goldberg [0020]). Note that the limitation “the plurality of plugs…is vertically offset from the first insulator layer” is taught by the combination of the plugs contacting the top surface of the etch stop layer, as shown by Goldberg, and the insulator layer being vertically offset from the top surface of the etch stop layer, as shown by Lin.
Claim(s) 31-33 and 35-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Yu et al. (US 2010/0308463; herein “Yu”) and Kim.
Regarding claim 31, Lin teaches in Figs. 1A-J and related text a method for forming an integrated chip, comprising:
forming an electronic device (see [0016] and [0020]) over a substrate (100, see [0016]);
depositing a first dielectric structure (e.g. 102, see [0017]) over the electronic device;
forming a first plurality of conductive wires (106, see [0018]) in the first dielectric structure wherein the first plurality of conductive wires comprises a first conductive wire electrically coupled to the electronic device (see [0020]);
forming an etch stop structure (110, see [0022]) over the first plurality of conductive wires, wherein the etch stop structure comprises a first etch stop layer (112A/112B, see [0023] and [0027]), an insulator layer (114, see [0032]) over the first etch stop layer, and a second etch stop layer (116, see [0033]) over the insulator layer, wherein a material of the insulator layer (e.g. SiO, see [0032]) and is different from a material of the first etch stop layer (e.g. AlN, see [0024]) and a material of the second etch stop layer (e.g. AlO, see [0035]);
depositing a second dielectric structure (120, see [0035]) over the etch stop structure;
performing an etching process (see Figs. 1F-I) on the second dielectric structure and the etch stop structure to form a plurality of openings in the second dielectric structure and the etch stop structure, wherein the etching process exposes an upper surface of individual conductive wires of the first plurality of conductive wires, wherein the etching process comprises:
performing a first etch at a first power level on the second dielectric structure; and
performing a second etch at a second power level on the etch stop structure (in a first example interpretation, the first etch is shown in Fig. 1F and the second etch is shown in Figs. 1G-I; in a second example interpretation the first etch is shown in Fig. 1G and the second etch is shown in Fig. 1H-I);
forming a plurality of conductive interconnects (142, see [0045]) in the plurality of openings, wherein an individual conductive interconnect of the plurality of conductive interconnects is formed in a corresponding opening of the plurality of openings.
Lin does not explicitly disclose
wherein the first dielectric structure comprises a first dielectric layer over the substrate, a lower etch stop layer over the first dielectric layer, and a second dielectric layer over the lower etch stop layer;
forming the first plurality of conductive wires in the second dielectric layer and the lower etch stop layer;
wherein the second dielectric structure comprises a third dielectric layer over the etch stop structure, an upper etch stop layer over the third dielectric layer, and a fourth dielectric layer over the upper etch stop layer;
wherein the second power level is less than half of the first power level.
in the same field of endeavor, Yu teaches in Fig. 1A-E and related text
wherein the first dielectric structure comprises a first dielectric layer (111, see [0063]) over the substrate, a lower etch stop layer (113, see [0065]) over the first dielectric layer, and a second dielectric layer (115, see [0066]) over the lower etch stop layer;
forming the first plurality of conductive wires (124/125, see [0069]) in the second dielectric layer and the lower etch stop layer;
wherein the second dielectric structure comprises a third dielectric layer (111 in additional layer of metallization, see [0070]) over the etch stop structure (109 in the additional layer of metallization, see [0063]), an upper etch stop layer (113 in the additional layer of metallization) over the third dielectric layer, and a fourth dielectric layer (115 in the additional layer of metallization) over the upper etch stop layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Lin by having the first dielectric structure comprises a first dielectric layer over the substrate, a lower etch stop layer over the first dielectric layer, and a second dielectric layer over the lower etch stop layer; forming the first plurality of conductive wires in the second dielectric layer and the lower etch stop layer; and having the second dielectric structure comprises a third dielectric layer over the etch stop structure, an upper etch stop layer over the third dielectric layer, and a fourth dielectric layer over the upper etch stop layer, as taught by Yu, in order to provide a multilayer metallization dual damascene structure for BEOL interconnects with improved electromigration properties (see Yu [0003]).
Note that the ranges disclosed by Lin overlap the claimed ranges. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art,” a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)). Additionally, one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the thickness to be a result effective variable affecting the ability to act as an etch stop layer, the electrical characteristics such as the parasitic capacitance between wiring layers, and mechanical characteristics such as adhesion between layers. Thus, it would have been obvious to modify the device of Lin to have the thicknesses within the claimed ranges in order to achieve desired balance the various affected characteristics, and since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art. Furthermore, it would have been obvious to modify the device of Lin to have the claimed relative thicknesses for the purpose of choosing from a finite number of identified, predictable solutions (i.e. the same, greater than, or less than), with a reasonable expectation of success (KSR International Co. v. Teleflex Inc. 82 USPQ2d 1385 (2007)).
The limitation “wherein the second power level is less than half of the first power level” is taught by Kim in substantially the same manner and for the same reasons as applied to claims 16, 24 and 29 above (note that one can choose any point during the respective etches such that the claimed relationship is met).
Further, it is noted that one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the etch power to be a result effective variable affecting the aspect ratio of the recess (see Kim and discussions of power affecting the aspect ratio, [0059]-[0076]). Thus, it would have been obvious to modify the device of Lin to have each of the first and second power levels such that the relative power is within the claimed range in order to achieve an improved etch recess of high aspect ratio, and since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Regarding claim 32, the combined method shows a dielectric constant of the insulator layer (Lin: 114, SiO) is less than dielectric constants of the first and second etch stop layers (112A, AlN and 116, AlO, see [0024], [0032], [0035]).
Regarding claim 33, the combined method shows wherein the thickness of the insulator layer (Lin: 114; Yu: a portion of 109) is less than a thickness of the third dielectric layer (Yu: 111) (Lin: see [0025], [0030], [0033], and [0036]; Yu: see [0077]-[0078]).
Regarding claim 35, the combined method shows wherein a thickness of the etch stop structure (Lin: 112/114/116) is less than a thickness of the third dielectric layer (Lin: see [0025], [0030], [0033], and [0036]; Yu: see [0077]-[0078]).
Regarding claim 36, the wherein the first etch stops on the etch stop structure and the second etch stops on the first plurality of conductive wires (in the first interpretation, where the first etch is shown in Fig. 1F and the second etch is shown in Figs. 1G-I).
Response to Arguments
Applicant's arguments filed 2/2/2026 have been fully considered but they are not persuasive.
Applicant argues (page 9-10) that Lin in view of Kim does not teach or suggest “the second etch process comprises performing a first plasma etch at a first power level, a second plasma etch at a second power level, and a third plasma etch at a third power level, wherein the first power level is greater than the second power level and the second power level is greater than the third power level,” because the time varying RF power is “not analogous to performing three discrete plasma etches at different power levels,” as recited in claim 16.
In response, the examiner disagrees. Specifically, it is noted that the features upon which applicant relies (i.e., “discrete plasma etches”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Further, it is noted that the only disclosure related to the first, second, and third etches of the second etch process is that they are at different power levels and that they are performed “immediately” after one another. It is accordingly unclear what applicant even intends by the processes being “discrete,” which is not shown by the reference.
Applicant argues (page 10-11) that Lin in view of Kim does not teach or suggest the invention of claim 16 because Lin discloses that mask 122B and layer 116 are removed by wet etching, which would not be modified to the plasma etch of Kim.
In response, the examiner disagrees. Specifically, it is first noted that the second etch process merely needs to comprise the plasma etch steps. Therefore, even if subsequent etching steps occur during or after the second etch process, the plasma etch portion of the second etch process is taught by the combination. Further, it is that Lin teaches “such as wet etching,” which is not teaching away from plasma etch, and any benefits of the plasma etch process of Kim would be motivation to perform the etch process by plasma etch.
Applicant argues (page 13-15) that the prior art does not teach or suggest the invention of claim 31 because Kim does not show “the second power level is less than half the first power level” and that optimization is irrelevant because the claim does not recite numerical values. Applicant further argues that Kim does is silent as to the relationship of power level between two discrete etches, and therefore does not show it is a result-effective variable.
In response, the examiner disagrees. First, as discussed above, “discrete” etches are neither recited in the current claims nor clearly defined or supported in the original disclosure. Kim clearly establishes a relationship between the variable of power level of the etches and the effects on aspect ratio. Applicant’s claim, while not containing “numerical values” per se, does indeed recite a range in the sense that the power levels are related in such a way that P2<0.5 P1. Further, it is readily recognized that the claimed relationship can be achieved merely by increasing or decreasing each of the first and second power levels an appropriate amount, i.e. optimization.
Applicant’s remaining arguments have been considered but are moot in view of the new grounds of rejection presented above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896 3/20/2026