DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous rejection: claims 15 through 34 rejected.
Current rejection: claims 15-17,20-21,24,27-30 and 32-41 rejected.
Claim Objections
Claim 16, 27, and 41 objected to because of the following informalities:
Claim 16 recites “bonding that pads have” in line 2. The examiner suggests “bonding pads that have”.
Claim 27 recites “two thirds or less an area” in line 3. The examiner suggests “or less than an area”
Claim 41 recites “the first wire equal the distance” in line 2. The examiner suggests, “the first wire equals the distance”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 33, 34, and 39 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 33 recites the limitation "the first bonding pads" in lines 1 and 2. There is insufficient antecedent basis for this limitation in the claim. The precedent element recites “a first bonding pad”.
Claim 33 recites the limitation "the second bonding pads" in line 2. There is insufficient antecedent basis for this limitation in the claim. The precedent element recites “a second bonding pad”.
Claim 33 recites the limitation "the first surfaces" in line 3. There is insufficient antecedent basis for this limitation in the claim. The precedent element recites “a first surface”.
Claim 33 recites the limitation "the second surfaces" in line 4. There is insufficient antecedent basis for this limitation in the claim. The precedent element recites “a second surface”.
Claim 34 depends from and incorporates claim 33.
Claim 39 recites the limitation "those that are narrower" in line 2. There is insufficient antecedent basis for this limitation in the claim. There is no precedent suggestion that any wires are narrower. The applicant may have intended, “
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15, 16, 17, 35, 37, 38, 39, and 40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yanagita (US 2015/0179691) in view of Ichikawa (US 2013/0092822) in view of Furuhashi (US 2019/0386052).
Regarding claim 15
Yanagita teaches a method comprising: forming a [conductive] interconnect structure (fig 9:31; [para 0097])on a first substrate (fig 9:3; [para 0095]), wherein: the [conductive] interconnect structure (fig 9:31; [para 0097])comprises wires in a stack of [conductive] layers (fig 5,9:33,56,55; [para 0078,0097]) including an uppermost [conductive] layer (fig 9:56,55; [para 0078,0097]), and a first bonding pad (fig 9:35; [para 0056]) having a first oblong surface (fig 4a:35; [para 0065]) in a bonding layer (fig 9[0060]) over the uppermost [conductive] layer (fig 9:56,55; [para 0078,0097]);
the uppermost [conductive] layer (fig 9:56,55; [para 0078,0097]) comprises wires (fig 9:55; [para 0078,0097]) that are electrically isolated from the first bonding pad (fig 9:35; [para 0056]), including two wires (fig 9:55; [para 0078,0097]) that are closest to the first bonding pad (fig 9:35; [para 0056]); and two wires (fig 9:55; [para 0078,0097]) that are closest to the first bonding pad (fig 9:35; [para 0056]) […]; forming a second bonding pad (fig 9:45; [para 0056,0065]) having a second oblong surface (fig 4a) on a second substrate (fig 9:9; [para 0095]); aligning the first substrate (fig 9:3; [para 0095]) and the second substrate (fig 9:9; [para 0095]) so that the first oblong surface lies across the second oblong surface (fig 4a; [para 0065]); and forming a bond ([para 0044]) between the first bonding pad (fig 9:35; [para 0056]) and the second bonding pad (fig 9:45; [para 0056]).
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Yanagita does not teach that the closest wire is parallel to a direction in which the first oblong surface of the bonding pad is longest.
Ichikawa teaches and the two wires that are closest to the first bonding pad (fig 1,2:105 9:35; [para 0056]) are parallel to a direction (fig 1:107; [para 0034]) in which the first oblong surface is longest (fig 1; [para 0035]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the bonding pad to be parallel to the closest wires in order to enable a shorter pixel pitch and thereby enable a greater number4 of pixels (Ichikawa; [para 0041]).
Yanagita does not teach the conductive layers comprise metal.
Furuhashi teaches conductive interconnect structures (fig 3:35a,36,71; [para 0063]) formed of metal ([para 0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form conductive interconnect structure from metal due to the high conductivity of metal
Regarding claim 16.
Yanagita in view of Ichikawa in view of Furuhashi teaches the method of claim 15 above.
Yanagita does not teach an array of pads
Ichikawa teaches the first bonding pad (fig 2:106; [para 0038]) is one in a first array of first bonding pads (fig 7; [para 0104]) that have first oblong surfaces (fig 2) all having the same orientation (fig 7); the second bonding pad (fig 2:105; [para 0038]) is one in a second array of second bonding that pads have second oblong surfaces (fig 2); and forming the bond (fig 2:201; [para 0038]) between the first bonding pad (fig 2:106; [para 0038]) and the second bonding pad (fig 2:105; [para 0038]) forms bonds (fig 7:713; [para 0104]) between first bonding pads in the first array and respective second bonding pads in the second array (fig 7).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of he claimed invention to form the bond pads as part of an array of bond pads so that each photoelectric unit can comprise a separate connection to the controlling transistors and therefore enabling the readout for each pixel (Ichikawa; [para 0098]).
Regarding claim 17.
Yanagita in view of Ichikawa in view of Furuhashi teaches the method of claim 16, further:
Ichikawa teaches the first array and the second array are two-dimensional arrays fig 2,7).
Regarding claim 35.
Yanagita in view of Ichikawa in view of Furuhashi teaches the method of claim 15, further:
Yanagita teaches the two wires (fig 5,9:55; [para 0078]) that are closest to the first bonding pad (fig 9:35; [para 0065]) among those that are electrically isolated from the first bonding pad (fig 9:35; [para 0065]) are ground wires ([para 0078,0097]).
Regarding claim 37.
Yanagita in view of Ichikawa in view of Furuhashi teaches the method of claim 15, further:
Yanagita teaches the uppermost [conductive] layer (fig 9:56,55; [para 0097]) comprises a [conductive] island (fig 9:56; [para 0097]) that is directly beneath and electrically connected to the first bonding pad (fig 9:56; [para 0097]).
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Furuhashi teaches conductive interconnect structures (fig 3:35a,36,71; [para 0063]) formed of metal ([para 0061]).
Regarding claim 38.
Yanagita in view of Ichikawa in view of Furuhashi teaches the method of claim 37, further:
Yanagita teaches the two wires (fig 9:55; [para 0097]) that are closest to the first bonding pad (fig 9:35; [para 0044]) among those that are electrically isolated from the first bonding pad are on opposite sides of the [conductive] island (fig 9:56; [para 0097]).
Furuhashi teaches conductive interconnect structures (fig 3:35a,36,71; [para 0063]) formed of metal ([para 0061]).
Regarding claim 39.
Yanagita in view of Ichikawa in view of Furuhashi teaches the method of claim 38, further:
Yanagita teaches the two wires (fig 9:55; [para 0097]) that are closest to the first bonding pad (fig 9:35; [para 0044]) among those that are narrower than [a conductive] island (fig 5:33; [para 0052]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the conductive island to be wider than the closest wires in order to facilitate the formation and placement of adjacent vias thereby reducing the occurrence of misalignment and improper electrical connection.
Furuhashi teaches conductive interconnect structures (fig 3:35a,36,71; [para 0063]) formed of metal ([para 0061]).
Regarding claim 40.
Yanagita in view of Ichikawa in view of Furuhashi teaches the method of claim 39, further:
Yanagita teaches the method further comprises forming photodiodes (fig 9:PD1,PD2; [para 0045]), transfer gates (fig 9:tra,tr2; [para 0041]), and floating diffusion regions (fig 5,9:FD; [para 0042]) on the first substrate (fig 9:3; [para 0097]), and the [conductive] island (fig 9:56; [para 0097]) is electrically coupled to one of the floating diffusion regions (fig 5,9:FD; [para 0042]).
Furuhashi teaches conductive interconnect structures (fig 3:35a,36,71; [para 0063]) formed of metal ([para 0061]).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yanagita (US 2015/0179691) in view of Ichikawa (US 2013/0092822) in view of Furuhashi (US 2019/0386052) as applied to claim 16, and further in view Chen (US 2019/0123006).
Regarding claim 20.
Yanagita in view of Ichikawa in view of Huruhashi teaches the method of claim 16.
Yanagita teaches the first and second oblong surfaces (fig 4a:45,35; [para 0065]).
Yanagita in view of Ichikawa in view of Furuhashi does not teach the first and second oblong surfaces are elliptical.
Chen teaches the oblong surfaces (110,120) are elliptical.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the oblong surface elliptical in order to avoid the stress concentrations at corners and thereby avoid crack nucleation points.
Claim(s) 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yanagita (US 2015/0179691) in view of Ichikawa (US 2013/0092822) in view of Furuhashi (US 2019/0386052) as applied to claim 15, and further in view of Haneda (US 2022/0384207).
Regarding claim 36.
Yanagita in view of Ichikawa in view of Furuhashi teaches the method of claim 15.
Yanagita teaches the two wires (fig 9:55; [para 0097])) that are closest to the first bonding pad (fig 9:35; [para 0044]) among those that are electrically isolated from the first bonding pad (fig 9:35; [para 0044]) are [connected] to the first substrate (fig 9:3; [para 0097]).
Yanagita in view of Ichikawa in view of Furuhashi does not teach coupling the wires to the substrate.
Haneda teaches ground lines are electrically coupled to the first substrate (not illustrated; [para 0162]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to couple ground line to the substrate in order to provide a grounding voltage to the lines so that the lines are not floating.
Claim(s) 21, 27, 28, and 30 is is/are rejected under 35 U.S.C. 103 as being unpatentable over Yanagita (US 2015/0179691) in view of Furuhashi (US 2019/0386052)
Regarding claim 21.
Yanagita teaches a method, comprising: forming a [conductive] interconnect structure (fig 10:41; [para 0101]) on a first integrated circuit (IC) device (fig 10:9; [para 0101]), wherein: the [conductive] interconnect structure (fig 10:41; [para 0101]) comprises a bonding layer (fig 10:45; [para 0060]) and a [conductive] layer (fig 10:43,53,57; [para 0050,0102]) immediately below the bonding layer (fig 10:45; [para 0060]); the bonding layer comprises a first bonding pad (fig 10:45; [para 0060]); and the [conductive] layer (fig 10:43,53,57; [para 0050,0102]) comprises a first wire (fig 3,10:43; [para 0050]) coupled to the first bonding pad (fig 10:45; [para 0060]) and a second wire (fig 10:57; [para 0102]) that is separate from but next to the first wire (fig 10:43; [para 0050]); forming a second bonding pad (fig 3,10:35; [para 0044]) on a second IC device (fig 10:3; [para 0099]); and bonding the first IC device (fig 10:9; [para 0101]) to the second IC device (fig 10:3; [para 0099]); wherein the first bonding pad (fig 10:45; [para 0060]) is bonded (fig 10; [para 0044]) to the second bonding pad (fig 10:35; [para 0060]) at an interface between the first IC device (fig 10:9; [para 0101]) and the second IC device (fig 10:3; [para 0099]); the first bonding pad (fig 10:45; [para 0060]) is wider than the second bonding pad (fig 10:35; [para 0060]) in a first cross-section (annotated Y,Z) that is perpendicular to the interface (fig 4a,10); the second wire (fig 10:57; [para 0102]) runs parallel to the first cross-section (fig 8,10); and the second bonding pad (fig 4a,10:35; [para 0065]) is wider than the first bonding pad (fig 4a10:35; [para 0060]) in a second cross- section (annotated X,Z) that is perpendicular to the interface and to the first cross-section (annotated Y,Z).
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Yanagita does not teach the conductive layers comprise metal.
Furuhashi teaches conductive interconnect structures (fig 3:35a,36,71; [para 0063]) formed of metal ([para 0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form conductive interconnect structure from metal due to the high conductivity of metal
Regarding claim 27.
Yanagita in view of Furuhashi teaches the method of claim 21, further:
Yanagita teaches shapes and orientations of the first bonding pad (fig 4a,10:45; [para 0065]) and the second bonding pad (fig 4a,10:35; [para 0065]) limit an area of contact between them to two thirds or less an area of a smallest one of the first bonding pad (fig 4a,10:45; [para 0065]) and the second bonding pad (fig 4a,10:35; [para 0065]).
Regarding claim 28.
Yanagita in view of Furuhashi teaches the method of claim 21, further:
Yanagita teaches an area of contact between the first bonding pad (fig 4a,10:45; [para 0065]) and the second bonding pad (fig 4a,10:35; [para 0065]) has a derivative of zero with respect to linear displacement in any direction in a plane (annotated X,Y) of the interface (fig 4a).
Regarding claim 30.
Yanagita in view of Furuhashi teaches the method of claim 21, further:
Yanagita teaches the first bonding pad (fig 4a,10:45; [para 0065]) is coupled to a floating diffusion region (fig 3,10:FD; [para 0045]) of a photodetector (fig 3,10:PD1,PD2; [para 0045]).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yanagita (US 2015/0179691) in view of Furuhashi (US 2019/0386052) as applied to claim 21, and further in view Chen (US 2019/0123006).
Regarding claim 24.
Yanagita in view of Furuhashi teaches the method of claim 21.
Yanagita teaches the first bonding pad (fig 4a:45; [para 0065]) has a […] surface with a first major axis and a first minor axis; the second bonding pad (fig 4a:35; [para 0065]) has an […] surface with a second major axis and a second minor axis; and the first major axis lies across the second major axis (fig 4a).
Yanagita in view of Furuhashi does not teach the first and second surfaces are elliptical.
Chen teaches the oblong surfaces (110,120) are elliptical.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the oblong surface elliptical in order to avoid the stress concentrations at corners and thereby avoid crack nucleation points.
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yanagita (US 2015/0179691) in view of Furuhashi (US 2019/0386052) as applied to claim 21 and further in view of Ichikawa (US 2013/0092822).
Regarding claim 29
Yanagita in view of Furuhashi teaches the method of claim 21 above.
Yanagita in view of Furuhashi does not teach an array of pads
Ichikawa teaches the first bonding pad (fig 2:106; [para 0038]) is one of a plurality of first bonding pads (fig 7; [para 0104]) having like orientations and in a first array (fig 7); the second bonding pad (fig 2:105; [para 0038]) is one of a plurality of second bonding pads having like orientations and in a second array (fig 7); and the first bonding pads in the first array are bonded to respective second bonding pads in the second array (fig 7).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of he claimed invention to form the bond pads as part of an array of bond pads so that each photoelectric unit can comprise a separate connection to the controlling transistors and therefore enabling the readout for each pixel (Ichikawa; [para 0098]).
Claim(s) 32 and 41 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yanagita (US 2015/0179691) in view of Furuhashi (US 2019/0386052)
Regarding claim 32.
Yanagita teaches a method comprising: forming a [conductive] interconnect structure (fig 10:41; [para 0101]) over a first substrate (fig 10:9; [para 0101]), wherein: the [conductive] interconnect structure (fig 10:41; [para 0101]) comprises a bonding layer (fig 10:45; [para 0060]) and a [conductive] layer (fig 10:53,43,57; [para 0102]) immediately below the bonding layer (fig 10:45; [para 0060]); the bonding layer comprises a first bonding pad (fig 10:45; [para 0044]); and the [conductive] layer (fig 10:53,43,57; [para 0102]) comprises a [conductive] island (fig 10:43; [para 0050]) coupled to the first bonding pad (fig 10:45; [para 0060]), a first wire (fig 10:57; [para 0102]) next to the [conductive] island (fig 10:43; [para 0050]) on a first side, and a second wire (fig 10:57; [para 0102]) next to the [conductive] island (fig 10:43; [para 0050]) on an opposite side; the first bonding pad (fig 4a,10:45; [para 0044]) has a first surface and is oblong (fig 4a), whereby the first surface has a longer dimension and a shorter dimension (fig 4a); and the first bonding pad (fig 4a,10:45; [para 0065]) is oriented to maximize its distances from the first and second wires (fig 10:57; [para 0102]); forming a second bonding pad (fig 4a,10:35; [para 0060]) over a second substrate (fig 10:3; [para 0099]) wherein the second bonding pad (fig 4a,10:45; [para 0065]) has a second surface and is oblong (fig 4a), whereby the second surface has a longer dimension and a shorter dimension (fig 4a; [para 0065]); and aligning the first substrate (fig 10:9; [para 0099]) and the second substrate (fig 10:3; [para 0099]) and bonding (fig 3; [para 0044]) them together so that the first surface is against the second surface and the longer dimension of the first surface is oriented transversely relative to the longer dimension of the second surface (fig 4a,10).
Yanagita does not teach the conductive layers comprise metal.
Furuhashi teaches conductive interconnect structures (fig 3:35a,36,71; [para 0063]) formed of metal ([para 0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form conductive interconnect structure from metal due to the high conductivity of metal
Regarding claim 41.
Yanagita teaches the method of claim 32, wherein the distance between the first bonding pad (fig 8,10:45; [para 0044]) and the first wire (fig 10:57; [para 0101]) equal (center of the pixel; [para 0057]) the distance between the first bonding pad (fig 8,10:45; [para 0044]) and the second wire (fig 10:57; [para 0101]).
Claim(s) 33 and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yanagita (US 2015/0179691) in view of Furuhashi (US 2019/0386052) as applied to claim 32 and further in view of Ichikawa (US 2013/0092822).
Regarding claim 33
Yanagita in view of Furuhashi teaches the method of claim 32 above.
Yanagati teaches […] the first bonding pad (fig 10:45; [para 0044]) on the first substrate [fig 10:9; [para 0099]) is joined to […] the second bonding pad (fig 10:35; [para 0044]) of the second substrate (fig 10:3; [para 0099]), whereby the first surfaces of the first bonding pad (fig 10:45; [para 0044] are against the second surface of corresponding second bonding pad (fig 10:35; [para 0044]) with the longer dimensions of the first surfaces oriented transversely to the longer dimensions of the second surfaces (fig 4a).
Yanagita in view of Furuhashi does not teach an array of pads
Ichikawa teaches an array of the first bonding pads (fig 2:106; [para 0038]) on the first substrate (fig 7:701; [para 0096]) is joined to an array of the second bonding pads (fig 2:105; [para 0038]) of the second substrate (fig 7:702; [para 0096]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of he claimed invention to form the bond pads as part of an array of bond pads so that each photoelectric unit can comprise a separate connection to the controlling transistors and therefore enabling the readout for each pixel (Ichikawa; [para 0098]).
Regarding claim 34.
Yanagita in view of Furuhashi in view of Ichikawa teaches the method of claim 33, further:
Yanagita teaches forming photodiodes (fig 10:PD1,PD2; [para 0105]), transfer gates (fig 10:TRG; [para 0077]), and floating diffusion regions (fig 10:FD; [para 0104]) on the first substrate (fig 10:9; [para 0101]); and forming a [conductive] interconnect structure (fig 10:31; [para 0097]) that electrically couples each of the floating diffusion regions (fig 10:FD; [para 0104]) to a distinct one of the first bonding pads (fig 10:45; [para 0044]).
Yanagita does not teach the conductive layers comprise metal.
Furuhashi teaches conductive interconnect structures (fig 3:35a,36,71; [para 0063]) formed of metal ([para 0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form conductive interconnect structure from metal due to the high conductivity of metal
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Previous rejection of claims 27 and 34 under 35 USC 112(b), second paragraph have been withdrawn due to amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 6, 2026