DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 11/6/25 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-9, 12-14, 21, 22, 23, 25 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al US 2020/0312715 and further in view of Karta et al US 2009/0011543.
Pertaining to claim 1, Choi teaches a method of manufacturing a semiconductor device, the method comprising:
forming a first bonding layer 40 over a substrate 10+20 of a first wafer 1000, the first wafer comprising a first semiconductor die 100 and a second semiconductor die 200;
performing a first dicing process to form two grooves 530/540 that extend through the first bonding layer 40, the two grooves being disposed between the first semiconductor die and the second semiconductor die See Figure 5;
performing a second dicing process 610 to form a trench that extends through the first bonding layer 40 and partially through the substrate 10+20 of the first wafer 1000, wherein the trench is disposed between the two grooves See Figure 6 and [0070];
Choi teaches separating the first and second die using dicing [0076] Figure 7 and is silent regarding backside thinning as an option.
Karta teaches a process to separate two die by thinning a backside of the substrate of the wafer that includes a trench partially through, where the polishing occurs until the first semiconductor die is singulated from the second semiconductor die See Figure 1E and 1F as well as[0035]-[0037] for the purpose of creating a more reliable semiconductor IC device [0037] . It would have been within the scope of one of ordinary skill in the art at the time the invention was filed to combine the teachings of Choi and Karta to enable the die separation step of Choi to be performed according to the teachings of Karta because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed die separation step of Choi and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Pertaining to claim 3, Choi in view of Karta teaches the method of claim 1, wherein the two grooves 530/540 see Figure 5 also extend partially through the substrate 10+20 of the first wafer 1000. Note that the “substrate” is being defined as layers 10 AND 20 together, and that 530/540 extends at least partially into layer 20 of the substrate 10+20.
Pertaining to claim 4, Choi in view of Karta teaches the method of claim 3, wherein the two grooves have a first depth measured from a point that is level with a top surface of the first bonding layer to a bottom surface of the two grooves, and the trench has a second depth measured from a point that is level with a top surface of the first bonding layer to a bottom surface of the trench, and wherein the second depth is greater than the first depth. See Choi Figure 6 trench formed as illustrated is deeper than the trenches 530/540 illustrated in Figure 5. Also note that Karta teaches a similar two trench step method, the first trench not being as deep as the second formed trench, see Karta element 103 and element 106
Pertaining to claim 6, Choi in view of Karta teaches the method of claim 1, wherein the first dicing process comprises a plasma dicing process Karta teaches a first groove formation process 103 that uses a plasma process [0029], and the second dicing process comprises a blade dicing process Karta teaches a second dicing process to form 106 using a saw [0035].
Pertaining to claim 7, Choi in view of Karta teaches the method of claim 6, wherein the first dicing process comprises deep reactive ion etching (DRIE) using a fluorine plasma. Karta teaches reactive ion etching using a fluorine gas [0029] specifically CF4 containing gases which are the fluorine gases used in reactive ion etching
Pertaining to claim 8, Choi teaches a method of manufacturing a semiconductor device, the method comprising:
forming a first bonding layer 40 over a substrate of a first wafer 10+20, the first wafer 1000 comprising a plurality of top dies 210/220; and
singulating the first wafer to separate each of the plurality of top dies from other top dies of the plurality of top dies [0076] Figure 7, wherein singulating the first wafer comprises:
forming two grooves 530/540 that extend through the first bonding layer 40, the two grooves being disposed between adjacent top dies of the plurality of top dies See Figure 5;
forming a trench 610 along a dicing path that extends through the first bonding layer 40 and partially through the substrate 10+20 of the first wafer, wherein the dicing path extends into portions of the two grooves See Figure 6 and [0070];
Choi is silent with respect to thinning the backside to separate the two die and that the trenches are formed using plasma/saw respectively.
Karta teaches a process to separate two die by thinning a backside of the substrate of the wafer that includes a trench partially through, where the polishing occurs until the first semiconductor die is singulated from the second semiconductor die See Figure 1E and 1F as well as[0035]-[0037] for the purpose of creating a more reliable semiconductor IC device [0037] .
Karta teaches performing a plasma dicing process to form grooves that extend through the first bonding layer Karta teaches a first groove formation process 103 that uses a plasma process [0029]
performing a blade dicing process to form a trench along a dicing path that extends through the first bonding layer and partially through the substrate of the first wafer, wherein the dicing path extends into portions of the groove Karta teaches a second dicing process to form 106 using a saw [0035]
It would have been within the scope of one of ordinary skill in the art at the time the invention was filed to combine the teachings of Choi and Karta to enable the die separation step and trench formation steps of Choi to be performed according to the teachings of Karta because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed die separation and trench formation steps of Choi and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
9. (Original) The method of claim 8, wherein during the plasma dicing process the first bonding layer and top portions of the first wafer are removed in corner regions of each of the plurality of top dies. See Figure 5 marked up below
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Pertaining to claim 12, Choi in view of Karta teaches the method of claim 8, wherein the plasma dicing process comprises an etching process that uses fluorine plasma as an etchant. Karta teaches reactive ion etching using a fluorine gas [0029] specifically CF4 containing gases which are the fluorine gases used in reactive ion etching
Pertaining to claim 14, Choi in view of Karta teaches the method of claim 8, wherein performing the plasma dicing process comprises:
forming a first groove 530 of the two grooves adjacent to a first sidewall of a first top die 200 of the plurality of top dies; and
forming a second groove adjacent to a second sidewall of the first top die, wherein the first sidewall of the first top die is on an opposite side of the first top die as the second sidewall of the first top die. Choi only illustrates two die 100/200. However, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have more than two die on a wafer for a singulation process, whereas most dies have orders of magnitude more than that, and if one were to duplicate the parts, it would achieve that which is claimed in claim 14, where a single die has trenches adjacent either side of the die sidewall. See Figure 5 marked up below with additional die extrapolated to show where these trenches would be located. See In reHarza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a “web” which lies in the joint, and a plurality of “ribs” projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
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Pertaining to claim 21, Choi teaches a method of manufacturing a semiconductor device, the method comprising:
forming a first bonding layer 40 over a substrate 10+20 of a first wafer 1000, the first wafer 1000 comprising a first semiconductor die 100 and a second semiconductor die 200;
forming two grooves 530/540 in a top portion of the first wafer, wherein the two grooves are disposed between the first semiconductor die 100 and the second semiconductor die 200 see Figure 5;
forming a trench 610 see Figure 6 along a dicing path that extends through the top portion of the first wafer 1000, wherein the dicing path extends into portions of the two grooves See Figure 6; and
Choi teaches separating the first and second die using dicing [0076] Figure 7 and is silent regarding backside thinning as an option.
Karta teaches a process to separate two die by thinning a backside of the substrate of the wafer that includes a trench partially through, where the polishing occurs until the first semiconductor die is singulated from the second semiconductor die See Figure 1E and 1F as well as[0035]-[0037] for the purpose of creating a more reliable semiconductor IC device [0037] . It would have been within the scope of one of ordinary skill in the art at the time the invention was filed to combine the teachings of Choi and Karta to enable the die separation step of Choi to be performed according to the teachings of Karta because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed die separation step of Choi and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Pertaining to claim 22, Choi in view of Karta teaches the method of claim 21, wherein forming the two grooves in the top portion of the first wafer comprises performing a plasma dicing process using fluorine plasma as an etchant. Karta teaches a first groove formation process 103 that uses a plasma process [0029] using a fluorine gas [0029] specifically CF4 containing gases which are the fluorine gases used in reactive ion etching
Pertaining to claim 23, Choi in view of Karta teaches the method of claim 21, wherein forming the trench along the dicing path comprises performing a blade dicing process. Karta teaches a second dicing process to form 106 using a saw [0035].
Pertaining to claim 25, Choi in view of Karta teaches the method of claim 21, wherein after forming the trench, a bottom surface in the trench is lower than bottom surfaces in the two grooves. See Choi Figure 6 trench formed as illustrated is deeper than the trenches 530/540 illustrated in Figure 5. Also note that Karta teaches a similar two trench step method, the first trench not being as deep as the second formed trench, see Karta element 103 and element 106
Pertaining to claims 5, 13 and 26, Choi in view of Karta teaches the method of claims 1, 8 and 21, including wherein the width of the first and second groove is in a range from 10µm to 50µm Karta teaches that the wafer grooves 103 is preferably less than 60µm. [0035]-[0036]
Allowable Subject Matter
Claims 2, 10, 11 and 24 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pertaining to claims 2 and 24, the prior art does not teach nor suggest in combination wherein the additional method steps further comprise bonding the first semiconductor die and the second semiconductor die to a second wafer, wherein the first wafer comprises first bonding pads in the first bonding layer, wherein the second wafer comprises second bonding pads in a second bonding layer, and wherein the bonding comprises: bonding the first bonding pads to the second bonding pads using direct metal-to- metal bonding; and bonding the first bonding layer to the second bonding layer using direct oxide-to- oxide bonding.
Pertaining to claims 10 and 11, the prior art does not teach nor suggest in combination wherein the additional method steps further comprise wherein each of the corner regions is adjacent to a first sidewall of a corresponding top die of the plurality of top dies, wherein each first sidewall of the corresponding top die is adjacent to a second sidewall of the corresponding top die, wherein each first sidewall of the corresponding top die is also adjacent to a third sidewall of the corresponding top die, and wherein the first sidewall of the corresponding top die is slanted in a top down view such that it is not be disposed at a right angle relative to the second sidewall of the corresponding top die and the third sidewall of the corresponding top die.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817