DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-16 and 21-24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “mask” and “opening in the mask” of claim 21 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al. (US 2022/0139911 A1, hereinafter Wei ‘911) in view of the following arguments.
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With respect to Claim 1 Wei ‘911 discloses a method (Fig 1-8) for manufacturing a semiconductor structure, comprising:
forming (disclosed in Para [0066]) a fin (359, Fig 3C, Para [0066]) over a substrate (350, Fig 3C, Para [0066]) in a third direction (z direction as shown in Fig 3C), wherein the fin (359) comprises first semiconductor layers (356, FIG 3B, Para [0063]) and second semiconductor layers (354, Fig 3B, Para [0063]) alternately stacked (disclosed in Para [0063])(Fig 3C discloses fin 359 comprising 354 and 356);
forming (disclosed in Para [0068]) a dummy gate structure (361, Fig 3C, Para [0068]) extending in a second direction (x direction as shown in Fig 3C) and over the fin (359)(361 over 359 disclosed in Fig 3C);
growing (disclosed in Para [0089], an epitaxial deposition process, one of ordinary skill in the art would recognize epitaxial deposition as a “growth” process) a first epitaxial source/drain layer (left 366, Fig 3I, Para [0089]) and a second epitaxial source/drain layer (right 366, Fig 3I, Para [0089]) on opposite sides of the dummy gate structure (361) in a first direction (y direction as shown in Fig 3I)(Fig 3I discloses first and second source/drain features on opposite sides of 361), respective bottom surfaces of each of the first epitaxial source/drain layer (bottom of left 366) and the second epitaxial source/drain layer (bottom of right 366) extending below an uppermost surface (top of 350) of the substrate (350)(Para [0075] discloses an modification wherein each of the first and second openings (367-1 and 367-2) for the first and second epitaxial source/drain layer extend below the uppermost surface of substrate 350)
removing (disclosed in Para [0095] and Fig 3K) the dummy gate structure (361) and the first semiconductor layers (356)(Para [0095] discloses removing 356) in the fin (359) to form a gate trench (gate trench is not numbered in Figures, but Para [0095] discloses removing the dummy gate structure (361) and semiconductor layers (356) leaves an opening, hereinafter referred to as GT);
forming (disclosed in Para [0095]) a gate structure (371, Fig 3K, Para [0095]) in the gate trench (GT), wherein the gate structure (371) wraps around the second semiconductor layers (354)(Para [0096] discloses gate stack 371 wraps around 354, “…a portion of the first semiconductor material 354 of the nanoribbon 375-1 that is wrapped (at least partially) by the gate stack 371-2”); and
forming a via (364/383, Fig 3P, Para [0108]) in contact with the bottom surface (bottom of left 366 as shown in annotated Fig 3P of Wei ‘911) of the first epitaxial source/drain layer (left 366),
Wei ‘911 fails to expressly disclose wherein the bottom surface of the first epitaxial source/drain layer is a first distance below the uppermost surface of the substrate, the bottom surface of the second epitaxial source/drain layer is a second distance below the uppermost surface of the substrate, and the first distance is greater than the second distance. However, the examiner notes that Wei ‘911 appears to provide options (Para [0075]) for the depths of the first and second epitaxial source/drain layers below the uppermost surface of the substrate. Therefore, it would have been obvious to a person of ordinary skill in the art to arrive at the recited limitation of the first epitaxial source/drain layer is a first distance below the uppermost surface of the substrate, the bottom surface of the second epitaxial source/drain layer is a second distance below the uppermost surface of the substrate, and the first distance is greater than the second distance, to obtain the well-known advantage of having the bottom of the first/source drain region closer to the bottom of the substrate than the bottom surface of the second source/drain epitaxial layer, to reduce the amount of drilling time needed to create the opening for the backside via connection to the first source/drain epitaxial layer. See MPEP§2144.05 (II)(A),(B).
With respect to Claim 2 Wei ‘911 discloses all limitations of the method of claim 1, and Wei ‘911 discloses further wherein a ratio of a width (385, Fig 3S, Para [0115]) of the via (364/383) in the first direction (y direction) to a thickness (387-2, Fig 3S, Para [0115]) of the via (364/383) in the third direction (z direction) is greater than 1 (Fig 3S discloses 385 as larger than 387-2 therefore the ratio of 385:387-2 is greater than 1).
With respect to Claim 3 Wei ‘911 discloses all limitations of the method of claim 1, wherein the via (364/383) extends directly under the gate structure (371) in the third direction (z direction)(Fig 3S discloses 364/383 extending directly under gate spacers 362).
With respect to Claim 4 Wei ‘911 discloses all limitations of the method of claim 1, and Wei ‘911 further discloses wherein the formation of the via (364/383) comprises:
performing a chemical mechanical polishing process (Para [0102] discloses a CMP process to thin substrate) to thin the substrate (350);
removing the substrate (350) directly under the first source/drain feature (left 366) and a portion (one of ordinary skill in the art will recognize that the etch process to create the opening 379 (disclosed in Para [0106]) will remove at least a small amount, Å or more) of the first source/drain (left 366) feature to form an opening (379, Fig 3O, Para 0106]); and depositing a conductive material (378, Fig 3O, Para [0108]) in the opening (379) to form the via (364/383).
With respect to Claim 5 Wei ‘911 discloses all limitations of the method of claim 1, and Wei ‘911 further discloses wherein the via (364/383) has a substantially flat surface (Fig 3P discloses 364/383 has a flat surface as it contacts the first source/drain) in contact with the bottom surface (bottom of left 366 as shown in Fig 3P) of the first source/drain feature (left 366).
With respect to Claim 6 Wei ‘911 discloses all limitations of the method of claim 1, and Wei ‘911 further discloses wherein the formation of the first source/drain feature (left 366) and the second source/drain feature (right 366) comprises:
etching a first region (region of 367-1, Fig 3D, Para [0073]) of the fin (359) to form a first source/drain trench (367-1, Fig 3D, Para [0073]) in the first region (region of 367-1);
etching a second region (region of 367-2, Fig 3D, Para [0073]) of the fin (359) to form a second source/drain trench (367-2, Fig 3D, Para [0073]) in the second region (region of 367-2); and
forming (forming first and second source/drain features in trenches disclosed in Para [0089]) the first source/drain feature (left 366) in the first source/drain trench (367-1) and the second source/drain feature (right 366) in the second source/drain trench (367-2).
With respect to Claim 7 Wei ‘911 discloses all limitations of the method of claim 1, and Wei ‘911 further discloses wherein a length of the via (364/383) in the second direction (x direction) is greater than a length of the first source/drain feature (left 366) in the second direction (x direction)(upper image of 3O discloses left 366 does not extend the entire length of liner 364 in the x direction and the upper image of Fig 3R shows 364/383 extends the entire length of the x direction so length of 364/383 in the x direction is greater than a length of left 366 in the x direction).
With respect to Claim 8 Wei ‘911 discloses all limitations of the method of claim 1, wherein a distance from the bottom surface of the first source/drain feature (bottom of opening 353, Fig 3A, Para [0061] is the bottom of left 366) to the bottom surface of the second source/drain feature (top of opening 353, Fig 3A, Para [0061] is the bottom of right 366) in the third direction (z direction) is in a range from about 10 nm to about 50 nm.
Wei ‘911 teaches (dimension 355, Fig 3A, Para [0061] is the dimension of opening 353 in the z direction. Para [0061] discloses 355 ranges from 2nm to 50 nm therefore the distance, in the z direction, from bottom of left 366 to the bottom of right 366 covers the range of 10nm to 50nm). The instant application paragraph 0062 does not disclose any criticality to the claimed depth range. Wei ‘911 in paragraph 0115 teaches the dimensions are critical in the fabrication process of the via to connect to the source/drain feature. The entire range of 10-50nm would perform the same function of fabricating a via to connect to the source/drain feature. Because there is no allegation of criticality and no evidence demonstrating a difference across the range, Wei ‘911 discloses the claimed range with sufficient specificity. See MPEP section 2131.03.II. ClearValue Inc. v. Pearl River Polymers Inc., 668 F.3d 1340, 101 USPQ2d 1773 (Fed. Cir. 2012)).
Claims 9-16 are rejected under 35 U.S.C. 103 as being unpatentable over Wei ‘911 in view of Lee et al. (KR 2023-0108565 A, hereinafter Lee ‘565) in view of the following arguments.
With respect to Claim 9 Wei ‘911 discloses all limitations of the method of claim 1, and but Wei ‘911 fails to explicitly disclose comprising:
forming a source/drain contact over and electrically connected to the first source/drain feature.
Nevertheless, in a related endeavor (Fig 1-20b of Lee ‘565), Lee ‘565 teaches forming (formation of 195 disclosed in Para [0142] of Lee ‘565) a source/drain contact (195, Fig 19a of Lee ‘565, Para [0142]) over (disclosed in Fig 19a) and electrically connected to (Para [0142] of Lee ‘565 discloses making a conductive connection between 195 and 150A) the source/drain feature (150A, Fig 14a, Para [0121])).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘565’s teaching forming a source/drain contact over and electrically connected to the first source/drain feature into Wei ‘911’s method. Wei ‘911 teaches a method for manufacturing a semiconductor device and teaches methods to form contacts to that device but it is silent on the formation of a via over the source/drain feature. Lee ‘565 teaches a method for forming a semiconductor device and further teaches the formation of vias over the source/drain features. The ordinary artisan would have been motivated to modify Wei ‘911 in the manner set forth above, at least, because as Lee ‘565 teaches in Para [0066] these vias enable signals to be sent to the source/drain areas which would increase the functionality of the device.
As incorporated, the teaching of forming a via over source/drain (150A) of Lee ‘565 would be used to form a source/drain contact over the first source/drain feature (left 366) in the method of Wei ‘911.
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With respect to Claim 10 Wei ‘911 discloses a method (Fig 1-8) for manufacturing a semiconductor structure, comprising:
forming (disclosed in Para [0066]) fins (359, Fig 3C, Para [0066] discloses a plurality of 359) over a substrate (350, Fig 3C, Para [0066]) in a third direction (z direction as shown in Fig 3C), wherein each of the fins (359) comprises first semiconductor layers (356, FIG 3B, Para [0063]) and second semiconductor layers (354, Fig 3B, Para [0063]) alternately stacked (disclosed in Para [0063])(Fig 3C discloses fin 359 comprising 354 and 356;
forming (disclosed in Para [0068]) a dummy gate structure (361, Fig 3C, Para [0068]) extending in a second direction (x direction as shown in Fig 3C) and over the fins (359)(361 over 359 disclosed in Fig 3C);
forming (disclosed in Para [0089]) first source/drain features (left 366, Fig 3I, Para [0089]) and second source/drain features (right 366, Fig 3I, Para [0089]) in the fins (359) (Fig 3C-3I discloses forming first and second source/drain features in fins 359), wherein a thickness (thickness of first source/drain from top to bottom as shown in annotated Fig 3I of Wei ‘911, hereinafter tfsd) of the first source/drain features (left 366) is greater than a thickness (thickness of second source/drain from top to bottom as shown in annotated Fig 3I of Wei ‘911, hereinafter tssd) of the second source/drain features (right 366)(thickness of first source/drain greater than thickness of second source/drain shown in annotated Fig 3I of Wei ‘911 and disclosed in Para [0075]),
Wei ‘911 fails to expressly disclose such that the first source/drain features extend to a depth below a bottommost surface of a bottommost first semiconductor layer of the first semiconductor layers and the second source/drain features extend to a second depth below the bottommost surface of the bottommost first semiconductor layer. However, the examiner notes that Wei ‘911 appears to provide options (Para [0075]) for the depths of the first and second epitaxial source/drain features below the bottommost surface of a bottommost first semiconductor layer. Therefore, it would have been obvious to a person of ordinary skill in the art to arrive at the recited limitation of the first source/drain feature extends to a depth below the bottommost surface of a bottommost first semiconductor layer and the second source/drain feature extends to a second depth below the bottommost surface of the bottommost first semiconductor layer, to obtain the well-known advantage of having the bottom of the first/source drain region closer to the bottom of the substrate than the bottom surface of the second source/drain epitaxial layer, to reduce the amount of drilling time needed to create the opening for the backside via connection to the first source/drain epitaxial layer. See MPEP§2144.05 (II)(A),(B).
removing (disclosed in Para [0095] and Fig 3K) the dummy gate structure (361) and the first semiconductor layers (356)(Para [0095] discloses removing 356) in the fins (359) to expose (Para [0095] discloses354 exposed during process) the second semiconductor layers (354);
forming (disclosed in Para [0095]) a gate structure (371, Fig 3K, Para [0095]) wrapping around the second semiconductor layers (354)(Para [0096] discloses gate stack 371 wraps around 354, “…a portion of the first semiconductor material 354 of the nanoribbon 375-1 that is wrapped (at least partially) by the gate stack 371-2”); and
forming vias (364/383, Fig 3P, Para [0108]) in contact with the first source/drain features (left 366 as shown in Fig 3P), wherein a width (a width of 364/383 in y direction is shown in annotated Fig 3P of Wei ‘911) of the vias (364/383) in a first direction (y direction as shown in Fig 3P) is greater than a thickness (a thickness of 364/383 in a direction is shown in annotated Fig 3P of Wei ‘911) of the vias (364/383) in the third direction (z direction as shown in Fig 3P)(annotated Fig 3P of Wei ‘911 discloses width of 364/383 in first direction is greater than a thickness of 364/383 in third direction).
But Wei ‘911 fails to explicitly disclose forming an isolation structure between the fins; the dummy gate structure extending in a second direction and over the isolation structure and forming vias in contact with the first source/drain features and the isolation structure.
Nevertheless, in a related endeavor (Fig 1-20b of Lee ‘565), Lee ‘565 teaches forming an isolation structure (110, Fig 2b of Lee ‘565, Para [0025]) between the fins (105/140/120/121, Fig 9b of Lee ‘565, Para [0100], hereinafter FINS)(Fig 2b of Lee ‘565 discloses 110 between FINS); the dummy gate (200, Fig 13a of Lee ‘565, Para [0116]) structure extending in a second direction (x direction as shown in Fig 13b of Lee ‘565) and over the isolation structure (110)(dummy gate 200 over 110 and FINS disclosed in Fig 13b of Lee ‘565) and forming vias (182/185, Fig 20a of Lee ‘565, Para [0148]) (Para [0145–0148] of Lee ‘565 disclose making an opening (via) OP and subsequently filling the via) in contact with the source/drain features (150, Fig 14A of Lee ‘565, Para [0121]) and the isolation structure (110)(arrangement disclosed in Fig 20a and 20b of Lee ‘565),
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘565’s teachings of forming an isolation structure between the fins; the dummy gate structure extending in a second direction and over the isolation structure and forming vias in contact with the first source/drain features and the isolation structure into Lee ‘565’s device. Wei ‘911 teaches a method for manufacturing a semiconductor device and teaches the substrate upon which the device is built can have different forms, including a silicon-on-insulator structure (Para [0039], but Wei’995 is silent on the details of those substrate compositions. Lee ‘565 teaches a method for forming a semiconductor device and further teaches the formation of insolation structures within the device. The ordinary artisan would have been motivated to modify Lee ‘565 in the manner set forth above, at least, because including the isolation layer on the substrate would provide additional dielectric protection for the device against parasitic capacitance.
As incorporated, the isolation structure (110) of Lee ‘565 would be formed between the fins (359 of Wei ‘911) so that the dummy gate structure (361 of Wei ‘911) extending in a second direction and over the isolation structure (359 of Wei ‘911) and therefore the vias (364/383 of Wei ‘911) would be in contact with the first source/drain features (left 366) and the isolation structure (110 of Lee ‘565) as incorporated in the device Wei ‘911.
With respect to Claim 11 Wei ‘911 as modified by Lee ‘565 discloses all limitation of the method of claim 10, and Wei ‘911 discloses further wherein forming the vias (364/383) results in the first source/drain features (left 366) having substantially flat bottom surfaces (Fig 3P discloses 364/383 has a flat surface as it contacts the flat surface of first source/drain, left 366).
With respect to Claim 12 Wei ‘911 as modified by Lee ‘565 discloses all limitation of the method of claim 10, and Wei ‘911 further discloses wherein forming the vias (364/383) comprises forming a first via (364/383, Fig 3P, Para [0108]) extending from the gate structure (371) to an adjacent gate structure (center gate 371 as shown in Fig 3R)(Fig 3R discloses via 364/383 extend from gate spacer of left 371 to gate spacer of center 371).
With respect to Claim 13 Wei ‘911 as modified by Lee ‘565 discloses all limitation of the method of claim 10, and Wei ‘911 further discloses wherein forming the first source/drain features (left 366) and the second source/drain features (right 366) comprises forming the first source/drain features (left 366) and the second source/drain features (right 366) each having at least two sidewalls (left and right sides of left 366 and right 366) in contact with respective gate spacers (362 of gates 371)(Fig 3R discloses left and right sides of left 366 and right 366 contact two sidewalls (spacers 362) of gates 371).
With respect to Claim 14 Wei ‘911 as modified by Lee ‘565 discloses all limitation of the method of claim 13, wherein forming the vias comprises forming the vias (vias 364/383) that extend beyond the respective gate spacers (right spacer 362 of leftmost gate structure 371 and left spacer 362 of center gate structure 371) there above along the second direction (x direction)(upper image of Fig 3R discloses via 364/383 extends in second direction x and the lower image of Fig 3R shows that via 364/383 extends over the right spacer 362 of the leftmost 371 and the right spacer 362 of the center 371).
With respect to Claim 15 Wei ‘911 as modified by Lee ‘565 discloses all limitations of the method of claim 10, and Wei ‘911 further discloses wherein forming the vias comprises forming the vias (364/383) having square profile in a top view (upper image of Fig 3R)(upper image of Fig 3R discloses 364/383 as having a square profile),
But Wei ‘911 as modified by Lee ‘565 fails to explicitly disclose the width of the vias being in a range from about 6 nm to about 200 nm.
Nevertheless, Wei ‘911 does teach, in Para [0115], provides teachings for the dimensions of the via (364/383) to enable a connection to source/drain feature.
However, Applicant has not presented persuasive evidence that the claimed the width of the vias being in a range from about 6 nm to about 200 nm is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed range). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (MPEP 2144.04 IV)
Therefore, it would be obvious to a person having ordinary skill in the art, before the effective filing date, absent unexpected results to use the width of the vias being in a range from about 6 nm to about 200 nm is critical to the overall claimed invention. As stated above, Wei ‘911 teaches that the via should be of sufficiently small diameter to connect the source bottom surface. Therefore, the width of the via being in a range from about 6 nm to about 200 nm would be obvious to one of ordinary skill in the art as a result of routine experimentation to use the width of the via to from a sufficiently small diameter to connect the source bottom surface as taught by the method of Wei ‘911 as modified by Lee ‘565.
As described above, the width of the via as being between 6 nm to 200 nm would be incorporated in the width of via 185 in the method of as modified by Lee ‘565.
With respect to Claim 16 Wei ‘911 as modified by Lee ‘565 discloses all limitations of the method of claim 10, and Wei ‘911 as modified by Lee ‘565 further discloses wherein the formation of the vias comprises:
removing the substrate (350) (Para [0102] discloses a CMP process to remove substrate 350); and
forming the vias (formation of 364/383 disclosed in Para [0108]) in the substrate (350) and in contact with (Fig 3P and Para [0108] discloses 364/383 in contact with left 366) the first source/drain features (left 366) and the isolation structure (110 of Lee ‘565 as incorporated in Wei ‘911)(as incorporated the isolation structure would be over the substrate, therefore the vias 364/383 would be in contact with that isolation structure).
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Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Wei ‘911 in view of Wang et al. (US 2021/0343639A1, hereinafter Wang ‘639) in further view of Morrow et al. (US 2018/0248012 A1, hereinafter Morrow ‘012) in view of the following arguments.
With respect to Claim 21 Wei ‘911 discloses a method (Fig 1-8), comprising:
forming a stack (357, Fig 3B, Para [0063]) comprising alternately stacked first nanostructures (356, Fig 3B, Para [0063]) and second nanostructures (354, Fig 3B, Para [0063])(Para [0018 and 0063] disclose stack comprised of nanoribbons);
forming (disclosed in Para [0089]) a first source/drain trench (367-1, Fig 3D, Para [0073]) adjacent the stack (357)(357 adjacent to 367-1 shown in Fig 3D), the first source/drain trench (367-1) extending to a first depth (first depth of 367-1 shown in annotated Fig 3D of Wei ‘911, hereinafter fd);
a second source/drain trench (367-2, Fig 3D, Para [0073])(367-2 formed after 367-1 disclosed in Para [0073]) adjacent the stack (357)(357 adjacent to 367-2 shown in Fig 3D) opposite the first source/drain trench (367-1)(Fig 3D shows 367-2 opposite 367-1 relative to 357) relative to the stack (357), the second source/drain trench (367-2) extending to a second depth (second depth of 367-1 shown in annotated Fig 3D of Wei ‘911, hereinafter sd) different than the first depth (annotated Fig 3D of Wei ‘911 discloses fd and sd are different);
forming a first source/drain feature (left 366, Fig 3I, Para [0089]) in the first source/drain trench (367-1) and a second source/drain feature (right 366, Fig 3I, Para [0089]) in the second source/drain trench (367-2);
forming (disclosed in Para [0095]) a gate structure (371, Fig 3K, Para [0095]) wrapping around the second nanostructures (354)(Para [0096] discloses gate stack 371 wraps around 354, “…a portion of the first semiconductor material 354 of the nanoribbon 375-1 that is wrapped (at least partially) by the gate stack 371-2”);
forming a via opening (379, Fig 3N, Para [0105]) exposing a bottom surface (bottom of left 366 as shown in Fig 3N) of the first source/drain feature (left 366);and
forming a second via (364/383, Fig 3P, Para [0108]) in the opening (379).
But Wei ‘911 fails to expressly disclose while the first source/drain trench is covered by a mask, etching through an opening in the mask to form a second source/drain trench.
Nevertheless, in a related endeavor (Fig 1-24C of Wang ‘639), Wang ‘639 teaches while the first source/drain trench (right most trench R1, Fig 7B of Wang ‘639, Para [0046]) is covered by a mask (P3, Fig 8 of Wang ‘639, Para [0049]), etching (disclosed in Para [0050} of Wang ‘639) through an opening (opening in P3 above R3 as shown in Fig 8 of Wang ‘639) in the mask (P3) to form a second source/drain trench (R3, Fig 8 of Wang ‘639, Para [0050]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Wang ‘639’s teaching of while the first source/drain trench is covered by a mask, etching through an opening in the mask to form a second source/drain trench into Wei ‘911’s method. The ordinary artisan would have been motivated to modify Wei ‘911 in the manner set forth above, at least, because a person of ordinary skill in the art would recognize that covering one etched recess when etching a second recess of a different depth would protect the first recess from further etching which would change the targeted depth of the first recess.
As incorporated, the teaching of Wang ‘639 of covering one recess while the second recess is etched would be incorporated into Wei ‘911’s method so that the first source/drain trench (367-1 of Wei ‘911) would be covered by the mask (P3 of Wang ‘639) while etching through an opening of the mask (P3 of Wang ‘639) to form a second source/drain trench (367-2) of Wie ‘911.
But Wei ‘911 as modified by Wang ‘639 fails to explicitly disclose forming a first via on an upper surface of the first source/drain feature;
Nevertheless, in a related endeavor (Fig 1-2p of Morrow ‘012), Morrow ‘012 teaches forming a first via (220, Fig 2iA of Morrow ‘012, Para [0029]) on an upper surface of the first source/drain feature (218, Fig 2iA of Morrow ‘012, Para [0029]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Morrow ‘012’s teachings of forming a first via on an upper surface of the first source/drain feature into Wei ‘911 as modified by Wang ‘639’s method. The ordinary artisan would have been motivated to use the taught method of Morrow ‘012 of forming a via on an upper surface of the first source/drain in the method of Wei ‘911 as modified by Wang ‘639 in the manner set forth above, at least, because as Morrow ‘012 teaches in Para [0020] “The …contacts of the embodiments herein provide interconnect structures for both above and below a device layer, within the footprint of the device”, thereby providing a proven way to integrate the device and providing additional electrical connects to the device which would also ease its’ integration into a larger device.
As incorporated, the forming an upper via (220 of Morrow ‘012) would be used above the first source/drain (left 266 of Wei ‘911).
With respect to Claim 22 Wei ‘911 as modified by Wang ‘639 and further modified by Morrow ‘012 discloses all limitation of the method of claim 21, and Wei ‘911 further discloses wherein forming the second source/drain trench (367-2) results in a difference between the second depth (sd) and the first depth (fd) being in a range of about 10 nm to about 50 nm.
Wei ‘911 teaches (dimension 355, Fig 3A, Para [0061] discloses the additional depth of the first depth (fd). Para [0061] discloses 355 ranges from 2nm to 50 nm the difference between fd and sd covers the range of 10nm to 50nm). The instant application paragraph 0062 does not disclose any criticality to the claimed depth range. Wei ‘911 in paragraph 0115 teaches the dimensions are critical in the fabrication process of the via. The entire range of 10-50nm would perform the same function of fabricating a via. Because there is no allegation of criticality and no evidence demonstrating a difference across the range, Wei ‘911 discloses the claimed range with sufficient specificity. See MPEP section 2131.03.II. ClearValue Inc. v. Pearl River Polymers Inc., 668 F.3d 1340, 101 USPQ2d 1773 (Fed. Cir. 2012)).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Wei ‘911 in view of Wang ‘639, in view of Morrow ‘012 and in further view of Lee ‘565, in view of the following arguments.
With respect to Claim 23 Wei ‘911 as modified by Wang ‘639 and further modified by Morrow ‘012 discloses all limitation of the method of claim 21, and Wei ‘911 as modified by Morrow ‘012 further discloses wherein forming the second via comprises forming the second via (364/383) having a first sidewall taper (sidewall taper of 364/383 as shown in Fig 3P)
But Wei ‘911 as modified by Wang ‘639 and further modified by Morrow ‘012 fails to explicitly disclose that is different than a second sidewall taper of the first via.
Nevertheless, in a related endeavor (Fig 1-20b of Lee ‘565), Lee ‘565 teaches a second sidewall taper (Para [0066] of Lee ‘565 teaches a sidewall inclined to decrease in width toward the source drain).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘565’s teaching of a second sidewall taper for the first via in the method of Wei ‘911 as modified by Wang ‘639 and further modified by Morrow ‘012. The ordinary artisan would have been motivated to modify Wei ‘911 as modified by Wang ‘639 and further modified by Morrow ‘012 in the manner set forth above, at least, because using a sidewall inclined to decrease in width toward the source drain would prevent unwanted contact of the via with other structures thereby increasing the yield and/or reliability of the device.
As incorporated, the sidewall inclined to decrease in width toward the source drain taught by Lee ‘565 would be used as the shape of the first via (220 of Morrow ‘012 as incorporated in Wei ‘911) and that shape is different than the straight sides of the second via 364/383 of Wei ‘911 as modified by Wang ‘639 and further modified by Morrow ‘012.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Wei ‘911 in view of Wang ‘639 in view of Morrow ‘012 and in further view of Chu et al. (US 2021/0391421 A1, hereinafter Chu ‘421), in view of the following arguments.
With respect to Claim 24 Wei ‘911 as modified by Wang ‘639 and further modified by Morrow ‘012 discloses all limitation of the method of claim 21, but Wei ‘911 as modified by Wang ‘639 and further modified by Morrow ‘012 fails to explicitly disclose further discloses wherein forming the second via comprises forming the second via extending into the first source/drain feature by a second distance less than a first distance to which the first via extends into the first source/drain feature.
Nevertheless, in a related endeavor (Fig 21B of Chu ‘421), Chu ‘421 teaches comprises forming the second via (282, Fig 21B of Chu ‘421, Para [0052] extending into the first source/drain feature (260’, Fig 21B of Chu ‘421, Para [0050] by a second distance less than a first distance to which the first via (275, Fig 20C and Fig 21B of Chu ‘421, Para [0041]) extends into the first source/drain feature (260’)(Fig 21B of Chu ‘421 discloses contact 275 penetrates into the source/drain 260’ deeper that the contact 282 penetrates into 260’).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chu ‘421’s teachings the second via extending into the first source/drain feature by a second distance less than a first distance to which the first via extends into the first source/drain feature into Wei ‘911 as modified by Wang ‘639 and further modified by Morrow ‘012’s method. The ordinary artisan would have been motivated to use the second via extending into the first source/drain feature by a second distance less than a first distance to which the first via extends into the first source/drain feature as taught by Chu ‘421 in the method of Wei ‘911 as modified by Wang ‘639 and further modified by Morrow ‘012 in the manner set forth above, at least, because using the via connections taught by Chu ‘421 present a proven method to make an electrical interconnection “beneficially reducing the contact resistance” as taught in Para [0051] of Chu ‘421.
As incorporated, the teaching of Chu ‘421 wherein the second via (282 of Chu ‘421) extension into the first source/drain is less than the first via (275 of Chu ‘421) extension into the first source/drain would be incorporated in the first (220 of Morrow ‘012 as incorporated in Wei ‘911 as described above) and second via (364/383 or Wei ‘911) connections into the first source/drain feature (left 366) of Wei ‘911 as modified by Wang ‘639 and further modified by Morrow ‘012.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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